Unified Generation of Analog Sizing and Placement … Universität München Institute for Electronic...

Technische Universität MünchenInstitute forElectronic Design Automation

Unified Generation of Analog Sizing and Placement Constraints

Michael Eick and Helmut Graeb

Institute for Electronic Design AutomationProf. Dr.-Ing. Ulf Schlichtmann

Technische Universität München

Overview

• Analog constraints

• Unified constraint generation flow– Universal constraint graph– Sizing and placement constraint generation

• Experimental results

• Conclusion

Constraints in Design Flow

specification

structure

sizing

placement

routing

analog block

sizing constraints

placement constraints

routing constraints

process variations,parasitic devices etc.

structural analysis

Matching Constraints - Sizing

[Hastings, The Art of Analog Layout]

equal lengths

fixed ratio (optional)

current matching (optional)

voltage matching (optional)

limited Vgs, Vds mismatch

Matching Constraints - Placement

[Hastings, The Art of Analog Layout]

equal finger geometriesequal orientationclose proximity

common centroid

quadratic common centroid

More Constraints

Operating Point Constraintslinear / saturation region

Symmetric Place & Route Constraints

State of the Art

sizingconstraints

Massier et al. TCAD’08

placementconstraints

sensitivityanalysis

building blockanalysis

symmetryanalysis

Eick et al. TCAD’11

Kole et al. ISCAS’94 Hao et al. ICCCS’04

Malavasi et al. TCAD’96 Chen et al. IEE Proc. G’92

Abstract constraint management concepts [Jerke et al. ISPD’09]

Structural Analysis

Building Block Analysis[Massier et al. TCAD’08]

• comparison with library• ambiguity resolution

Symmetry Analysis[Eick et al. TCAD’11]

• Structural Signal Flow Graph• propagation of symmetry pairs

currentmirror

differential pair

Unified Constraint Generation Flow

netlist

building blocks

symmetrical devices

universal constraintgraph

sizing constraints

Overview

• Conclusion

Universal Constraint Graph (UCG)

Edge Constraint Attributes

proximity

operating pointrobust operation

region: linear, saturation

matchinggrade: minimal, moderate, maximaltype: undefined, voltage, i currentratio: variable, fixed(value)

symmetry

Undirected Graph• Nodes: Devices• Edges:

UCG Generation - Overview

building blocks

netlist

symmetrical devices

Edge Constraint

proximity

op. point / robust op.

matching

symmetry

UCG Generation - Netlist

building blocks

netlist

symmetrical devices

Edge Constraint

proximity

matching

symmetry

UCG Generation – Building Blocks

min,i,v min,i,v

max,v,f(1)

building blocks

netlist

symmetrical devices

Edge Constraint

proximity

matching

symmetry

UCG Generation - Symmetry

building blocks

netlist

symmetrical devices

Edge Constraint

proximity

matching

symmetry

mod,u,f(1)

Unified Constraint Generation Flow

netlist

building blocks

symmetrical devices

universal constraintgraph

sizing constraints

Sizing Constraint Generation

operating point

linear saturation

matching

minimal moderate maximal

general

current voltage

variable ratio fixed ratio

robust operation

Edge Constraint

proximity

matching

symmetrygeneral

Sizing Constraint Examples

operating point

linear saturation

matching

general

current voltage

variable ratio fixed ratio (q=1)

robust operationgeneral

Placement Constraint Generation

proximity

matching

minimal moderate perfect

general

variable ratio fixed ratio

symmetric placement

Edge Constraint

proximity

matching

symmetry

general

Placement Constraint Examples

proximity

matching

general

variable ratio fixed ratio (q=1)

symmetric placement

general

Overview

• Conclusion

Experimental Results - Placement

Schematic Layout

A0 [dB] 72 dB 72 dB

fT [MHz] 12.9 MHz 12.6 MHz

CMRR [dB] 138 dB 144 dB

Voffset [mV] 0.008 mV 0.3 mV

Yield [%] 99.0 % 98.8 %

Conclusion

• Knowledge of constraints necessary for (automatic) design of analog circuits

• Unified constraint generation flow– Structural analysis– Universal constraint graph– Generation of sizing and placement constraints

Unified Generation of Analog Sizing and Placement … Universität München Institute for Electronic...

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