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October 2002 ISSS
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1Center for Research on Embedded Systems and Technology (CREST), http://crest.ece.gatech.edu
2Assistant 3Professor, 1Electrical and Computer Engineering2Adjunct Assistant Professor, College of ComputingGeorgia Institute of Technology, Atlanta, GA USA
44Tallin Technical University, Tallin, Estonia
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory
KiranKiran PuttaswamyPuttaswamy11, , KyuKyu--Won ChoiWon Choi11, Jun , Jun CheolCheol ParkPark11,,Vincent J. MooneyVincent J. Mooney IIIIII1,1,22, , AbhijitAbhijit ChatterjeeChatterjee1,1,33 and and Peeter Peeter EllerveeEllervee44
{{kiranpkiranp, , kwchoikwchoi, , jcparkjcpark, chat, , chat, mooneymooney}@ece.gatech.ed}@ece.gatech.eduulrvlrv@cc.@cc.ttuttu..eeee
2Hardware/Software Hardware/Software CodesignCodesign Group, http://Group, http://codesigncodesign..eceece..gatechgatech..eduedu
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Overview
• Introduction• Motivation• Contribution• Framework• Methodology• Results
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Introduction
• Embedded Systems –essential components of living
• Constraining Factor: Power
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Motivation
• Limited Battery Capacity
• Battery Energy Supplying Characteristic10 mA , 1.5 volts = 1000 hours100 mA, 1.5 volts = 80 hours
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Previous Work
• Three broad approaches to memory optimization for power/energy reduction– Cache optimizations– Memory access reduction (especially of off-chip memory)– Memory sizing/structuring and memory intensive voltage
scaling
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Our Contribution
• Combination of an architectural technique (store buffer) and a circuit level technique (voltage and frequency scaling) to realize savings in both power and energy in an embedded system composed of an ARM-like processor chip plus a separate memory chip
• System savings in power from 28% to 36%• System savings in energy from 13% to 35%
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Computation Part of an Embedded System
CPU
Datacache
Instruction cache
Off-ChipMemory
64
96
32
32
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Power Models
• Verilog RTL model for processor (excluding caches)• Compaq Personal Server PCB Board called “Skiff”• Analytical memory model for caches and off-chip
memory
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Framework
Benchmark Programs ( c )
Off-Chip Memory Power Model
Toggle Rate Generation
MARS Simulator
VHX Translation
Processor Core Power Model Off-chip Bus Power Model
System Level Power
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Wither the power?• Computation in system
– MARS processor (U. Michigan, www.eecs.umich.edu/~jringenb/power)• ~30K lines Verilog
– synthesized using TSMC .25u std. cell lib. from LEDA Systems
• 4KB Icache, 4KB Dcache
– 0.5MB SRAM memory chip (L2)
• Approximately 50% of the power consumed by processor chip (excluding I/O pads and drivers)
• 50% of the power consumed to drive L2 memory: the 0.5MB memory chip + PCB bus + I/O pads/drivers
• => reduce power to drive L2 memory by 60%, system power reduced 30%
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3.3 V -> 2V, SRAMdelay doubles, powerreduces up to 66%
Use TSMC 0.25 utech. param. from
MOSIS
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Embedded System
CPU
Datacache
Instruction cache
Off-ChipMemory
64
96
32
32
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Embedded System (with Store Buffer)
CPU
Datacache
Instruction cache
Off-ChipMemory
64
96
32
32
Store buffer
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Methodology
• Voltage/frequency scaling of L2 memory accesses• Store buffer technique
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Voltage/Frequency Scaling
Processor Off-chip Memory
Off-chip Buses
3.3 Volts, 100 Mhz2.75 Volts, 100 Mhz
3.3 V, 100 Mhz
2 Volts, 50 Mhz
2 Volts, 50 Mhz
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Conclusion
• Reduction in both power and energy – For an ARM-like processor chip plus a separate memory chip:– System savings in power from 28% to 36%– System savings in energy from 13% to 35%– Increase in execution time from 1% to 29%
• Possible technique for power modulation by user/application
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