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8/2/2019 Synchronization Enhancement Using IEEE 1588
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Synchronization enhancement
using IEEE 1588
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CONTENTS
Introduction
Problem Definition
Aim
Design Approach
Implementation
Result observations
Conclusion
References
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Introduction Data communication in industries are defined by a
fixed structured network.
These networks uses Physical link for Datacommunication.
More accurate than wireless networks.
Cost effective under distributed system havingsensitive data transmission.
commonly used in industrial communication.
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Problem Definition
Even though wired network are currently been usedfor reliable data transfer they are non-synchronous innature due to multiple sources.
In industry multiple units transfer informationsimultaneously.
Synchronizing these multiple links result ininconsistency problem.
Inconsistency result in wrong operation reducingsystemperformance.
Priority based or FCFS communication results indelayed communication.
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Aim
To develop an approach for simultaneous datatransfer in multi source design in a faster way.
Develop IEEE-1588 standards to realize a fast
mode of communication. To develop a Best Master clock approach for high
speed clock synchronization.
To develop the approach for Ethernet linkpoints
with multiple nodepoints. To develop the data communication model with
and without synchronizingprotocol for timeperformance evaluation.
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Design Approach
For the realization of the suggested approach
following communication architecture is been
used as mentioned.
communication Model:
Network
Processor
LP
LP
LP
LP
IU
IU
IU
IU
IU-Individual
UnitsLP-linkpoints
(Ethernet links)
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Links are the communication points for NP
from IU. They consist of Ethernet communication logic.
Each linkpoint get synchronized from the NP
unit individually. Communicate with NP using Internet protocol.
Each source communicate with the receiving
point at different data rate. Networkprocessor is synchronized with the
individual linkpoints using their existing
operational time period.
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In case of a network having sensors output
which are more sensitive for operation a delaymay result in a abrupt operation.
To achieve a faster data transfer thesenetworks are designed with a newsynchronizingprotocol called IEEE-1588protocol.
IEEE-1588protocol is a clock synchronization
protocol under different source modecommunication.
The protocol works on the concept of the bestmaster clock operation.
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IEEE 1588 SYNCHRONIZATION
The synchronization of the 1588protocol isdefined as;
Step 1: Organize the clocks into a master-slave
hierarchy (based on observing the clockpropertyinformation contained in multicast Syncmessages)
Step 2: Each slave synchronizes to its master
(based on Sync, delay_Req, Follow-Up, and Delay_ Resp messages
exchanged between master and its slave)
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Offset and Delay measurement
For the chosen delay all the slave clocks are updated to this
offset value to synchronize the received data into a common
master clock frequency.
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SYNCHRONIZATION APPROACH
For the synchronization of the nodes a communicationapproach is suggested as explained;
Sync Messages:
Issued by clocks in the Master state
Contain clock characterization information Contain an estimate of the sending time (~t1)
When received by a slave clock the receipt time is noted
Can be distinguished from other legal messages on the
network For best accuracy these messages can be easily
identified and detected at or near the
physical layer and the precise sending (or receipt) time
recorded.
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Follow-Up messages:
Issued by clocks in the Master state Always associated with the preceding Sync
message
Contain the precise sending time= (t1)as
measured as close as possible to the physical layer of the network
When received by a slave clock the precisesending time is used in computations rather
than the estimated sending time contained in theSync message
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Delay_Req Messages:
Issued by clocks in the Slave state
The slave measures and records the sending time(t3)
When received by the master clock the receipttime is noted (t4)
Can be distinguished from other legal messageson the network
For best accuracy these messages can be easilyidentified and detected at or near the
physical layer and the precise sending (or receipt) time recorded
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Delay_Resp messages:
Issued by clocks in the Master state Always associated with a preceding Delay_Req
message from a specific slave clock
Contain the receipt time of the associated
Delay_Req message (t4) When received by a slave clock the receipt time
is noted and used in conjunction with
the sending time of the associated Delay_Req
message aspart of the latency calculation
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MASTER CLOCK SELECTION
A clock at startup listens for a time Sync_receipt_timeout
A master clock (clock in the PTP_MASTER state) issuesperiodic Sync messages
(period is called the sync interval)
A master clock may receive Sync messages from other clocks(who for the moment
think they are master) which it calls foreign masters
Each master clock uses the Best Master Clock algorithm todetermine whether it should
remain master or yield to a foreign master.
Each non-master clock uses the Best MasterClock algorithm todetermine whether it should become a master.
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SYSTEM DESIGN
For the development of the suggested designarchitecture the a multi port Ethernet points with
link unit is used as shown below.
Ethernet
Transmitter 1
Ethernet
Transmitter2
Ethernet
Transmitter 3
Ethernet
Transmitter 4
Ethernet
Receiver 1
Ethernet
Receiver2
Ethernet
Receiver 3
Ethernet
Receiver 4
Interface
LINK
Network
Processor
(IEEE 1588)
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LINKPOINT
The Linkpoints are designed with the Ethernet logic.The transmission block is as shown below;
F_enH
O
S
T
FIFO
CRC
GeneratorFrame
Builder
Parallel
-Serial
ControllerDatalength
rd/wr
Crc_en Fr_en status
P2s_en
S_out
Transmission Unit
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The Ethernet unit communicate using the
data frame structure as shown below;
SOFPreamble
Type Source
Address
Destination
AddressData
Length
EOF
3 bits 7 bits 4 bits 8 bits 8 bits 4 bits variable 2 bits
Data
Start-of-frame delimiter (SOF) The SOF is an alternating pattern of ones and
zeros, ending with two consecutive 1-bits indicating that the next bit is the left-most
bit in the left-most byte of the destination address.
Preamble (PRE)The PRE is an alternating pattern of ones and zeros that tells
receiving stations that a frame is coming, and that provides a means to synchronizethe frame-reception portions of receiving physical layers with the incoming bit
stream.
TypeThe Type field is used to indicate if the packet is control packet or datapacket.
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Source addresses (SA) The SA field identifies the sending station.The SA is always an individual address and the left-most bit in the SAfield is always 0.
Destination address (DA) The DA field identifies which station(s)should receive the frame. The left-most bit in the DA field indicateswhether the address is an individual address (indicated by a 0) or agroup address (indicated by a 1). The second bit from the left indicateswhether the DA is globally administered (indicated by a 0) or locallyadministered (indicated by a 1). The remaining 46 bits are a uniquelyassigned value that identifies a single station, a defined group ofstations, or all stations on the network.
LengthThis field indicates either the number ofMAC-client data bytesthat are contained in the data field of the frame
DataIs a sequence of n bytes of any value, where n is less than or equal to 8.
Frame check sequence (FCS)This sequence contains a 32-bit cyclicredundancy check (CRC) value, which is created by the sending MACand is recalculated by the receiving MAC to check for damagedframes. The FCS is generated over the DA, SA, Length/Type, and
Data fields.
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Receiver unit
Serial-
parallel FIFOFrame
reader
Address
match
logic
crc
checker
controller
S_in
S2p_en Rd/wr F_en Fr_en Match
FCS
Crc_en
Crc_err
Ethernet receiver receives the data frame and the frame reader is used to divide
the frame into the 7 fields transmitted.
Address match logic is used to match the destination address with the address of
the receiver and if it matches then only the frame is accepted.
CRC checker is used to check for the faults in the data frame and if any then the
frame is discarded.
Controller is used to deliver control signals to all the units at correct intervals so
that the receiverperforms its operation correctly.
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Communication Unit With IEEE-1588
Ethernet
Transmitter 1
Ethernet
Transmitter2
Ethernet
Transmitter 3
Ethernet
Transmitter 4
Ethernet
Receiver 1
Ethernet
Receiver2
Ethernet
Receiver 3
Ethernet
Receiver 4
Network
Processor
Synchronization Unit
Clock Generation Unit
LINK
INTERFACE
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Frame format for IEEE-1588 protocol
SOF
Preamble
Type Source
AddressDestination
Address
DataEOF
Synchronization
Time
stampProp
delay
3 bits 7 bits 4 bits 8 bits 8 bits 8 bits 7 bits 4 bits 2 bits
The frame consists of2 internal fields one is the time stamp
and the second is the propagation delay.
These two fields specify the two values that is the offset value
and the propagation delay value of the slave clocks from the
master clock.
The devices which receive this packet will take these two
fields and corrects its clock to the master clock.
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Result observations
Simulation result of the communication model showing the
communication time for the designed unit in a non-synchronized mode.
The observed time for the communication of 4 nodes data to
the receiver unit is observed as, 5580ns.
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Simulation result of the communication model showing the
communication time for the designed unit with synchronization
Protocol.
The observed time for the communication of 4 nodes data to
the receiver unit is observed as, 1445ns.
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Observations
dlc=3bytes Best master clock (BMC)= min ( tstamp )
Default clock = ck1 (under asynchronous mode communication )
Frequency selection method = round robin
Total number of communicating nodes = 4
Total amount of data generatedper node = 3 bytes Total amount of expected data in processor = 12bytes
Total time taken = 5580 ns (under non synchronous round robin basedcomm)
(total time = processing time + comm Time)
Total time taken = 1445 ns (under 1588 synchronous mode comm) Total time saved (ts)= 4135 ns
Total clock cycles saved = ts / BMC
= 4135 / 10 413 cycles
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Implementation
Logical Implementation of the developed system on targeted
FPGA. (xc3s1500-5fg456)
without IEEE 1588 with IEEE 1588
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Conclusion
The IEEE 1588protocol has been designed, verifiedfunctionally in the VHDL simulator, and synthesized onXilinx Project Navigator 9.1.
The functional verification were made and the total
communication time were observed.
It is observed that the system with IEEE-1588protocolworks at a faster rate as compared to the existing system.
The overall resource required for the implementation is
about 5000 gate count more than the existing link units.
The operable frequency with which the system canoperate underpractical condition is observed to be68.885MHz.
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References
[1] IEEE 1588* in NetworkProcessors for Next-GenerationIndustrial Automation Solutions, Puneet Sharma, Technical
Marketing Engineer, Digital Enterprise Group, Intel Corporation,
May 2005.
[2] Special Focus: Understanding the IEEE 1588 Precision TimeProtocol Developer Zone, National Instruments, February
2006..
[3] Hardware-Assisted IEEE 1588* Implementation in the Intel
IXP46X Product Line, White Paper, March 2005.
[4] IEEE 1588 : Running Real-time on Ethernet, Dirk.S.Mohl,
Hirschmann Electronics, The Online Industrial Ethernet Book,
Issue 17, November2003.
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Thank You
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