Signal Integrity Simulation and Equivalent Circuit Modeling

Tzong-Lin Wu

Department of Electrical EngineeringNational Taiwan University

Taipei, Taiwanwtl@cc.ee.ntu.edu.tw

NTU OutlineIntroduction

Signal Integrity Simulation in SPICEA case Study: Driver Board of TFT Display Panel

TDR Concept and Layer Peeling Technique (one port)

Macro-model Synthesis for Coupled Discontinuities of Signal Path (two-port)

Challenge of SI Modeling for Real PCB and Package

Summary

Introduction

With rapidly increased clock rate and denser interconnect layout, noise caused by the discontinuities can be a critical factor to degrade the signal integrity (SI) of circuit systems.

Example: Via coupling

TDTVCoupling

0 2E-011 4E-011 6E-011 8E-011 1E-010 1.2E-010t (s)

-0.005

olt) Signal rising time

100ps50ps20ps10ps

Introduction

Extracting SPICE-compatible models for thosediscontinuities are essential.

Benefits:1. More convenient integration with chip circuits

under SPICE environment.2. Better accuracy with higher order of equivalent circuits.

NTU Case Study: Driver Board of TFT Display

Time Controller (T-CON)

Driver IC

Driver PCB

NTU Case Study: Driver Board of TFT Display

Objectives of this project: Signal integrity modeling for the driver PCB and compare with the measured results.

Approaches:Establishing SPICE-compatible model for all interconnects and doing SI simulation on HSPICE.

IC I/O Buffer ModelSPICE modelIBIS model

Driver IC Driver IC Driver IC

Case Study: Driver Board of TFT Display -- HSPICE Approach

via3via3

Differential line (no GND)

Differential line(with GND)

FPCFPC FPC

Step 1: Trace all interconnects from driver (T-CON) to receiver (driver IC)

Differential line (with GND)

Step 2: Extract SPICE Compatible models for each partitioned interconnects byAnsoft Q3D (Differential signals)

via3via3

FPCFPC FPC

via1. via2.

Step 2: Extract SPICE Compatible models for each partitioned interconnects byAnsoft Q3D (Differential Via Holes)

Via Macro-model (type 1)

Via Macro-model (type 2)

via3via3

FPCFPC FPC

Step 2: Extract SPICE Compatible models for each partitioned interconnects byAnsoft Q3D (Flexible PCB)

Substrate : polyimide

Differentialline

•Line pitch : 0.028mm•Substrate : polyimide (εr 3.5)•Thickness : 0.038mm

軟板軟板

via2via3 via3

TCON(IBIS . spice)

open open open

Case1 : Open circuit for the receiver side (Driver IC)Using SPICE and IBIS models for transmitted side (T-CON)

Measuring Probes

軟板

Step 4: Comparison between modeling and measurement

SpiceIBISmeasurement

Case1 : Open circuit for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)

Driver IC

軟板軟板

via2via3 via3

TCON(IBIS . spice)

Driver(IBIS)

訊號觀測點

Driver IC軟板

Driver(IBIS)

軟板

Driver(IBIS)

Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)

Summary

TDR basic theory

2 d cablet

open circuit

load circuit

short circuit0

2 stepV1Γ =

1Γ = −

Coaxial cable

stepV rV

stT eDR p rV V V= +

DUT Time-DomainReflectometry (TDR)

(1 )TDR step r stepV V V V= + = + Γ ⋅ ( ) ( )0 0/L LZ Z Z ZΓ = − +

20 2005/6/18

TDR theory

capacitive dip

inductive peak

Coaxial cable

stepV rV

stT eDR p rV V V= +

DUT Time-DomainReflectometry (TDR)

TDR theory

Fig. Source: HP TDR

Layer Peeling Technique (LPT)

1x1ZdT

1, ja−

1, jb−

( )I t

,i ja−

,i jb−

,i jb +

,i ja+

, 1i jb

+, 1i j

( )V t

0Z 2Z1Z

1X 2X 3X

X←Δ →

1ix +( )inV t

bZ ZZ Z a

−−

−Γ ≡ =

+ ( )1

, ,2 2

1i j i ji

iii j i j

+ −−

⎡ ⎤ ⎡ ⎤−Γ⎡ ⎤= −Γ⎢ ⎥ ⎢ ⎥⎢ ⎥−Γ⎢ ⎥ ⎢ ⎥⎣ ⎦⎣ ⎦ ⎣ ⎦

1, , 1

i j i j

− ++

− ++ +

=( ) ( )( ) ( )

1 1i i i i i i

i i i ii i

Z a b Z a b

a b a bZ Z

− − + +−

− − + +

− = −

23 2005/6/18

Layer Peeling Technique (LPT) Begin

Z Z −+ Γ

=− Γ

, ,2 2

1i j i ji

iii j i j

+ −−

⎡ ⎤ ⎡ ⎤− Γ⎡ ⎤= − Γ⎢ ⎥ ⎢ ⎥⎢ ⎥− Γ⎣ ⎦⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

−Γ =

⇒1, 1

− −

0 50, 1Z i= =

1, ,i j i ja a− ++ =

1, , 1i j i jb b− ++ += 1,2,3, ,j N i= −

1,2,3, ,j N i= −

1, ja−

1, jb−

( )I t

,i ja−

,i jb−

,i jb +

,i ja+

, 1i jb

+, 1i j

( )V t

0Z 2Z1Z

1X 2X 3X

X←Δ →

1ix +( )inV t

24 2005/6/18

Layer Peeling Technique (LPT)

0 1 2 3 4 5 6 7t (ns)

70 ohm

100 ohm

40 ohm50 ohm

Summary

262005/6/18

shorting vias

Differential via

ICThrough-hole via

Broadband Macro-Models of Differential Via

Port 1

Port 2

0LR Z=

Terminatted traces

Anti-Pad

Via-Pad

trace1

trace2

trace3

trace4

Step responses and macro-PI model

Step response : : incident wave: reflected wave: stimulative port: detected port

: step responsemn

1( ) exp( )

mn mn mn

iy t r p t

== −∑

: residues

: poles: mode numbers

Pencil of matrix method

29 2005/6/18

11 22 12 21 11 22 12 210

11 22 12 21 11 22 12 21

0 21 21

(1 )(1 ) (1 )(1 )2 2

1 (1 )(1 ) (1 )(1 )2 2

ZA BC D

ξ ξ ξ ξ ξ ξ ξ ξξ ξ

+ − + + + −⎡ ⎤⎢ ⎥⎡ ⎤ ⎢ ⎥=⎢ ⎥ − − − − + +⎢ ⎥⎣ ⎦⎢ ⎥⎣ ⎦

[ ]1 2 31 1 1D AM M M

B B B− −⎡ ⎤= ⎢ ⎥⎣ ⎦

( ) ( ) ( )( ) ( )

( ) ( ) ( )

11 22 12 21 211

0 11 22 12 21

11 22 12 21 212

0 11 22 12 21

(1 )(1 ) 21(1 )(1 )

1 2 (1 )(1 )

ξ ξ ξ ξ ξξ ξ ξ ξ

ξξ ξ ξ ξ

− + + −+ + −

+ − + −+ + −

=+ + −

Lapalace transformation:

( )mnL i

mnmn i

rs ss p

=+∑Impulse response:

Port 1

Port 2

Step responses and macro-PI model

( )0 1 1 *

1 1 10 1 1 1 1

( )( ) ( )

( )i i iN i N i N i

k k ki ii i i i i

k k kk k k k k

r r rM s s Ks s j s j

sα α β α β= = =

++ + + + −

= + +∑ ∑ ∑

mnL imn

mn ii mn

ry ss p=

30 2005/6/18

Order reduction

( )0 1 1 *

1 1 10 1 1 1 1

( )( ) ( )

( )i i iN i N i N i

k k ki ii i i i i

k k kk k k k k

++ + + + −

= + +∑ ∑ ∑

( )0 1

1 10 1 1

( ) ( )

i ik k

N i N ik k

i i i ik kk k k

r D r D

ii ik k k

r rM s ss s j

r Ks j

sα α β

= =≥ ≥

∑ ∑

: 0.1% ~ 5% maximum residueD

We define a parameter D for mode selection

31 2005/6/18

Passivity criterion

* *Re{ } Re{ } 0P V I V YV= = ≥

3M 12Y−

11 12Y Y+22 12Y Y+

1 3 311 12

3 2 321 22

M M MY YY

M M MY Y+ −⎡ ⎤⎡ ⎤

= = ⎢ ⎥⎢ ⎥ − +⎣ ⎦ ⎣ ⎦

11 1 3

12 21 3

22 2 3

Y M MY Y M

= += = −

= +1 3 3

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

Systematic lumped-model extraction technique (SLET)

( )( )( )

K Ki i i

i ii ii i iq v

q rs v P sM s s s Ks h s u s m Q s= =

+= + + +

+ + +∑ ∑

( )0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k

i ii i i i ik k kk k k k k

r D r D r D

≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

1 2 0 31/ 0K K Z K= = =

33 2005/6/18

( )( )( )

i ii iq v

s P sM s s s Ks s s m

q r vuh Q s= =

+= + + +

+ + +∑ ∑

Li Cii

⎛ ⎞= −⎜ ⎟

⎝ ⎠

2 ( ) ( )i

i i i i i

i i i L

L i i C i i C L i i L

sLC C RY s

s R LC R LC s R R C L R+

=+ + + +

( )( )

ii iq v

qP s ss s r vu

KQ s s s s mh= =

+= + +

+ + +∑ ∑

iC2 ( )

( ) iCV s+ −

iCRiCR

2 ( )iLV s

( ) iCV s+ −

2 ( )iCV s ( )

iLV s+ −

ii Li Ci

i Li iCi i i

i i i i

vC R Rm r

r R rR u Lv C C m

−= = −

⎛ ⎞ ⋅= + =⎜ ⎟ ⋅⎝ ⎠

3M +−

2 ( )LV s

2 ( )CV s

( )CV s+

-( )LV s

2 ( )CV s

( )CV s

Port 1

Port 2

Port 3

Port 4

Flow chart

1( ) exp( )

mn mn mn

iy t r p t

== −∑

TDR or FDTD

( ) ( ) ( )( ) ( )

( ) ( ) ( )

11 22 12 21 211

0 11 22 12 21

11 22 12 21 212

0 11 22 12 21

(1 )(1 ) 21(1 )(1 )

1 2 (1 )(1 )

ξ ξ ξ ξ ξξ ξ ξ ξ

ξξ ξ ξ ξ

− + + −+ + −

+ − + −+ + −

=+ + −

( )0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k

i i i i i ik k kk k k k k

r D r D r D

≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

Port 1

Port 2

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

Example: asymmetric vias

LR LR4.3rε =

Transmission line 50 OhmPort 2

S = 3 mil

Port 1

Port 3 Port 4

Coupling Vias

Port 1

Port 2

Eigen-values profile of asymmetric vias

0.1 1 10GHz

asymmetric vias£f1£f2

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

39 2005/6/18

Stability

( )0 1

1 10 1 1

( ) ( )

i ik k

N i N ik k

i i i ik kk k k

r D r D

ii ik k k

r rM s ss s j

r Ks j

sα α β

= =≥ ≥

∑ ∑

Time-domain response – V11

0 10 20 30 40 50 60 70 80t (ps)

3D-FDTDextracted model mode 54extracted model mode 44

( )0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k

r D r D r D

≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

LR LR4.3rε =

S = 3 mil

Port 1

Port 3 Port 4

Coupling Vias

Time-domain response – V12 & V22

0 10 20 30 40 50 60 70 80t (ps)

3D-FDTDextracted model mode 54extracted model mode 44

-0.015

-0.005

V12 & V

21 (volt)

( )0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k

r D r D r D

≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

LR LR4.3rε =

S = 3 mil

Port 1

Port 3 Port 4

Coupling Vias

0 5 10 15 20 25 30GHz

3D-FDTD S11extracted model mode 54extracted model mode 44

0 5 10 15 20 25 30GHz

Frequency-domain response - S11 & S21

0 5 10 15 20 25 30GHz

LR LR4.3rε =

S = 3 mil

Port 1

Port 3 Port 4

Coupling Vias

0 5 10 15 20 25 30GHz

LR LR4.3rε =

S = 3 mil

Port 1

Port 3 Port 4

Coupling Vias

Example: Differential via

S = 3 mil

Port 1

LR LR4.3rε =

Port 3 Port 4

Differential Vias

Port 1

Port 2

Eigen-values profile of differential vias

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

0.1 1 10GHz

Differential via£f1£f2

Time-domain response – V11 & V21

0 10 20 30 40 50 60 70 80t (ps)

3D-FDTDextracted model

V12 & V

21 (volt)

0 5 10 15 20 25 30GHz

3D-FDTD S11extracted model S11

0 5 10 15 20 25 30GHz

3D-FDTD S11extracted model

0 5 10 15 20 25 30GHz

)3D-FDTD S21extracted model

48 2005/6/18

0 5 10 15 20 25 30GHz

Summary

NTU Challenge of Modeling the Real PCB and Package

4-layer Motherboard for Desktop Computer (PCB)

NTU Challenges for Modeling the Real PCB and Package

Top side

Bottom side

4-layer Motherboard for Desktop Computer (PCB)

4-layer BGA Package, 37.5mm ×

37.5mm, 788 pin balls

Ground Layer (layer 2)

Power Layer (layer 3)

Real PCB and Packages

1. Several thousands traces routed on a PCB.2. Several thousand through hole vias3. Perforated power and ground planes4. Irregular power/ground planes partitions.

In SI simulation, we need to think

How accurate you need?How complicated your circuits are?How much (computing) resources you have?

Material Characteristics:

1. Substrate: Broadband information of dielectric constant and loss tangent.

2. Conductor: frequency dependent loss (skin effect)

( ) ( ) ( )' ''f f j fε ε ε= −

NTUChallenges for Modeling the Real PCB and Package in High-speed Circuits

Signal Propagation Characteristics:

1. Signal line referred to the perforated power or ground planes.

2. Broadband single (differential) via models

Power distribution networks characteristics

Challenges: (how accurate?)• Power/ground ring with shorting vias• Thousands of via holes on power/ground planes• Vertical interconnects modeling and linking between package and PCB• Mutual coupling between package and PCB

Power Network Pre-drive

Circuits

( )VDD sig shot pd clampI I I I I≅ + + +

IBIS Model for Power Noise modeling

Isig are considered in IBIS model (pull up and pull down current)

The pre-drive current Ipd and shot-through current Ishot are not considered in IBIS model

NTUChallenges for Modeling the Real PCB and Package in High- speed Circuits

IBIS Model for SSN modeling

Pull up current

Pre-drive current

NTU Summary

As an example, a driver PCB for TFT display panel is modeled by two approaches. One is using commercial SI design tool, and the other is based on the HSPICE environment by constructing equivalent SPICE-compatible models.

TDR concept and layer peeing technique for extracting equivalent circuit models is introduced based on time domain response.

A synthesis approach for macro equivalent circuit model for coupled discontinuity is also discussed.

Challenges for SI design tool in modeling the real PCB and package in high-speed circuits are discussed. They includes material characteristics, signal propagation characteristics, power distribution networks, and IBIS model for SSN.

Signal Integrity Simulation and Equivalent Circuit Modeling

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