Signal Integrity Simulation and Equivalent Circuit Modeling

NTU

Signal Integrity Simulation and Equivalent Circuit Modeling

Tzong-Lin Wu

Department of Electrical EngineeringNational Taiwan University

Taipei, [email protected]

NTU OutlineIntroduction

Signal Integrity Simulation in SPICEA case Study: Driver Board of TFT Display Panel

TDR Concept and Layer Peeling Technique (one port)

Macro-model Synthesis for Coupled Discontinuities of Signal Path (two-port)

Challenge of SI Modeling for Real PCB and Package

Summary

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3

Introduction

With rapidly increased clock rate and denser interconnect layout, noise caused by the discontinuities can be a critical factor to degrade the signal integrity (SI) of circuit systems.

Example: Via coupling

stepV

TDTVCoupling

0 2E-011 4E-011 6E-011 8E-011 1E-010 1.2E-010t (s)

-0.005

0

0.005

0.01

0.015

0.02

0.025

V TD

T (v

olt) Signal rising time

100ps50ps20ps10ps

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4

Introduction

GND

Power

Extracting SPICE-compatible models for thosediscontinuities are essential.

Benefits:1. More convenient integration with chip circuits

under SPICE environment.2. Better accuracy with higher order of equivalent circuits.

NTU Case Study: Driver Board of TFT Display

Time Controller (T-CON)

Driver IC

Driver PCB

NTU Case Study: Driver Board of TFT Display

Objectives of this project: Signal integrity modeling for the driver PCB and compare with the measured results.

Approaches:Establishing SPICE-compatible model for all interconnects and doing SI simulation on HSPICE.

IC I/O Buffer ModelSPICE modelIBIS model

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TCON

Driver IC Driver IC Driver IC

Case Study: Driver Board of TFT Display -- HSPICE Approach

via1

via2

via3via3

Differential line (no GND)

Differential line(with GND)

FPCFPC FPC

Step 1: Trace all interconnects from driver (T-CON) to receiver (driver IC)

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GND

Differential line (with GND)


Step 2: Extract SPICE Compatible models for each partitioned interconnects byAnsoft Q3D (Differential signals)


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TCON




via1

via2

via3via3

FPCFPC FPC

via1. via2.


Step 2: Extract SPICE Compatible models for each partitioned interconnects byAnsoft Q3D (Differential Via Holes)

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2

1

34

via1.

12

3

4

Via Macro-model (type 1)

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via2.

Via Macro-model (type 2)

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TCON


via1

via2

via3via3



FPCFPC FPC


Step 2: Extract SPICE Compatible models for each partitioned interconnects byAnsoft Q3D (Flexible PCB)

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Substrate : polyimide

Differentialline

•Line pitch : 0.028mm•Substrate : polyimide (εr 3.5)•Thickness : 0.038mm

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TCON



軟板軟板

via1

via2via3 via3

TCON(IBIS . spice)

open open open

Case1 : Open circuit for the receiver side (Driver IC)Using SPICE and IBIS models for transmitted side (T-CON)

Measuring Probes

軟板

open

via2

軟板

100Ω


Step 4: Comparison between modeling and measurement

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-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

SpiceIBISmeasurement


Case1 : Open circuit for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)


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TCON

Driver IC



軟板軟板

via1

via2via3 via3

TCON(IBIS . spice)

Driver(IBIS)

訊號觀測點

Driver IC軟板

Driver(IBIS)

via2

軟板

Driver(IBIS)

100Ω

Driver(IBIS)


Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)


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Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)







Summary

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19

TDR basic theory

2 d cablet

open circuit

load circuit

short circuit0

stepV

2 stepV1Γ =

0Γ =

1Γ = −

Coaxial cable

TDRV

stepV rV

stT eDR p rV V V= +

DUT Time-DomainReflectometry (TDR)

(1 )TDR step r stepV V V V= + = + Γ ⋅ ( ) ( )0 0/L LZ Z Z ZΓ = − +

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20 2005/6/18

TDR theory

0Z 0Z

0Z0Z

C

L

0

stepV

capacitive dip

0

stepV

inductive peak

Coaxial cable

TDRV

stepV rV

stT eDR p rV V V= +

DUT Time-DomainReflectometry (TDR)

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21

TDR theory

Fig. Source: HP TDR

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22

Layer Peeling Technique (LPT)

1x1ZdT

1, ja−

1, jb−

( )I t

2x2Z

dT

3xdT

ixiZ

dT

,i ja−

,i jb−

,i jb +

,i ja+

, 1i jb

+

+, 1i j

a+

+

( )V t

0Z 2Z1Z

1X 2X 3X

X←Δ →

1iZ +

1ix +( )inV t

sZ

,11

1 ,1

ii ii

i i i

bZ ZZ Z a

−−

−−

−Γ ≡ =

+ ( )1

, ,2 2

, ,

11

1i j i ji

iii j i j

a a

b b

+ −−

+ −

⎡ ⎤ ⎡ ⎤−Γ⎡ ⎤= −Γ⎢ ⎥ ⎢ ⎥⎢ ⎥−Γ⎢ ⎥ ⎢ ⎥⎣ ⎦⎣ ⎦ ⎣ ⎦

1, ,

1, , 1

i j i j

i j i j

a a

b b

− ++

− ++ +

=

=( ) ( )( ) ( )

1

1

1 1i i i i i i

i i i ii i

Z a b Z a b

a b a bZ Z

− − + +−

− − + +

−

+ = +

− = −

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23 2005/6/18

Layer Peeling Technique (LPT) Begin

i=N?

i=i+1

End

111

ii i

i

Z Z −+ Γ

=− Γ

( )1

, ,2 2

, ,

11

1i j i ji

iii j i j

a a

b b

+ −−

+ −

⎡ ⎤ ⎡ ⎤− Γ⎡ ⎤= − Γ⎢ ⎥ ⎢ ⎥⎢ ⎥− Γ⎣ ⎦⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

,1

,1

ii

i

ba

−

−Γ =

TDR

in

VV

⇒1, 1

1, 1

j

j

a a

b b

− −

− −

=

=

0 50, 1Z i= =

1, ,i j i ja a− ++ =

1, , 1i j i jb b− ++ += 1,2,3, ,j N i= −

1,2,3, ,j N i= −

1x

1ZdT

1, ja−

1, jb−

( )I t

2x2Z

dT

3xdT

ixiZ

dT

,i ja−

,i jb−

,i jb +

,i ja+

, 1i jb

+

+, 1i j

a+

+

( )V t

0Z 2Z1Z

1X 2X 3X

X←Δ →

1iZ +

1ix +( )inV t

sZ

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24 2005/6/18

Layer Peeling Technique (LPT)

TDRV

0 1 2 3 4 5 6 7t (ns)

0.05

0.1

0.15

0.2

0.25

0.3

V TD

R (v

olt)

0 1 2 3 4 5 6 7t (ns)

20

30

40

50

60

70

80

90

100

110

Line

Impe

danc

e (O

hm)

70 ohm

100 ohm

40 ohm50 ohm






Summary

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262005/6/18

shorting vias

Differential via

SG

IC

GS

ICThrough-hole via

Broadband Macro-Models of Differential Via

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27

Broadband Macro-Models of Differential Via

LR

1M

2M

3M

Port 1

Port 2

0LR Z=

0Z 0Z

stepV

Terminatted traces

Anti-Pad

Via-Pad

trace1

trace2

trace3

trace4

TDRV

TDRV

TDTV

TDTV

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28

Step responses and macro-PI model

Step response : : incident wave: reflected wave: stimulative port: detected port

: step responsemn

abnmy

( )im

mn in

by ta

=

1( ) exp( )

mni i

mn mn mn

L

iy t r p t

== −∑

: residues

: poles: mode numbers

imn

imn

mnL

rp

Pencil of matrix method

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29 2005/6/18

11 22 12 21 11 22 12 210

21 21

11 22 12 21 11 22 12 21

0 21 21

(1 )(1 ) (1 )(1 )2 2

1 (1 )(1 ) (1 )(1 )2 2

ZA BC D

Z

ξ ξ ξ ξ ξ ξ ξ ξξ ξ

ξ ξ ξ ξ ξ ξ ξ ξξ ξ

+ − + + + −⎡ ⎤⎢ ⎥⎡ ⎤ ⎢ ⎥=⎢ ⎥ − − − − + +⎢ ⎥⎣ ⎦⎢ ⎥⎣ ⎦

[ ]1 2 31 1 1D AM M M

B B B− −⎡ ⎤= ⎢ ⎥⎣ ⎦

( ) ( ) ( )( ) ( )

( ) ( ) ( )( ) ( )

( ) ( ) ( )

11 22 12 21 211

0 11 22 12 21

11 22 12 21 212

0 11 22 12 21

213

0 11 22 12 21

(1 )(1 ) 21(1 )(1 )

(1 )(1 ) 21(1 )(1 )

1 2 (1 )(1 )

M sZ

M sZ

M sZ

ξ ξ ξ ξ ξξ ξ ξ ξ


ξξ ξ ξ ξ

− + + −+ + −

+ − + −+ + −

=+ + −

=

=

Lapalace transformation:

1

( )mnL i

mnmn i

i mn

rs ss p

ξ=

=+∑Impulse response:

LR

LR1M

2M

3M

Port 1

Port 2

0Z 0Z

Step responses and macro-PI model

( )0 1 1 *

0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i iN i N i N i

k k ki ii i i i i

k k kk k k k k

r r rM s s Ks s j s j

sα α β α β= = =

++ + + + −

= + +∑ ∑ ∑

( )1

mnL imn

mn ii mn

ry ss p=

=+∑

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30 2005/6/18

Order reduction

( )0 1 1 *

0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i iN i N i N i

k k ki ii i i i i

k k kk k k k k



++ + + + −

= + +∑ ∑ ∑

( )0 1

0 1

1

1

0 1

1 10 1 1

*1

1 1 1

( )

( ) ( )

(

)

i i

i ik k

i

ik

N i N ik k

i i i ik kk k k

r D r D

N ik

ii ik k k

r D

r rM s ss s j

r Ks j

sα α β

α β

= =≥ ≥

=≥

+ + +

+ −

= +

+ +

∑ ∑

∑

: 0.1% ~ 5% maximum residueD

We define a parameter D for mode selection

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31 2005/6/18

Passivity criterion

* *Re{ } Re{ } 0P V I V YV= = ≥

1M 2M

3M 12Y−

11 12Y Y+22 12Y Y+

1 3 311 12

3 2 321 22

M M MY YY

M M MY Y+ −⎡ ⎤⎡ ⎤

= = ⎢ ⎥⎢ ⎥ − +⎣ ⎦ ⎣ ⎦

11 1 3

12 21 3

22 2 3

Y M MY Y M

Y M M

= += = −

= +1 3 3

3 2 3

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

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32

Systematic lumped-model extraction technique (SLET)

0 1

21 1

0 0

( )( )( )

i i

K Ki i i

i ii ii i iq v

q rs v P sM s s s Ks h s u s m Q s= =

> >

+= + + +

+ + +∑ ∑

( )0 1 1

0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k

i ii i i i ik k kk k k k k

r D r D r D



≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

1 2 0 31/ 0K K Z K= = =

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33 2005/6/18


0 1

21 1

0 0

( )( )( )

i i

K K

i ii iq v

i

i

i

i i

i

s P sM s s s Ks s s m

q r vuh Q s= =

> >

+= + + +

+ + +∑ ∑

1

1Ci

Ci i

RY ss

R C

=+

1

1

Ci

iCi

i

i

R

C

q

h R

=

=

iC

iCRiC

iCR

iLRiL

1

1

i

Cii

Li Cii

Lii

i i

i

i

ii

i

i

vm

ruv

C

RC

R R

RL

rr

C m

=

⎛ ⎞= −⎜ ⎟

⎝ ⎠

= −

⋅=

⋅

2 ( ) ( )i

i i i i i

i i i L

L i i C i i C L i i L

sLC C RY s

s R LC R LC s R R C L R+

=+ + + +

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34


32

21 1

0 0

( )( )

i i

i i

i

KK

ii iq v

i

i

i

qP s ss s r vu

KQ s s s s mh= =

< <

+= + +

+ + +∑ ∑

iC2 ( )

iCV s

( ) iCV s+ −

iCRiCR

2 ( )iLV s

L

iLR

iC

( ) iCV s+ −

2 ( )iCV s ( )

iLV s+ −

1

1

Cii

ii Ci

Rq

Ch R

=

−=

1

1

ii Li Ci

i i

i Li iCi i i

i i i i

vC R Rm r

r R rR u Lv C C m

−= = −

⎛ ⎞ ⋅= + =⎜ ⎟ ⋅⎝ ⎠

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35

1M

2M

3M +−

+−

+−

+−

+−

+−

+−

+−

+−

2 ( )LV s

+-

+-

2 ( )CV s

( )CV s+

-

+

-( )LV s

+-

2 ( )CV s

( )CV s

+

-

Vstep

LR

LRC

1M

2M

3M

Port 1

Port 2

Port 3

Port 4

0Z 0Z

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36

Flow chart

( )im

mn in

by ta

=

1( ) exp( )

mni i

mn mn mn

L

iy t r p t

== −∑

TDR or FDTD

( ) ( ) ( )( ) ( )

( ) ( ) ( )( ) ( )

( ) ( ) ( )

11 22 12 21 211

0 11 22 12 21

11 22 12 21 212

0 11 22 12 21

213

0 11 22 12 21

(1 )(1 ) 21(1 )(1 )

(1 )(1 ) 21(1 )(1 )

1 2 (1 )(1 )

M sZ

M sZ

M sZ



ξξ ξ ξ ξ

− + + −+ + −

+ − + −+ + −

=+ + −

=

=

( )0 1 1

0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k

i i i i i ik k kk k k k k

r D r D r D



≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

LR

LR1M

2M

3M

Port 1

Port 2

0Z 0Z

1 3 3

3 2 3

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

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37

Example: asymmetric vias

LR LR4.3rε =

Transmission line 50 OhmPort 2

S = 3 mil

GND

Port 1

Port 3 Port 4

Coupling Vias

LR

LR1M

2M

3M

Port 1

Port 2

0Z 0Z

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38

Eigen-values profile of asymmetric vias

0.1 1 10GHz

0.01

0.02

0.03

0.04

0.05

Eige

nval

ue

asymmetric vias£f1£f2

1 3 3

3 2 3

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

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39 2005/6/18

Stability

( )0 1

0 1

1

1

0 1

1 10 1 1

*1

1 1 1

( )

( ) ( )

(

)

i i

i ik k

i

ik

N i N ik k

i i i ik kk k k

r D r D

N ik

ii ik k k

r D

r rM s ss s j

r Ks j

sα α β

α β

= =≥ ≥

=≥

+ + +

+ −

= +

+ +

∑ ∑

∑

1M

2M

3M

+−

+−

+−

+−

+−

+−

+−

+−

+−

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40

Time-domain response – V11

0 10 20 30 40 50 60 70 80t (ps)

0

0.05

0.1

0.15

0.2

0.25

V 11

(vol

t)

3D-FDTDextracted model mode 54extracted model mode 44

( )0 1 1

0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k


r D r D r D



≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

LR LR4.3rε =


S = 3 mil

GND

Port 1

Port 3 Port 4

Coupling Vias

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41

Time-domain response – V12 & V22

0 10 20 30 40 50 60 70 80t (ps)

0

0.05

0.1

0.15

0.2

0.25

V 22

(vol

t)

3D-FDTDextracted model mode 54extracted model mode 44

-0.015

-0.005

0.005

0.015

0.025

0.035

V12 & V

21 (volt)

( )0 1 1

0 1 1

*0 1 1

1 1 10 1 1 1 1

( )( ) ( )

( )i i i

i i ik k k

N i N i N ik k k


r D r D r D



≥ ≥ ≥

+ + + + −= + + +∑ ∑ ∑

LR LR4.3rε =


S = 3 mil

GND

Port 1

Port 3 Port 4

Coupling Vias

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42

0 5 10 15 20 25 30GHz

-70

-60

-50

-40

-30

-20

-10

0

S11

(dB

)

3D-FDTD S11extracted model mode 54extracted model mode 44

0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S11

(deg

)


Frequency-domain response - S11 & S21

0 5 10 15 20 25 30GHz

-80

-70

-60

-50

-40

-30

-20

-10

0

S21

(dB

)


0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S21

(deg

)


LR LR4.3rε =


S = 3 mil

GND

Port 1

Port 3 Port 4

Coupling Vias

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43


0 5 10 15 20 25 30GHz

-20

-15

-10

-5

0

5

S31

(dB

)


0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S31

(deg

)


0 5 10 15 20 25 30GHz

-70

-60

-50

-40

-30

-20

-10

0

S22

(dB

)


0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S22

(deg

)


LR LR4.3rε =


S = 3 mil

GND

Port 1

Port 3 Port 4

Coupling Vias

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44

Example: Differential via


S = 3 mil

GND

Port 1

LR LR4.3rε =

Port 3 Port 4

GND

Differential Vias

LR

LR1M

3M

Port 1

Port 2

0Z 0Z

1M

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45

Eigen-values profile of differential vias

1 3 3

3 2 3

( ) ( ) ( )eigen{Re } 0

( ) ( ) ( )M j M j M j

M j M j M jω ω ω

ω ω ω⎡ ⎤+ −

≥⎢ ⎥− +⎣ ⎦

0.1 1 10GHz

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Eige

nval

ue

Differential via£f1£f2

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46

Time-domain response – V11 & V21

0 10 20 30 40 50 60 70 80t (ps)

0

0.05

0.1

0.15

0.2

0.25

V 11

(vol

t)

3D-FDTDextracted model

-0.02

-0.01

0

0.01

0.02

0.03

0.04

V12 & V

21 (volt)

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47


0 5 10 15 20 25 30GHz

-70

-60

-50

-40

-30

-20

-10

0

10

S11

(dB

)

3D-FDTD S11extracted model S11

0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S11

(deg

)

3D-FDTD S11extracted model

0 5 10 15 20 25 30GHz

-80

-70

-60

-50

-40

-30

-20

-10

0

S21

(dB

)


0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S21

(deg

)3D-FDTD S21extracted model

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48 2005/6/18


0 5 10 15 20 25 30GHz

-20

-15

-10

-5

0

5

S31

(dB

)


0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S31

(deg

)


0 5 10 15 20 25 30GHz

-80

-70

-60

-50

-40

-30

-20

-10

0

S41

(dB

)


0 5 10 15 20 25 30GHz

-200

-150

-100

-50

0

50

100

150

200

S41

(deg

)







Summary

NTU Challenge of Modeling the Real PCB and Package

4-layer Motherboard for Desktop Computer (PCB)

NTU Challenges for Modeling the Real PCB and Package

Top side

Bottom side

4-layer Motherboard for Desktop Computer (PCB)


4-layer BGA Package, 37.5mm ×

37.5mm, 788 pin balls

Ground Layer (layer 2)

Power Layer (layer 3)


Real PCB and Packages

1. Several thousands traces routed on a PCB.2. Several thousand through hole vias3. Perforated power and ground planes4. Irregular power/ground planes partitions.

In SI simulation, we need to think

How accurate you need?How complicated your circuits are?How much (computing) resources you have?


Material Characteristics:

1. Substrate: Broadband information of dielectric constant and loss tangent.

2. Conductor: frequency dependent loss (skin effect)

( ) ( ) ( )' ''f f j fε ε ε= −

NTUChallenges for Modeling the Real PCB and Package in High-speed Circuits

Signal Propagation Characteristics:

1. Signal line referred to the perforated power or ground planes.

2. Broadband single (differential) via models


Power distribution networks characteristics

Challenges: (how accurate?)• Power/ground ring with shorting vias• Thousands of via holes on power/ground planes• Vertical interconnects modeling and linking between package and PCB• Mutual coupling between package and PCB


Power Network Pre-drive

Circuits

IVDD

Ipd

Ishot

Isig

( )VDD sig shot pd clampI I I I I≅ + + +

IBIS Model for Power Noise modeling

Isig are considered in IBIS model (pull up and pull down current)

The pre-drive current Ipd and shot-through current Ishot are not considered in IBIS model

NTUChallenges for Modeling the Real PCB and Package in High- speed Circuits

IBIS Model for SSN modeling

Pull up current

Pre-drive current

NTU Summary

As an example, a driver PCB for TFT display panel is modeled by two approaches. One is using commercial SI design tool, and the other is based on the HSPICE environment by constructing equivalent SPICE-compatible models.

TDR concept and layer peeing technique for extracting equivalent circuit models is introduced based on time domain response.

A synthesis approach for macro equivalent circuit model for coupled discontinuity is also discussed.

Challenges for SI design tool in modeling the real PCB and package in high-speed circuits are discussed. They includes material characteristics, signal propagation characteristics, power distribution networks, and IBIS model for SSN.

Documents

Signal Integrity Simulation and Equivalent Circuit Modeling