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REVIEW EXAM 2INEL 4207 Digital Electronics
TOPICS
• Emitter-coupled Logic
• BiCMOS
• TTL
Figure 15.25 The basic element of ECL is the differential pair. Here, VR is a reference voltage.
ECL
Figure E15.12
Figure 15.26 Basic circuit of the ECL 10K logic-gate family.
Figure 15.27 The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the “ringing” that would otherwise corrupt the logic signals. (See Section 15.4.6.)
Figure 15.28 Simplified version of the ECL gate for the purpose of finding transfer characteristics.
Figure 15.30 Circuit for determining VOH.
fig. 15.32 (international, 6th edition)
Figure 15.36 The wired-OR capability of ECL.
BICMOS
Figure 15.37 Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of QN and QP of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices.
(c) To reduce the turn-off times of Q1 and Q2, “bleeder resistors” R1 and R2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R1 to the output node.
TTL: TRANSISTOR-TRANSISTOR LOGIC
Q1 Q2vIN
VCC=+5V
RRC
vO
Simple pseudo-TTL Inverter
1.6K14K1 1301
1.0K1
Q1 Q3
Q2
Q4
vIN
VCC=+5V
D1vOUT
RE
RBRC RS
TTL Inverter
DATA CONVERTERS
DAC
<
+
2N-1RR 2R 4RVREF
R/2
vOUT = �R
2
�VREF
Rbn�1 +
VREF
2Rbn�2 + · · · +
VREF
2n�1Rb0
⇥
= �R⇤ VREF
2
n�1⇤
i=0
bi
2n�i�1R
= �VREF
n�1⇤
i=0
bi
2n�i
b0bn�1
DAC
<
+
2R2R 2R 2R
VREF
RF
2RRRRi
i
2i
SIMPLE ADC
<
+timer/counter
enableclear clk
N output bits
control
VREF
R
C
vA
clock
DOUBLE-SLOPE ADC
timer/counterenable
clearclk
N output bits
clock
controllogic
<
+
<
+vA
VREFR C
s1
s2
up/down
vpeak
T1 T1+T2
t
At t=0 capacitor C is discharged and s2 is connected to vA. At t=T1 s2 is switched to VR
vO
vO
VREF > 0vA < 0
Name: INEL4207 Digital Electronics - A2
Student #: Sec.: December 21, 2010
This exam has 3 problems. Each problem counts for 1/3 of the exam grade.
1. For the ECL inverter shown in the following sketch, the high voltage level is VH = −1.7V andthe average power dissipated when the input is high 50% of the time is P = 5mW . Determinethe source’s current IEE, the low voltage level VL, the reference voltage level VREF and thevalue of resistance R3.
-5.2V-3.3V
VREFvin
2k�
2k�
IEE
Q1 Q2
Q3
voutR3
2. El siguiente diagrama muestra una red de transmision:
+5V
+5V +5V +5V
a bc
CL
Los parametros son: VT0 = 0.75V , γ = 0.55√
V , 2φF = 0.6V , y Kn = 100µA/V 2.
a) (15 puntos) Determine el voltaje en los nodos a, b, y c si se desprecia el body effect.
b) (20 puntos) Repita la parte (a) tomando en cuenta el ”body effect.”Debe analizar el circuito ymostrar el procedimiento que conduce al resultado.
Name: Student number:
2. Find VL, VH and VREF for the following circuit. Neglect base currents and assumeVBE = 0.7V if a transistor is ON. (25 points)
-2V-5V
1kΩ
1kΩ
VREFvINvOUT
4kΩ
Q1
Q2
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