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Pre-Computed Asynchronous Scan Invited Talk. Vishwani D. Agrawal James J. Danaher Professor Electrical and Computer Engineering Auburn University, USA With help from Praveen Venkataramani, PhD Candidate Quito, Ecuador, April 13, 2012. Scan Testing. PI. PO. SFF. SCANOUT. - PowerPoint PPT Presentation
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Pre-Computed Asynchronous ScanInvited Talk
Vishwani D. AgrawalJames J. Danaher Professor
Electrical and Computer Engineering Auburn University, USA
With help from Praveen Venkataramani, PhD Candidate
Quito, Ecuador, April 13, 2012
LATW, April 13, 2012 Agrawal: Asynchronous Scan 2
Scan Testing
SFF
SFF
SFF
Combinational
logic
PI PO
SCANOUT
SCANINSE or TCK Not shown: CK or
MCK/SCK feed allSFFs.
Agrawal: Asynchronous Scan 3
Test Time
LATW, April 13, 2012
Total scan test time (Number of scan test clock cycles × clock period):
TT = NT = [(ncomb + 2) nsff + ncomb + 4] × T
Where, ncomb = number of combinational vectors
nsff = number scan flip-flops in the longest scan chain
T = scan clock period
Example: 10,000 scan flip-flops in longest chain, 1,000 comb. vectors, total scan test length, TT ≈ 107 T.
Reference:M. L. Bushnell and V. D. Agrawal, Essentials of
Electronic Testing for Digital, Memory and Mixed- Signal VLSI Circuits, Springer, 2000.
Agrawal: Asynchronous Scan 4
Scan Power During a Clock Cycle
LATW, April 13, 2012
Clock period, Ttime
Chip
cur
rent
, i(t
)
0
TCycle energy, E = VDD ∫ i(t) dt
0
Cycle power, P = E/T
Agrawal: Asynchronous Scan 5
Scan Power During Test WithSynchronous Clock
LATW, April 13, 2012
1 2 3 4 5 6 7 8
Clock cycles
Cycl
e En
ergy
, E Emax
Cycl
e po
wer
, P
Pmax
E E EE
E
E
E
E
P
PP P PP
P
P
Scan clock period, T = Emax/Pmax
T T T T T T T T
Agrawal: Asynchronous Scan 6
Test Time for Synchronous Clock
LATW, April 13, 2012
N EmaxTTsync = NT = ———— Pmax
Where,
N = Number of scan test clock cycles
Agrawal: Asynchronous Scan 7
Power vs. Time
• Reduce power:– Use low activity vectors slower rise in fault ⇒
coverage more vectors longer test time⇒ ⇒• Reduce test time:
– Use high efficiency vectors ⇒ produce high activity ⇒ increase test power
LATW, April 13, 2012
Agrawal: Asynchronous Scan 8
Can We Speed Up Scan Testing?
• Maximum clock speed is limited by Emax of vectors and Pmax of circuit; T ≥ Emax/Pmax.
• For most cycles E << Emax ⇒ reduce period.• Structural limits on clock period:
• Critical path delay (functional and scan)• Set up and hold times < critical path delay
• A variable clock period can be shorter than the global (synchronous) power constrained period, T = Emax/Pmax.
LATW, April 13, 2012
Agrawal: Asynchronous Scan 9
Asynchronous Scan
• Pre-compute energy {Ei} for all clock cycles {i}.• For given power constrain Pmax of the circuit, set
the period Ti of ith clock cycle as:
Ti = max {Ei/Pmax, critical path delay} = Ei/Pmax, for power constrained testing
Where critical path delay can be different for scan and normal mode cycles.
LATW, April 13, 2012
Agrawal: Asynchronous Scan 10
Scan Power During Test WithAsynchronous Clock
LATW, April 13, 2012
1 2 3 4 5 6 7 8
Clock cycle, i
Cycl
e En
ergy
, E Emax
Cycl
e po
wer
, P
Pmax
E E EE
E
E
E
E
PPP P P P P P
Scan clock period, Ti = Ei/Pmax
T1 T7T5T2 T8T3 T4 T6
Agrawal: Asynchronous Scan 11
Test Time for Asynchronous Clock
LATW, April 13, 2012
N NTTasyn = Σ Ti = Σ Ei/Pmax
i=1 i=1
N 1 N = ——— × — Σ Ei
Pmax N i=1
N Eav Etotal = ——— = ———
Pmax Pmax
Agrawal: Asynchronous Scan 12
Comparing Two Scans
LATW, April 13, 2012
Test
tim
e (a
rbitr
ary
units
)200
150
100
50
0
TTsync
TTasyn
Pmax
Emax/Eav = 4
Agrawal: Asynchronous Scan 13
Test Time Reduction
LATW, April 13, 2012
N EmaxTTsync = ————
Pmax
N Eav EtotalTTasyn = ——— = ———
Pmax Pmax
TTsync/TTasyn = Emax/Eav ≥ 1
Agrawal: Asynchronous Scan 14
Theorem
• For any given Pmax, minimum test time has a lower bound, obtained upon dividing the smallest synchronous scan test time by the Emax/Eav ratio. This lower bound is achieved by asynchronous scan when every cycle consumes Pmax.
LATW, April 13, 2012
Agrawal: Asynchronous Scan 15
Comparing Tests
LATW, April 13, 2012
time
Ener
gy
Emax/Eav = 21.0
0.5
0.0
time
Ener
gy
Emax/Eav = 51.0
0.5
0.0
Low power test
Agrawal: Asynchronous Scan 16
0 2 4 6 8 10 12 14 16 18 20 220.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
Time (µs)
Dyna
mic
Pow
er (m
W)
Asynchronous clock
Synchronous clock, T = 40ns
Pmax= 0.711 mW
Pav = 0.455 mW
TTsync, 40ns clock
TTasyn
Spice Simulation: s289 (14FF) Scan Test
LATW, April 13, 2012
Agrawal: Asynchronous Scan 17
0 5 10 15 20 25 30 35 40 450.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
Time (µs)
Dyna
mic
Pow
er (m
W)
Asynchronous clock
Synchronous clock, T = 80ns
LATW, April 13, 2012
Spice Simulation: s289 (14FF) Scan TestPmax= 0.356 mW
Pav = 0.228 mW
TTasyn
TTsync, 80ns clock
Agrawal: Asynchronous Scan 18
0 5 10 15 20 25 30 35 40 450.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
Time (µs)
Dyna
mic
Pow
er (m
W)
Asynchronous clock
Synchronous clock, T = 80ns
LATW, April 13, 2012
Pav = 0.228 mW
Spice Simulation: s289 (14FF) Scan Test
Agrawal: Asynchronous Scan 19
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80
20
40
60
80
100
120
140
Pmax, Peak Power (mW)
Test
Tim
e (µ
s)
Test Time Synchronous
Test Time Asynchronous= 1.54
Test Time (Synchronous)
Test Time (Asynchronous)
LATW, April 13, 2012
Spice Simulation: s298 Test Time Ratio
Agrawal: Asynchronous Scan 20
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 320.0
0.2
0.4
0.6
0.8
1.0
1.2
Time (µs)
Dyna
mic
Pow
er (m
W)
Asynchronous clock
Synchronous clock, T 40ns
LATW, April 13, 2012
Spice Simulation: s713 Scan Test
Pmax = 1.06mW
Pav = 0.53mW
Agrawal: Asynchronous Scan 21
Conclusion• Total test energy (Etotal) is invariant for a test.• Cycle power (Pmax) is a circuit characteristic.• For power constrained scan testing,
– Synchronous clock test time = Etotal/Pav– Asynchronous clock test time = Etotal/Pmax
• Asynch. clock test will benefit from low energy tests.• Recent work on adaptive clock BIST (VTS’11, VLSI Design’12, etc.).• Future explorations may investigate energy reduction techniques
like reduced voltage testing.• Test programming for asynchronous clock needs to be worked
out.
LATW, April 13, 2012
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