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1/18/06 VLSI Design & Test Seminar 1
Overview of Overview of VirtexVirtex 44& & VirtexVirtex 4 BIST Project4 BIST Project
1/18/06 VLSI Design & Test Seminar 2
FPGA Testing ChallengesFPGA Testing ChallengesProgrammabilityProgrammability
Must test all modes of operationMust test all modes of operationArchitectures designed for applicationsArchitectures designed for applications
Testability is after thoughtTestability is after thoughtLeft to product/test engineersLeft to product/test engineers
Constantly growing sizeConstantly growing sizeReconfiguration dominates test timeReconfiguration dominates test time
Constantly changing architecturesConstantly changing architecturesIncorporation of new and different coresIncorporation of new and different cores
1/18/06 VLSI Design & Test Seminar 3
Xilinx Xilinx VirtexVirtex 4 FPGAs4 FPGAsArray of 1,536 to 22,272 PLBsArray of 1,536 to 22,272 PLBs
4 4 LUTs/RAMsLUTs/RAMs (4(4--input)input)4 4 LUTsLUTs (4(4--input)input)8 FF/latches8 FF/latches
48 to 552 18K48 to 552 18K--bit dualbit dual--port port RAMsRAMs
Also operate as Also operate as FIFOsFIFOsAlso operate as 36KAlso operate as 36K--bit bit RAMsRAMswith ECC (Hamming)with ECC (Hamming)
32 to 512 DSP cores 4832 to 512 DSP cores 48--bits bits 0 to 2 PowerPC processor 0 to 2 PowerPC processor corescores
=Xtreme DSP=PLBs=Block RAMs/FIFOs=I/O Buffers=Guard Band Area
PPC
PPC
1/18/06 VLSI Design & Test Seminar 4
VirtexVirtex 4 BIST Project4 BIST Project
BIST for BIST for CLBsCLBs = = SachinSachin DhingraDhingraBIST for I/O Buffers = BIST for I/O Buffers = SudheerSudheer VemulaVemulaBIST for BIST for RAMsRAMs & & DSPsDSPs = Daniel Milton= Daniel MiltonGuard Band (w/BIST) = Lee LernerGuard Band (w/BIST) = Lee LernerBIST for Interconnect = Chuck StroudBIST for Interconnect = Chuck StroudProject scheduled for completion this Project scheduled for completion this yearyear
1/18/06 VLSI Design & Test Seminar 5
Logic BIST for Virtex 4 Logic BIST for Virtex 4 FPGAs Using Embedded FPGAs Using Embedded
MicroprocessorMicroprocessor
Sachin Sachin DhingraDhingra
VLSI Design & Test Seminar - January 2006
1/18/06 VLSI Design & Test Seminar 6
OutlineOutlineIntroductionIntroductionPartial Configuration ReadbackPartial Configuration ReadbackComparisonComparison
Virtex 2 ProVirtex 2 ProVirtex 4Virtex 4
Logic BIST Using Embedded ProcessorLogic BIST Using Embedded ProcessorPowerPC/MicroblazePowerPC/MicroblazeNew approachNew approach
Circular Comparison BIST ArchitectureCircular Comparison BIST Architecture
1/18/06 VLSI Design & Test Seminar 7
IntroductionIntroductionBuiltBuilt--In Self Test (BIST) for FPGAsIn Self Test (BIST) for FPGAs
Program some Programmable Logic Blocks (PLBs) as Test Pattern Program some Programmable Logic Blocks (PLBs) as Test Pattern Generators (TPGs) and Output Response Analyzers (ORAs) to test Generators (TPGs) and Output Response Analyzers (ORAs) to test the remaining resources of the FPGAthe remaining resources of the FPGADiagnosis and Fault Tolerant Operation Diagnosis and Fault Tolerant Operation No area overheadNo area overhead
Issues Issues Large number of Configurations => High memory requirementsLarge number of Configurations => High memory requirementsSlow Configuration Speeds => Long test timesSlow Configuration Speeds => Long test times
Proposed SolutionsProposed SolutionsPartial ReconfigurationPartial ReconfigurationPartial Configuration Memory ReadbackPartial Configuration Memory ReadbackBIST using Embedded ProcessorBIST using Embedded Processor
1/18/06 VLSI Design & Test Seminar 8
Partial Configuration Memory ReadbackPartial Configuration Memory ReadbackRecent FPGAs allow configuration Recent FPGAs allow configuration memory readback of only a section memory readback of only a section of FPGAof FPGAColumn based configuration Column based configuration memory using frames spanning memory using frames spanning entire columnsentire columnsOnly the frames containing BIST Only the frames containing BIST results are readresults are read
Frames for FFs in ORA columns onlyFrames for FFs in ORA columns onlyTime saved compared to Full Time saved compared to Full Configuration Memory ReadbackConfiguration Memory Readback
Saves Logic & Routing resourcesSaves Logic & Routing resourcesScan Chain is absentScan Chain is absent
Empty PLBEmpty PLB
Block Under Test (BUT)Block Under Test (BUT)
Test Pattern Generator (TPG)Test Pattern Generator (TPG)
Output Response Analyzer (ORA)Output Response Analyzer (ORA)
ORA FlipORA Flip--FlipFlip
1/18/06 VLSI Design & Test Seminar 9
Comparison of V2P and V4 Comparison of V2P and V4 for Logic BISTfor Logic BIST
Virtex 4Virtex 2 Pro
XY CLB coXY CLB co--ordinatesordinatesSimilar to V2P w/ minor changesSimilar to V2P w/ minor changes
RowRow--Column CLB coColumn CLB co--ordinates ordinates Minor changes from Virtex IMinor changes from Virtex I
XDLXDL
Top and Bottom HalvesTop and Bottom HalvesLeft and Right HalvesLeft and Right HalvesLocation of 2 Location of 2 PPCsPPCsBetterBetterPoorPoorSlice TestabilitySlice Testability
2 slices of 2 types2 slices of 2 typesSliceL (logic) & SliceM (memory)SliceL (logic) & SliceM (memory)
All four Identical slicesAll four Identical slicesPLBPLBVirtex 4Virtex 4Virtex 2 ProVirtex 2 Pro
1/18/06 VLSI Design & Test Seminar 10
BIST Using Embedded ProcessorBIST Using Embedded ProcessorEmbedded Processor runs BIST and diagnosis Embedded Processor runs BIST and diagnosis
PowerPCPowerPCMicroblazeMicroblaze
No dedicated resources for embedded processorNo dedicated resources for embedded processorFPGA resources are required for interface toFPGA resources are required for interface to
Program memory (block Program memory (block RAMsRAMs))Internal Configuration Access Port (ICAP)Internal Configuration Access Port (ICAP)UART (hyperUART (hyper--terminal interface to PC)terminal interface to PC)
ReadRead--ModifyModify--Write using ICAP moduleWrite using ICAP moduleFast partial reconfigurationFast partial reconfigurationVerification and debug procedure for developmentVerification and debug procedure for developmentFault injection emulationFault injection emulation
FPGA is divided in two sections for testing:FPGA is divided in two sections for testing:Embedded ProcessorEmbedded ProcessorBIST circuitryBIST circuitry
1/18/06 VLSI Design & Test Seminar 11
Embedded Processors in V2PEmbedded Processors in V2P
Microblaze - Soft Core( Can be placed anywhere on the device )
PowerPC - Hard Core( Fixed position in a device )
1/18/06 VLSI Design & Test Seminar 12
Comparing Embedded ProcessorsComparing Embedded Processors
450 MHz (max)450 MHz (max)200 MHz (max)200 MHz (max)SpeedSpeedEDKEDKEDKEDKCompiler*Compiler*
Selected Virtex 2 Pro Selected Virtex 2 Pro and Virtex 4 FX onlyand Virtex 4 FX only
all Virtex 2, Virtex 2 all Virtex 2, Virtex 2 Pro, Pro, VirtexVirtex 4 devices4 devices
AvailabilityAvailability
36364040BRAM countBRAM count16161616BRAM count**BRAM count**
820820900900Slice count**Slice count**1035103510001000Slice countSlice count
Fixed Fixed -- hard core has fixed hard core has fixed location in FPGAlocation in FPGA
Variable Variable –– can be can be located anywhere in FPGAlocated anywhere in FPGA
LocationLocationPowerPCPowerPCMicroblazeMicroblaze
* Processor type is EDK compiler option - same code works for both Microblaze and PowerPC without any modifications
** Compacted Design
1/18/06 VLSI Design & Test Seminar 13
BIST ArchitectureBIST Architecture
Large Devices
Small Devices
CUTCUT
CUTCUT
Embedded Embedded ProcessorProcessor
BIST in part of the FPGABIST in part of the FPGAEmbedded Processor occupies restEmbedded Processor occupies rest
Hard core orHard core orSoft core (easier to move)Soft core (easier to move)
Embedded processor also consists Embedded processor also consists of peripheral devices:of peripheral devices:
UARTUARTMemory interfaceMemory interfaceBUS arbiterBUS arbiterICAP Module ICAP Module
BIST and processor swap places BIST and processor swap places for next test sessionfor next test session
Embedded Embedded ProcessorProcessor
1/18/06 VLSI Design & Test Seminar 14
Logic BIST ArchitectureLogic BIST Architecture
Logic BISTLogic BISTCircuitryCircuitry
Embedded Embedded ProcessorProcessor
FourFour Test Sessions Test Sessions Right Half Right Half –– EastEastRight Half Right Half –– WestWestLeft Half Left Half –– EastEastLeft Half Left Half –– WestWest
TwoTwo Test Slice sets for V2PTest Slice sets for V2POnly 2 of 4 slices can be tested in Only 2 of 4 slices can be tested in one configurationone configuration
SingleSingle Test Slice set for V4Test Slice set for V4More testable slice architectureMore testable slice architecture
Diagnostic ResolutionDiagnostic ResolutionDepends on ORA design and Depends on ORA design and connections to BUTsconnections to BUTs
1/18/06 VLSI Design & Test Seminar 15
Circular Comparison Logic BISTCircular Comparison Logic BISTArchitectureArchitecture
TPG moved to processor portion of TPG moved to processor portion of FPGAFPGA
Can be performed by processorCan be performed by processorORA column instead of TPGsORA column instead of TPGs
Circular comparison of BUTsCircular comparison of BUTs
Higher diagnostic Higher diagnostic resolutionresolution
BUTs on the edges are now compared BUTs on the edges are now compared by two ORAsby two ORAs
Needs sufficient routing Needs sufficient routing resourcesresources
Empty PLB
Block Under Test (BUT)
Test Pattern Generator (TPG)
Output Response Analyzer (ORA)
1/18/06 VLSI Design & Test Seminar 16
Virtex 2 Pro (XC2VP30) Virtex 2 Pro (XC2VP30) Circular Comparison Logic BISTCircular Comparison Logic BIST
Circular Comparison BIST Circuitry
TPGs(inside the
processor half)
Microblaze
Block RAMs
1/18/06 VLSI Design & Test Seminar 17
Defining Area ConstraintsDefining Area Constraints
Area Constraints defined using PACE
BIST Circuitry
Microblaze
Block RAMsArea constraints
defined using XDL
1/18/06 VLSI Design & Test Seminar 18
Virtex 4 FX12 with Logic BISTVirtex 4 FX12 with Logic BIST
6 Rows for Guard 6 Rows for Guard Band TestingBand Testing
Complete FPGAComplete FPGA Half FPGAHalf FPGA
1/18/06 VLSI Design & Test Seminar 19
Logic BIST for V4 Logic BIST for V4 SliceLSliceLFault Coverage (FC)
0
50
100
150
200
250
300
350
400
450
1 2 3 4 5 6 7 8 9 10
Configuration #
# Fa
ults
Det
ecte
d
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
FC (%
)
Individual FCCumulative FC
1/18/06 VLSI Design & Test Seminar 20
Summary & ConclusionsSummary & ConclusionsProcessor of choice: MicroblazeProcessor of choice: Microblaze
ReconfigurationReconfigurationResults retrievalResults retrievalDiagnosticsDiagnostics
Better testability of PLBs in V4 architectureBetter testability of PLBs in V4 architectureHigher diagnostic resolutionHigher diagnostic resolutionFewer ConfigurationsFewer Configurations
Circular Comparison Logic BIST possible due to Circular Comparison Logic BIST possible due to abundance of routing resourcesabundance of routing resourcesLesser details about the architectureLesser details about the architecture
Increased development timeIncreased development time
1/18/06 VLSI Design & Test Seminar 21
BuiltBuilt--In SelfIn Self--Test for Test for Programmable I/O BuffersProgrammable I/O Buffers
in in FPGAsFPGAs and and SoCsSoCs
Sudheer VemulaSudheer Vemula
1/18/06 VLSI Design & Test Seminar 22
MotivationMotivationFPGAsFPGAs consist ofconsist of
Programmable Logic Blocks Programmable Logic Blocks ((PLBsPLBs))Routing ResourcesRouting ResourcesInterconnect pointsInterconnect pointsI/O BuffersI/O Buffers
BIST configurations have been BIST configurations have been developed to test logic and developed to test logic and routing resources in the core of routing resources in the core of an FPGA.an FPGA.
BIST configurations were not BIST configurations were not developed to test the I/O developed to test the I/O (Input/Output) buffers in an (Input/Output) buffers in an FPGA. FPGA.
1/18/06 VLSI Design & Test Seminar 23
Types of I/O BuffersTypes of I/O BuffersEvery I/O Buffer can be: Every I/O Buffer can be:
InputInputOutputOutputBiBi--directionaldirectional
ConnectionsConnectionsBonded I/OBonded I/OUnbondedUnbonded I/OI/O
Types (in some FPGAs)Types (in some FPGAs)Primary I/O BufferPrimary I/O BufferSecondary I/O BufferSecondary I/O BufferClock BufferClock Buffer
PLB PLB
I/O I/O I/O I/OI/O= primary I/O buffer = secondary I/O buffer
X X
X X
X X
X X
Y
Y
Y Y
Y
Y
Y Y
TC
OUT
IN
PAD
to/frominternal
programmable routing
resources
1/18/06 VLSI Design & Test Seminar 24
Architecture of Atmel I/O BufferArchitecture of Atmel I/O Buffer
Routing associated with the I/O Buffer
1/18/06 VLSI Design & Test Seminar 25
Resources in I/O BufferResources in I/O BufferI/O buffers have several programmable featuresI/O buffers have several programmable features
MultiplexersMultiplexersFlipFlip--flops or Latchesflops or LatchesPullPull--up, Pullup, Pull--down capabilitiesdown capabilitiesDelays, Slew rate, I/O StandardsDelays, Slew rate, I/O StandardsDrive capabilities, TriDrive capabilities, Tri--state enablestate enableTransmission GatesTransmission GatesGlobal Reset ConnectionGlobal Reset Connection
1/18/06 VLSI Design & Test Seminar 26
Basic Testing ApproachBasic Testing Approach
fromTPG
to ORA
1/18/06 VLSI Design & Test Seminar 27
General I/O Buffer BIST ArchitectureGeneral I/O Buffer BIST ArchitectureTPG may be a counter or an LFSRTPG may be a counter or an LFSRORA is comparisonORA is comparison--based to latch mismatches due to based to latch mismatches due to faultsfaultsOutput of each I/O buffer is compared by two Output of each I/O buffer is compared by two ORAsORAswith the outputs of two other bufferswith the outputs of two other buffersCircular comparison improves diagnostic resolutionCircular comparison improves diagnostic resolution
=TPG=ORA
1/18/06 VLSI Design & Test Seminar 28
Manufacturing vs. InManufacturing vs. In--System TestSystem TestIn Manufacturing test all the bonded and In Manufacturing test all the bonded and unbondedunbonded IOBsIOBs can be testedcan be tested
Independent of packageIndependent of packageRouting associated with the Routing associated with the IOBsIOBs can also be can also be testedtested
In system level testing only the output In system level testing only the output buffers are testedbuffers are tested
Testing the input buffers will back drive themTesting the input buffers will back drive them
1/18/06 VLSI Design & Test Seminar 29
Atmel ImplementationAtmel Implementation3 BIST configurations developed using MGL3 BIST configurations developed using MGL
Configurations testConfigurations testprimary I/Oprimary I/Osecondary I/Osecondary I/Oglobal reset in primary and secondary I/Oglobal reset in primary and secondary I/O
Subsequent BIST configurations via dynamic partial Subsequent BIST configurations via dynamic partial reconfiguration from AVRreconfiguration from AVR
12 for primary I/O12 for primary I/O9 for secondary I/O9 for secondary I/OApproximately 2x3Approximately 2x3NN for global resetfor global reset
NN = # = # PLBsPLBs in one dimension of in one dimension of NNxxNN arrayarrayN=24 for AT94K10N=24 for AT94K10N=48 for AT94K40N=48 for AT94K40
AVR dynamic partial reconfiguration reduces test timeAVR dynamic partial reconfiguration reduces test timeParticularly when testing global resetParticularly when testing global reset
1/18/06 VLSI Design & Test Seminar 30
Fault Simulation Results for AT94KFault Simulation Results for AT94K
100% fault coverage is obtained with additional configuration fo100% fault coverage is obtained with additional configuration for global resetr global reset
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
1 2 3 4 5 6 7 8 9 10 11 12 13BIST Configurations
Faul
t Cov
erag
e (F
C)
1/18/06 VLSI Design & Test Seminar 31
Atmel SummaryAtmel SummaryNumber of BIST configurations for I/O buffers is highNumber of BIST configurations for I/O buffers is high
Compared to 16 for logic BIST and 48 for routing BISTCompared to 16 for logic BIST and 48 for routing BISTCan achieve 100% gate level stuckCan achieve 100% gate level stuck--at fault coverageat fault coverageMajor defects in analog circuitry of IOB are detected in both thMajor defects in analog circuitry of IOB are detected in both the e approachesapproaches
Parametric faults like VParametric faults like VOLOL, V, VOHOH, delay defects, current sink and source , delay defects, current sink and source capabilities may not be detectedcapabilities may not be detected
AVR
I/Obuffers
northcomparison
loop
eastcomparisonloop
westcomparison
loop
southcomparison
loop
1/18/06 VLSI Design & Test Seminar 32
I/O Buffers in I/O Buffers in VirtexVirtex 44Every I/O Buffer consists Every I/O Buffer consists
ILOGIC (Input Logic)ILOGIC (Input Logic)OLOGIC (Output Logic)OLOGIC (Output Logic)PADPAD
IOBsIOBs are paired to be able are paired to be able to operate as a differential to operate as a differential pairpair
Each can be accessed Each can be accessed individually in Single Data individually in Single Data Rate (SDR) modeRate (SDR) mode
I/O Blocks in the FPGA Editor
1/18/06 VLSI Design & Test Seminar 33
ILOGIC BlockILOGIC BlockGets input from the padGets input from the padConsists of Consists of
64 tap delay element 64 tap delay element (variable or fixed)(variable or fixed)FlipFlip--Flops (registered outputs Flops (registered outputs and Double Data Rate (DDR) and Double Data Rate (DDR) registers)registers)3 different outputs3 different outputs
Unregistered direct Unregistered direct connectionconnectionDifferent modes of operation Different modes of operation of DDR registersof DDR registers
Only upper register can be Only upper register can be configured as either Flipconfigured as either Flip--Flop or latch Flop or latch
ILOGIC Block inILOGIC Block inthe FPGA Editorthe FPGA Editor
1/18/06 VLSI Design & Test Seminar 34
IDDR Modes and ISERDESIDDR Modes and ISERDESIDDR registers can be operated in 3 modesIDDR registers can be operated in 3 modes
Opposite Edge Mode (2 registers)Opposite Edge Mode (2 registers)Same Edge Mode (3 registers)Same Edge Mode (3 registers)Same Edge Pipelined mode (4 registers)Same Edge Pipelined mode (4 registers)
ILOGIC block can also be operated in input ILOGIC block can also be operated in input serialserial--toto--parallel modeparallel modeISERDES can be operated in either Single Data ISERDES can be operated in either Single Data Rate (SDR) or DDR modeRate (SDR) or DDR mode
SDR Mode SDR Mode –– Creates 2Creates 2--8 bit parallel word8 bit parallel wordDDR Mode DDR Mode –– Creates 4, 6, 8, or 10Creates 4, 6, 8, or 10--bit parallel wordbit parallel word
1/18/06 VLSI Design & Test Seminar 35
OLOGIC BlockOLOGIC BlockSources output to the Sources output to the padpad6 storage elements6 storage elements
3 for tri3 for tri--state controlstate control3 for output data3 for output dataBoth sets of registers Both sets of registers have same have same functionalityfunctionalityOnly upper register Only upper register can be configured as can be configured as either Flipeither Flip--Flop or Flop or latch latch
OLOGIC Block inOLOGIC Block inthe FPGA Editorthe FPGA Editor
1/18/06 VLSI Design & Test Seminar 36
ODDR Modes and OSERDESODDR Modes and OSERDESODDR registers operate in 3 modesODDR registers operate in 3 modes
Opposite Edge Mode (2 registers)Opposite Edge Mode (2 registers)Same Edge Mode (3 registers )Same Edge Mode (3 registers )
OLOGIC block can be operated in output OLOGIC block can be operated in output parallel to serial converter modeparallel to serial converter modeOSERDES can be operated in either OSERDES can be operated in either Single Data Rate (SDR) or DDR modeSingle Data Rate (SDR) or DDR mode
SDR Mode SDR Mode –– Converts 2Converts 2--8 bit parallel word to 8 bit parallel word to serialserialDDR Mode DDR Mode –– Converts 4, 6, 8 or 10Converts 4, 6, 8 or 10--bit bit parallel word to serialparallel word to serial
1/18/06 VLSI Design & Test Seminar 37
SummarySummaryA BIST approach to test the programmable A BIST approach to test the programmable IOBsIOBsof any FPGA or FPGA core in an of any FPGA or FPGA core in an SoCSoCImplementation results for the Atmel Implementation results for the Atmel IOBsIOBsArchitecture of the Architecture of the IOBsIOBs in Xilinx Virtexin Xilinx Virtex--4 4 FPGAsFPGAs
BIST configurations are being developed for VirtexBIST configurations are being developed for Virtex--44
PublicationsPublicationsVemulaVemula & Stroud, & Stroud, ““BIST of I/O Buffers in Atmel BIST of I/O Buffers in Atmel FPGAsFPGAs ””, IEEE North Atlantic Test Workshop, 2005, IEEE North Atlantic Test Workshop, 2005VemulaVemula & Stroud, & Stroud, ““BIST for Programmable I/O BIST for Programmable I/O Buffers in Buffers in FPGAsFPGAs and and SoCsSoCs ””, IEEE Southeastern , IEEE Southeastern SympSymp. on System Theory, 2006. on System Theory, 2006
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