Operated by Los Alamos National Security, LLC for DOE/NNSA DC Reviewed by Kei Davis SKA – Static...

Operated by Los Alamos National Security, LLC for DOE/NNSA

DC Reviewed by Kei Davis

SKA – Static Kernel Analysis using LLVM IR

Kartik Ramkrishnan and Ben BergenApplied Computer Science (CCS-7)

Los Alamos National Laboratory

Operated by Los Alamos National Security, LLC for the U.S. Department of Energy's NNSA

SKA – Static Kernel Analyzer SKA is a very useful tool to improve the

development process. Performs static architecture aware analysis of

kernels. Outputs code metrics during the development

process. Visualizes the code execution on the specified

pipeline.

What is SKA

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SKA-Enhanced Development Cycle

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define i32 @main(i32 %argc, i8** nocapture %argv) nounwind uwtable readnone { entry: %a1 = alloca [32 x float], align 4 %b2 = alloca [32 x float], align 4 %c3 = alloca [32 x float], align 4 br label %"3" "3": ; preds = %"3", %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %"3" ] %0 = getelementptr [32 x float]* %a1, i64 0, i64 %indvars.iv %1 = load float* %0, align 4 %2 = getelementptr [32 x float]* %b2, i64 0, i64 %indvars.iv %3 = load float* %2, align 4 %4 = getelementptr [32 x float]* %c3, i64 0, i64 %indvars.iv %5 = load float* %4, align 4 %6 = fmul float %3, %5 %7 = fadd float %1, %6 store float %7, float* %4, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 32 br i1 %exitcond, label %"5", label %"3" "5": ; preds = %"3" ret i32 0

Example kernel – saxpy.ll

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LLVM IR is SSA (single static assignment) which has infinite register count.

ISAs(instruction set architectures) have a limited number of registers.

We improve SKA’s fidelity by allocating registers to the IR based on the target ISA.

Register allocation support for SKA

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Simple register allocation algorithm.

Register Allocation algorithm

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Build Liveness Tables

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SKA takes an LLVM IR module as input and builds a liveness table.

Build Liveness Tables

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Partial liveness table for saxpy.ll

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Build Liveness Tables

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Top level loop

Single BB liveness calculation

Populate liveness table

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Build Interference Graph

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Traverse the liveness table to create the interference graph.

Build Interference Graph

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Partial igraph for saxpy.ll

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Build Interference Graph

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Top level loop Populate igraph

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Simplify Interference Graph

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Populate a stack which records whether a register (node) is simple or not.

Simplify Interference Graph

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Partial node stack for saxpy.ll

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Simplify Interference Graph

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Populate simple node stack

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Assign ISA Registers to IR

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Assign ISA Registers to IR

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Assign ISA registers to IR, if no true spill. We choose between int, float and vector.

Partial register allocation for saxpy.ll

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Assign ISA registers to IR

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Assign register if no true spill

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Rewrite IR

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The live range of %a1 is shown in red. It reduces after rewriting the IR.

Rewrite IR

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Rewrite IR

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Store instruction into stack

Load, use and store

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Register allocation done !

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Specified in an xml file. Specifies logical units, instructions they process,

latencies, issue width …

Virtual architecture specification

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Pipeline simulation

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Pipeline simulation of saxpy.ll

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Skaview

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Graphical visualization of saxpy.ll

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SKA outputs useful metrics about the code.

Primitive statistics include basic performance counters, such as instructions, cycles and stalls.

Derived statistics are obtained from primitive statistics.

Code metrics

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CPI prediction is better after register allocation.

Results for residual.ll

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No change in CPI prediction. Why ?

Results for ef_operator.ll

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Predicts CPI > 1.0 for KNC for single threaded workloads.

Results for KNC (Knights corner)

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SKA now supports register allocation. Register allocation improves SKA’s fidelity by 5-

10% across three architectures for a compute intensive benchmark.

Dynamic scheduling and cache models can further improve SKA fidelity.

Conclusion

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Questions ?

Thank You !

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