M9195A PXIe Digital Stimulus/Responserfmw.em.keysight.com/mod/pdf/pxi_m9195a_customer... · 2015....

M9195A PXIe Digital Stimulus/Response

SMS Product Marketing

January 2015

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M9195A PXIe Digital Stimulus/Response

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Table of Contents

– M9195A Product Introduction

• Features

• Software features

• Pricing and accessories

– Advanced Features and capabilities

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M9195A PXIe Digital Stimulus/Response Module

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DSR Module Key Features

Front Panel IO: • 16 bidirectional channels with each channel capable of:

• Static digital • Parametric Measurements (PPMU) with remote sense• High speed digital stimulus/response

• 4 high voltage IO for flash/polyfuse tests• 4 open drain ports for fixture relay control • 2 GPIO for future useAdvanced Features• Single and multi-site configurations• Pattern cyclizer for flexible per bit timing control for waveform generation

with edge placement resolution of 1ns• On-the-fly pattern editing without recompiling and downloading the test• Channel delay adjustment to compensate for cable a fixture propagation

delays

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M9195A PXIe Digital Stimulus/Response

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Advanced features to match DV and production environmentsModule Key Features

High speed digital stimulus/response mode• 16 bidirectional channels• Programmable logic levels: -1.5V to +6.5V• Current per channel: ±75mA• Up to 250MHz pattern rate with RZ support for clock generation• Independent signal waveform definitions for arbitrary per bit patterns• Independent channels: per channel & per clock cycle IO control, per vector

timing, per period timing, on-the-fly modification• 1ns edge placement resolution for per period vector control• Per channel programmable stimulus/response compensation delay: up to

250ns with 25ps resolution• Real-time response comparison• Up to 125M vectors per channel memory• Deep response data capture for non-deterministic data

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M9195A Digital Stimulus/Response ModuleStandard Programming ToolsApplication Programming Interfaces:

• STIL (Standard Test Interface Language IEEE 1450)

• Define vectors and related timing

• IVI-COM, IVI-C drivers, LabVIEW driver (later date)

• Easy-to-use, Open XML (.xlsx) programming interface

• Soft-Front Panel for diagnostic and debug

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Open XML (.xlsx) Templates

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• Simple, easy to use and learn templates using common Open XML compliant commercial products

• Support all the basic DSR functions

• Example templates as a starting point

• Data input error checking

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Static Digital IO

- Use API (such as Soft front panel) to control or validate fixture status

- Use API reads and writes for direct access to channels

- Use API to validate cabling without requiring the user to create a pattern

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M9195A DSR Soft Front

Panel

- Programmatically write and read static binary values to/from digital pins

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Per Pin Parametric Measurements- Make parametric measurements on each of

the 16 channels - Program each channel independently- Selectable: FVMI, FVMV, FIMV, FIMI, MV - 5 current ranges: 40mA, 1mA, 100uA,

10uA, 2uA- Maximum source current : ± 40mA - Minimum source current: ± 1nA- Selectable remote sense

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- Built in windowing: Average 64, Window 50Hz, Window 60Hz

- High throughput: 1ms for first channel. For multiple channels add 100us.

M9195A DSR Soft Front

Panel

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Emulate Complex Digital Waveforms Using Flexible Pattern Creation Features

• Emulate parallel or serial waveforms• Change timing on a per vector basis.• Flexible pattern creation with per bit

timing control• High level pattern sequencing

commands• Macro definitions for repetitive pattern

functions and the creation of user definable timing sets

• On-the-fly vector modification from an API (such as Soft front panel) to existing test patterns. Doesn’t require user to re-compile and download like other PXI DIO modules.

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M9195A DSR Soft Front

Panel

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Single site or Multi-site Application Modes

Channels 0-3

Channels 4-7

Channels 8-11

Channels 12-15

Open Drain 0-3

Choose from 2 configuration modes: - Single: 16 synchronous channels

- Multi-site: 4 independent site of 4 channel testers

• The configuration mode is automatically selected based upon the test pin assignments.

• Modes can be changed on a per test basisChannels 0-15

Multi-site4 banks

Single site1 bank

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Single-site Application Modes

Use Single site configuration for wide parallel vector applications

• One sequencer controls all 16 channels

Channels 0-15

Single Site1 bank

Single site cables:- 1 meter (Y1246A) or 2 meter (Y1247A) - 50 ohm, high performance ribbonized coax- Samtec Edge Rate connectors- Standard or thumbscrew latching housing

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Multi-site Application Mode

Channels 0-3

Channels 4-7

Channels 8-11

Channels 12-15

Open Drain 0-3

One module with 4 Independent sequencers• Run the same, or different tests simultaneously• 4 asynchronous clocks• Use multiple modules for even more sites

Multi-site4 banks

Multi-site cables:- 1 meter (Y1248A) or 2 meter (Y1249A)- 50 ohm, high performance ribbonized coax- Samtec Edge Rate connectors- Standard or thumbscrew latching housing

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Per Pin Definition Example

Dynamic Digital (Ch 0-4, 6)• Synchronous, deterministic patterns taken from memory and

controlled by the sequencer

Channels 0123456789101112131415

Single site

Static Digital (9-11)• Defined in the API. Not stored in memory

PMU (Ch 14-15)• Perform FVMI, FIMV tests

Pin definition can be redefined for each test

Unused (Ch 7-8)

Unused (Ch 12-13)

Unused (Ch 5)

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Single site or Multi-site Application Modes

Dynamic Digital (Ch 0-4, 6)

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M9195A Digital Stimulus/Response ModulePattern Creation and Sequencing

• 32 waveform tables for flexible pattern generation• 15 user definable waveform definition characters• Variable equation based edge placement for flexible shmoo applications• Flexible pattern sequencing: loop, goto, watchloop for SW triggered advance, matchloop for pattern

compare, macro’s

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Example serial IO protocol templates (RFFE)

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Flexible Waveform Bit CyclizationTiming basic {WaveformTable one {Period 'clock';Waveforms {Sclk { 01 { '0ns' D/U; }}Sclk { T { '0ns' U; 'clock/2' D; }}

Sdata { 01 { '0ns' D/U; }}Sdata { T { '0ns' U; 'clock/2' D; }}

Sdata { LH { '0ns' Z; 'clock/2' L/H; }} Sdata { Z { '0ns' Z; }}

VIO { 01 { '0ns' D/U; }}

Synch { 01 { '0ns' D/U; }}

} // end waveforms} // end waveform table one

• 15 User definable waveform characters for each signal in the pattern: A-Z, 0-9

• M9195A Stimulus/Response Actions:U: Force the channel to a highD: Force the channel to a lowZ: Stop forcingP: Force the channel to the previous stateL: Compare the channel to a lowH: Compare the channel to a highT: Compare the channel to a Tri-stateX: Do not compare

• 32 WaveformTables define the period and times at which stimulus and response events occur within a period.

• Pattern period: Supports up to 250MHz clock and data.

• User defined variable for flexible timing equations

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On-the-fly Vector ModificationUse these 4 API commands to:1) SetSignal modify the pattern for a specific signal over a series of clock periods 2) SetVector completely replace the vector at a given location with the new pattern3) SetDCLevel modify the signal amplitude after the pattern has been downloaded to the DSR4) SetWaveformTable change the timing of a single bit period. Successive vectors will return to the

WaveformTable.

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- STIL test with cross reference labels

- Example API commands

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Cable Compensation • Stimulus Delay is used synchronize the signals arrival at the DUT per channel

• Response Delay Compensation makes the stimulus path to the DUT the same duration as the “Expected” path internal to the DSR per channel

• Adjust Response Delay Compensation to align the short internal path with the external path to the DUT and back

• Automatic Response Delay Compensation measurement

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PatternGeneration

StimulusDelay

DUTResponse

DelayCompensation

Response Comparison

Result

Expected

Stimulus

M9195A DSR Soft Front

Panel

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M9195A Accessories Structure and Price

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Product/Option

PreliminaryList Price

M9195A PXIe Digital Stimulus/Response $15K

125 Mb/ch pattern memory Mandatory* M10

Multi-site Mandatory* S04

250 MHz Mandatory* SR2*Mandatory options are included at intro. In the future options will be selectable

Accessories

Single-site Digital Stimulus/Response Cable: 1m Y1246A $ 700

Single-site Digital Stimulus/Response Cable: 2m Y1247A $ 750

Multi-site Digital Stimulus/Response Cable: 1m Y1248A $ 1,000

Multi-site Digital Stimulus/Response Cable: 2m Y1249A $ 1,200

Digital Stimulus/Response Calibration Fixture Y1252A $ 1,200

Digital Stimulus/Response Evaluation and Prototyping Board Y1253A $ 350

Digital Stimulus/Response SMA Breakout Cable: 1m Y1254A $ 1,500

Digital Stimulus/Response SMA Breakout Cable: 2m Y1255A $ 2,000

single-site DSR cable

multi-site DSR cable

SMA breakout cable

Evaluation and Prototyping Board

Calibration Kit

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Summary of the M9195A– High performance digital stimulus response module with per channel

control

– Very flexible timing capabilities with

• Up to 250MHz clock and data rate

• 1ns edge placement resolution

• Per bit timing control

• On-the-fly vector modification

• Robust pattern sequencing features

– Support for multiple programming modules

• STIL, API – IVI COM, IVI-C, OpenXML (Excel), Bulk data

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M9195A Digital Stimulus/Response Value Proposition

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Flexible RFFE emulation and device characterization with faster time to measurement results

for design validation and high volume test

• Precise vector timing with 1ns per bit edge placement resolution and up to 250 ns stimulus/response delay compensation with 25 psprogramming resolution

• Modify pattern variables on-the-fly for fast design verification test and production test throughput

• High speed leakage current measurements • Flexible test configurations with independent channel modes, up to 4

independent multi-sites, high voltage channels and open drain pins addressing your DUT specific test configurations.