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Ixia Hardware Guide
Release 3.65
Part No. 909-0005 Rev. EOctober 2002
ii Ixia Hardware Guide
Copyright © 1998-2002 Ixia. All rights reserved.
Ixia and its licensors retain all ownership rights to the IXIA 100, 400 and 1600 hardware and software and its doc-umentation. Use of Ixia hardware and software is governed by the license agreement accompanying your original purchase. This manual, as well as the hardware and software described in it, is furnished under license and may only be used or copied in accordance with the terms of such license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Ixia. Ixia assumes no responsibility or liability for any errors or inaccuracies that may appear in this book.Except as permitted by such license, no part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, recording, or otherwise, without the prior written permission of Ixia.
RESTRICTED RIGHTS LEGENDUse, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph 14(g)(iii) at FAR 52.227 and subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.
IXIA, the Ixia logo, ANVL, IxExplorer, IxServer, Ixia NetOps, IxCore, IxEdge, IxMapping, IxProfile, IxTraffic, IxActivate, and Optixia are either trademarks or registered trademarks of Ixia in the United States and/or other countries.
All other companies and product names and logos are trademarks or registered trademarks of their respective holders.
Part No. Part No. 909-0005 Rev. EOctober 1, 2002
Contacting Ixia
Corporate Headquarters
26601 W. Agoura Rd.Calabasas, CA 91302USA
Telephone 1 (877) FOR IXIA (877-367-4942) + 1 (818) 871 1800 (International)
Fax (818) 871-1805
Website www.ixiacom.com
General info@ixiacom.com
Investor Relations ir@ixiacom.com
Sales sales@ixiacom.com
Customer Support support@ixiacom.com
Training training@ixiacom.com
Table of Contents
Chapter 1 Introduction
Ixia Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IxClock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Ixia Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Ixia Load Module Properties . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Card Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
What’s New in Version 3.65 . . . . . . . . . . . . . . . . . . . . . . . . 1-21IXIA 250. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2110/100/1000 Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2110GE Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21RMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Chapter 2 Installation and Initial Configuration
Ixia Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1Unpacking the Ixia Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1Notes and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
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Initial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Windows 95 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7Windows 95 TCP/IP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .2-7Windows 95 General Configuration . . . . . . . . . . . . . . . . . . . . . . . .2-10
Windows 2000 Configuration . . . . . . . . . . . . . . . . . . . . . . . 2-11Windows 2000 TCP/IP Configuration . . . . . . . . . . . . . . . . . . . . . . .2-11Windows 2000 General Configuration . . . . . . . . . . . . . . . . . . . . . .2-16Windows 2000 Security Settings . . . . . . . . . . . . . . . . . . . . . . . . . .2-18
Local/Remote Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Powering Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
File-Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Chassis Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Chapter 3 IXIA 1600 Chassis
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Chapter 4 IXIA 1600T Chassis
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Installing Filler Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3Prerequisites for Baffle Unit Installation: . . . . . . . . . . . . . . . . . . . . . .4-3Baffle Unit Installation Procedure:. . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Chapter 5 IXIA 400 Chassis
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
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Chapter 6 IXIA 250 Chassis
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2Computer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4Test Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7Computer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8General Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Chapter 7 Optixia Chassis
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Chapter 8 Clocking - IXIA 100 and IxClock Modules
Ixia 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
IxClock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Background–Chassis Synchronization . . . . . . . . . . . . . . . . . 8-2Worldwide Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3Independent Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4Ixia 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4IxClock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
IxClock Components and Procedures. . . . . . . . . . . . . . . . . . 8-6IxClock Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7Rack Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8Making the IxClock Chassis Portable . . . . . . . . . . . . . . . . . . . . . . . 8-9Ixia Chassis Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
IXIA 100 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
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IxClock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Chapter 9 IXIA 10/100 Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Chapter 10 IXIA 10/100/1000 Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Chapter 11 IXIA 100 Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Chapter 12 IXIA Gigabit Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
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Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Chapter 13 IXIA Ethernet/USB Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Chapter 14 IXIA OC12c/OC3c Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Chapter 15 IXIA OC48c Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
OC48c VAR Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3Frequency Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3Frequency Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
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Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Optical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Chapter 16 IXIA Unframed BERT Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Clock-in / Clock-out Connectors . . . . . . . . . . . . . . . . . . . . 16-4
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
Optical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Chapter 17 IXIA OC192c Load Modules
Part Numbering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Trigger Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Optical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
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Chapter 18 IXIA 10Gigabit Ethernet Load Modules
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
XAUI Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6Reference Clock In/Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
.XENPAK Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9Clock In/Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9Power Sequencing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Trigger Out Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
Appendix A Time and Frequency Module
Time and Frequency Module. . . . . . . . . . . . . . . . . . . . . . . . .A-1Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2Environmental Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3Timing/Frequency Performance Specifications . . . . . . . . . . . . . . . . A-3Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4Satellite Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
Appendix B OC192c Emulator Board (LMF) Interface Specification
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
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Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1Electrical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14
Appendix C LM-RMII Interface Specification
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
MDC/MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6
Appendix D XAUI Connector Specifications
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
Standard Connector Specifications . . . . . . . . . . . . . . . . . . . D-1
Front Panel Loopback Connector . . . . . . . . . . . . . . . . . . . . D-3
Standard Cable Specification . . . . . . . . . . . . . . . . . . . . . . . . D-3
SMA Break-Out Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4
XAUI Fujitsu to XENPAK Adapter . . . . . . . . . . . . . . . . . . . . D-6
XAUI Tyco Interoperability Backplane HM-Zd Adapter . . . . D-7
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Appendix E Available Statistics
Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-2IxExplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
Statistics Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2Extra Statistics Checkboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3Key To Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
TCL Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5Statistics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5Access to Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
C++ Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6Statistics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6Access to Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6
Description of Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-7Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-24
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List of Figures
Figure 2-1. Rear View of IXIA 1600 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3Figure 2-2. Rear View of IXIA 400 Chassis with Serial Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3Figure 2-3. Rear View of IXIA 400 Chassis with PS-2 Keyboard and Mouse . . . . . . . . . . . . . . . .2-4Figure 2-4. Front View of Optixia Chassis with PS-2 Keyboard, Mouse and Monitor . . . . . . . . . .2-4Figure 2-5. IXIA 100/400 Supplied Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5Figure 2-6. IXIA 100 Chassis with Serial Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5Figure 2-7. IXIA 100 Chassis with PS-2 Mouse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6Figure 2-8. IXIA 100 Chassis Antenna Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6Figure 2-9. Initial Screen Display from Locally Connected Monitor . . . . . . . . . . . . . . . . . . . . . . .2-7Figure 2-10. Mouse Clicks to Invoke Network Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . .2-7Figure 2-11. Network Properties Dialog - Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8Figure 2-12. Network Properties Dialog - Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8Figure 2-13. IP Address Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8Figure 2-14. Accessing the Time Zone Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10Figure 2-15. Date/Time Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10Figure 2-16. Date/Time Properties - Time Zone Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11Figure 2-17. Accessing Anti-Virus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11Figure 2-18. Mouse Clicks to Invoke Network Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . .2-12Figure 2-19. Local Area Connection Status Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12Figure 2-20. Local Area Connection Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12Figure 2-21. Default Internet Protocol (TCP/IP) Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13Figure 2-22. Internet Protocol (TCP/IP) Properties for a Static Address . . . . . . . . . . . . . . . . . . . .2-14Figure 2-23. Mouse Clicks to Invoke System Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . .2-15Figure 2-24. System Properties Dialog - Network Identification Tab . . . . . . . . . . . . . . . . . . . . . . .2-15Figure 2-25. Identification Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16Figure 2-26. Accessing the Time Zone Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16Figure 2-27. Date/Time Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17Figure 2-28. Date/Time Properties - Time Zone Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
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List of Figures
Figure 2-29. Accessing Anti-Virus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18Figure 2-30. Accessing Computer Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18Figure 2-31. Change Password for Administrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18Figure 2-32. Accessing Tweak UI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19Figure 2-33. Setting the Password Associated with the Default User . . . . . . . . . . . . . . . . . . . . . . 2-19Figure 2-34. Chassis Chaining Using Sync Out / Sync In Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21Figure 3-1. Ixia 1600 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1Figure 4-1. Ixia 1600T Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1Figure 4-2. Installing a 4-Slot Filler Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Figure 4-3. Installing a 1-Slot Filler Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5Figure 5-1. Ixia 400 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1Figure 6-1. IXIA 250 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1Figure 6-2. IXIA 250 Integrated Support (Collapsed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2Figure 6-3. IXIA 250 Integrated Support (Extended). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2Figure 6-4. IXIA 250 Integrated Support Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3Figure 6-5. IXIA 250 Keyboard Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3Figure 6-6. IXIA 250 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4Figure 6-7. IXIA 250 Standby Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4Figure 6-8. IXIA 250 Keyboard and Touchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5Figure 6-9. IXIA 250 Keyboard/Mouse ‘Y’ Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5Figure 6-10. IXIA 250 Floppy and Hard Drive Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6Figure 6-11. IXIA 250 with Additional Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7Figure 7-1. Optixia Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1Figure 8-1. Ixia 100 Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1Figure 8-2. IxClock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1Figure 8-3. Worldwide Deployment of Synchronized Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3Figure 8-4. Independent Chassis Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4Figure 8-5. Chassis Timing Using an Ixia 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5Figure 8-6. IxClock Chassis Timing Choices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6Figure 8-7. IxClock Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7Figure 8-8. IxClock Front and Rear Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7Figure 8-9. Connecting the IxClock Chassis to the Rack Mount Adapter . . . . . . . . . . . . . . . . . . . 8-8Figure 8-10. Attaching the IxClock Chassis to the Rack Mount Adapter. . . . . . . . . . . . . . . . . . . . . 8-8Figure 8-11. Placing the IxClock in the Rack Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9Figure 8-12. Rack Mount Rear Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9Figure 8-13. Battery, Battery Charger and GPS Antenna Location in IxClock Carrying Case . . . . 8-9Figure 8-14. Battery Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10Figure 8-15. Threading Cables From Front to Rear of Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10Figure 8-16. Front Connections for IxClock in Portable Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11Figure 9-1. LM100TXS8 Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1Figure 9-2. LM100TXS8 Face Plate (with 4 ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1Figure 10-1. LM1000TXS Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
xiv Ixia Hardware Guide
List of Figures
Figure 11-1. LM100FX Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1Figure 11-2. LM100FX Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1Figure 12-1. LM1000SX Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1Figure 12-2. LM1000SX Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1Figure 13-1. LMUSB2 Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1Figure 13-2. LMUSB2 Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1Figure 14-1. LMOC12c Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1Figure 14-2. LMOC12c Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1Figure 15-1. LMOC48cBert Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1Figure 15-2. LMOC48cBert Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1Figure 16-1. LMUB1MOC48P8 Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1Figure 16-2. LMUB1MOC48P8 Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1Figure 16-3. Close-up of LMUB1MOC48P8 Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2Figure 17-1. LMOC192c Load Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1Figure 17-2. LMOC192c Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2Figure 18-1. 10GE Load Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2Figure 18-2. MDC/MDIO D-sub Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7Figure B-1. HS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Figure B-2. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14Figure C-1. IXIA RMII Test Board Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3Figure C-2. IXIA RMII Mictor Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4Figure C-3. Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6Figure D-1. Fujitsu MicroGiGa Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2Figure D-2. XAUI Connector Contact Details and Cable Cross Section . . . . . . . . . . . . . . . . . . . . D-3Figure D-3. XAUI Front Panel Loopback Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3Figure D-4. Ixia XAUI Cable (CAB10GE500S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4Figure D-5. Direct XAUI Interface using Ixia supplied cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4Figure D-6. XAUI SMA Break-Out Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5Figure D-7. XAUI SMA Break-Out Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5Figure D-8. Fujitsu to XENPAK Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6Figure D-9. Tyco Interoperability Backplane HM-Zd Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7Figure E-1. Statistics Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3Figure E-2. Receive Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4
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List of Figures
xvi Ixia Hardware Guide
List of Tables
Table 1-1. Ixia Chassis Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Table 1-2. Load Module to IxExplorer Name Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4Table 1-3. IxExplorer Name to Load Module Name Map (Alphabetical) . . . . . . . . . . . . . . . . . . .1-6Table 1-4. Ixia Load Module Feature Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7Table 1-8. Card Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-19Table 1-9. Measured Number of Packets for an LM100TX Card . . . . . . . . . . . . . . . . . . . . . . . .1-20Table 2-1. TCP/IP Networking Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9Table 2-2. Internet Protocol (TCP/IP) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14Table 3-1. Ixia 1600 Chassis Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1Table 4-1. Ixia 1600T Chassis Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2Table 4-2. Slot Preferences for Installing Multiple OC192 Load Modules . . . . . . . . . . . . . . . . . .4-3Table 5-1. Ixia 400 Chassis Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2Table 6-1. IXIA 250 Computer Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6Table 6-2. IXIA 250 Computer Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7Table 6-3. IXIA 250 Computer Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8Table 6-4. IXIA 250 Chassis Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8Table 7-1. Optixia Chassis Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2Table 8-1. Summary of Timing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3Table 8-2. Independent Chassis Timing Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4Table 8-3. Ixia 100 Chassis Timing Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5Table 8-4. IxClock Chassis Timing Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6Table 8-5. IxClock Front and Rear Connector Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7Table 8-6. IxClock Front Control Connector Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11Table 8-7. IXIA 100 Front Panel LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12Table 8-8. Ixia 100 Chassis Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12Table 8-9. IxClock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13Table 9-1. 10/100 Load Module Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2Table 9-2. LM100TXS8 Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
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Table 9-3. 10/100 Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3Table 9-4. 10/100 Trigger Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3Table 10-1. 10/100/1000 Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2Table 10-2. 10/100/1000 Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3Table 10-3. 10/100/1000 Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4Table 10-4. 10/100/1000 Trigger Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4Table 11-1. 100 Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2Table 11-2. 100 Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2Table 11-3. 100 Trigger Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3Table 12-1. Gigabit Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2Table 12-2. Gigabit Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3Table 12-3. Gigabit Trigger Out Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4Table 13-1. USB Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2Table 13-2. USB Port LEDs – USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2Table 13-3. USB Port LEDs – Ethernet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3Table 13-4. USB Trigger Out Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3Table 14-1. OC12c/OC3c Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2Table 14-2. OC12 Minimum Number of Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2Table 14-3. OC3 Minimum Number of Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3Table 14-4. LMOC12c Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3Table 14-5. OC12c/OC3c Trigger Out Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3Table 14-6. LMOC12c Optical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4Table 15-1. Currently Available OC48 modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2Table 15-2. OC48 Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2Table 15-3. LMOC48c Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4Table 15-4. 10/100/1000 Trigger Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4Table 15-5. LMOC48c Optical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4Table 16-1. Currently Available OC48 modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2Table 16-2. Unframed BERT Load Module Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3Table 16-3. Unframed Bert Clock-in/Clock-out Signal Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4Table 16-4. Unframed Bert Card-Level LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4Table 16-5. Unframed Bert Per-Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5Table 16-6. Unframed Bert Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5Table 17-1. Currently Available OC192 modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2Table 17-2. OC192 Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3Table 17-3. LMOC192cPOS Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4Table 17-4. OC192 Trigger Out Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5Table 17-5. LMOC192c Optical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6Table 18-1. Currently Available 10GE modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2Table 18-2. 10GE XAUI Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3Table 18-3. 10GB Load Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4Table 18-4. WAN Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
xviii Ixia Hardware Guide
List of Tables
Table 18-5. LAN/XAUI/XENPAK Port LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-5Table 18-6. 10GE Optical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-6Table 18-7. MDC/MDIO Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-7Table 18-8. XAUI Reference Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-8Table 18-9. Clock In/Out Electrical Interface Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-8Table 18-10. 10GE Trigger Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-9Table A-11. Time and Frequency Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2Table A-12. Environmental Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3Table A-13. Timing/Frequency Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3Table B-1. Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1Table B-2. LVTTL Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2Table B-3. Transmitter Electrical I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2Table B-4. Receiver Electrical I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Table B-5. Electrical Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Table B-6. Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4Table B-7. A Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4Table B-8. B Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6Table B-9. C Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7Table B-10. E Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8Table B-11. F Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9Table B-12. G Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10Table B-13. H Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11Table B-14. J Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12Table B-15. K Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13Table C-1. Voltage Selection Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5Table C-2. Selection of Reference Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5Table D-1. XAUI Connector Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2Table D-2. XAUI Electrical Interface Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6Table E-1. Key for Statistics Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4Table E-2. Tcl stat mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5Table E-3. Tcl port receive Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5Table E-4. C++ stat Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6Table E-5. Tcl port receive Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6Table E-6. Statistics Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8Table E-7. Notes for Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-24Table E-8. Statistics for 10/100 Cards and Ethernet/USB Cards in Ethernet Mode . . . . . . . . . E-28Table E-9. Statistics for 10/100 TXS Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-30Table E-10. Statistics for 10/100/1000 TXS and 1000 SFPS4 Cards . . . . . . . . . . . . . . . . . . . . . E-33Table E-11. Statistics for Ethernet/USB cards in USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . E-36Table E-12. Statistics for Gigabit Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-40Table E-13. Statistics for OC12c/OC3c Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-43Table E-14. Statistics for OC48c Modules with Bert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-48
Ixia Hardware Guide xix
List of Tables
Table E-15. Statistics for OC192c Modules with Bert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-52Table E-16. Statistics for 10GE Modules with BERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-57Table E-17. Statistics for Protocol Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-63
xx Ixia Hardware Guide
1Chapter 1: Introduction
Ixia produces a number of Load Modules which provide data transmission and reception capabilities for a variety of Ethernet and Packet Over Sonet (POS) speeds and technologies. These Load Modules reside in an Ixia chassis, which provide different numbers of Load Module slots and power. In addition, an IxClock chassis provides a facility for accurate timing. This chapter introduces the Ixia hardware components. The Ixia chassis and load modules are compared and contrasted.
Ixia ChassisFive Ixia chassis capable of holding Load Modules are available:
• IXIA 1600 Chassis–capable of holding up to 16 Ixia Load Modules.
• IXIA 1600T Chassis–capable of holding up to 16 Ixia Load Modules and equipped with extra power and fans required for some high-powered load modules.
• IXIA 400 Chassis–capable of holding up to 4 Ixia Load Modules. Revision C or higher is required to handle the extra power and cooling required for some of the high-powered load modules.
• IXIA 250 Chassis–a portable Field Service Unit (FSU) which includes a sin-gle 10/100/1000 port and capable of holding two additional Ixia Load Mod-ule. May optionally be equipped with a built-in GPS or CDMA receiver. Appendix A contains the specification of the GPS hardware.
• Clocking - IXIA 100 and IxClock Modules–the IXIA 100 is capable of hold-ing one Ixia Load Module and includes a built-in GPS or CDMA receiver. Appendix A contains the specification of the GPS hardware.
• Optixia Chassis–capable of holding a combination of high-density Ixia Load Modules with 24 or 48 ports and smaller Load Modules compatible with the other chassis. It supports up to a total of 480 10/100Mbps ports or 240 Giga-bit ports. It is equipped redundant power supplies and supports hot-swapping of Load Modules. The Optixia chassis includes sufficient power and airflow to support high-powered load modules.
Ixia Hardware Guide 1-1
IntroductionIxia Chassis1
All of the Ixia chassis have the ability to hold one or more standard Load Mod-ules. Ixia Load Modules provide media dependent and independent ports to Devices Under Test (DUTs). Any of the chassis may be daisy-chained and syn-chronized within 10ns. The IXIA 100 chassis includes timing provisions based on GPS which allows accurate worldwide synchronization without local inter-chassis connections.
Each chassis contains a self-contained PC-style computer running Windows 2000™ and includes a 10/100MB network interface, local disk, floppy drive and CD-ROM drive in some cases1. A chain of chassis may be controlled via a moni-tor, keyboard and mouse directly connected to any of the chassis or remotely through the network interface card. Multiple users may safely share ports in a chassis chain. Several of the high-end load modules consume more power and generate additional heat. Only a limited number of such modules may be used in selected chassis.
The basic characteristics of these chassis are compared in Table 1-1 on page 1-2.
1. Some older chassis utilize Windows 95 as their operating system.
Table 1-1. Ixia Chassis Comparison
Chassis # of slots
Special Feature Mounting High-Power Cards Accommodated
1600 16 Desktop/Rack
0
1600T 16 Extra power and cooling Desktop/Rack
8
400 4 Cannot be used with cards requiring extra power and cooling
Desktop/Portable
0
400C+ 4 Revision C can handle one one-port high power card.
Desktop/Portable
1 (1-port)
400L+ 4 Revision L can handle one two-port high power card.
Desktop/Portable
1 (2-port)
250 2 Built-in 10/100/1000 TXS4 or 1000 SFPS4 port.
Desktop/Portable
1
100 1 Built-in GPS for worldwide synchronization
Rack 0
Optixia 10 10 slots for large high-density cards. Four smaller cards may be used in a carrier in one of the slots. Redundant power supplies. Hot-swappable cards.
Free standing/Rack
6-10
1-2 Ixia Hardware Guide
IntroductionIxClock Module
The process of initial chassis configuration is detailed in Chapter 1, Introduction. Each chassis is further described in its own chapter.
IxClock ModuleThe IxClock module provides a means of maintaining accurate timing through a variety of input signals, including GPS, CDMA, T1/E1 and 1PPS signals. The IxClock module includes a battery so that a GPS signal can be obtained ‘outside’ and the unit then brought inside. It also includes a Rubidium oscillator that retains the time lock for a period of time.
Refer to Clocking - IXIA 100 and IxClock Modules for a complete discussion of this module.
Ixia Load ModulesIxia offers a number of Load Modules that provide 1 to 48 ports of technology and media dependent interfaces to DUTs. The Load Modules are divided into logical families:
• IXIA 10/100 Load Modules–utilize a copper interface and provide either 10Mbps or 100Mbps Ethernet speeds with auto-negotiation.
• IXIA 10/100 Load Modules with CPU–the same capabilities as above, but each port contains its own general purpose processor.
• IXIA 10/100/1000 Load Modules–provide either 10Mbps, 100Mbps or Giga-bit/sec Ethernet speeds with auto-negotiation (except for Gigabit).
• IXIA 100 Load Modules–utilize a fiber interface and provide 100Mbps Ether-net with auto-negotiation.
• IXIA Gigabit Load Modules–provide Gigabit/sec Ethernet speeds.
• IXIA Ethernet/USB Load Modules–provide selectable USB or Ethernet inter-faces, for use with Cable Modems.
• IXIA OC12c/OC3c Load Modules–provide selectable Optical Carrier inter-faces that operate in concatenated mode at OC3 or OC12 rates. Packet over Sonet (POS) is implemented on the interfaces.
• IXIA OC48c Load Modules–provide Optical Carrier interfaces that operate in concatenated mode at OC48 rates. Either Packet over Sonet (POS) or Bit Error Rate Testing (BERT) may be performed.
• IXIA Unframed BERT Load Modules–provide Optical Carrier interfaces that operate in unframed Bit Error Rate Testing (BERT) mode.
• IXIA OC192c Load Modules–provide Optical Carrier interfaces that operate in concatenated mode at OC192 rates. Either Packet over Sonet (POS) or Bit Error Rate Testing (BERT) may be performed.
• IXIA 10Gigabit Ethernet Load Modules–provides 10GB/sec Ethernet with a variety of interfaces.
Ixia Hardware Guide 1-3
IntroductionIxia Load Modules1
Load modules that end with -3 or -M are limited in their functionality. In general, -3 and -M modules do not have the following functions:
• Flows, except where Streams are not supported.
• Advanced Streams (included with OC48C-3, however)
• Packet Groups (included with OC48C-3, however)
• Latency (included with OC48C-3, however)
• Sequence Checking (included with OC48C-3, however)
• Data Integrity (included with OC48C-M, however)
• Multiple DLCIs on OC48c Cards
• Convert to streams in capture view
• Protocol Server for router testing
Each family of interfaces is discussed in full in its own chapter in this manual.
The load module names used within the IxExplorer software differ slightly from the load module names used in Ixia marketing literature. Table 1-2 on page 1-4 describes the mapping from load module names to the names used in IxExplorer. The reverse mapping, alphabetized, is shown in Table 1-3 on page 1-6.
Table 1-2. Load Module to IxExplorer Name Map
Family Load Module IxExplorer Card Name IxExplorer Port Name
10/100 Ethernet
LM100TX 10/100 10/100 Base TX
LM100TX2 10/100 TX2 10/100 Base TX
LM100TX3 10/100-3 10/100 Base TX-3
LM100TXS8 10/100 TXS8 10/100 Base TX
LM100MII 10/100 MII 10/100 MII
LM100RMII 10/100 Reduced MII 10/100 Reduced MII
10/100/1000 Ethernet
LM1000T-5 Copper 10/100/1000 Copper 10/100/1000
LM1000TXS4 10/100/1000 TXS4 10/100/1000 Base T
100MB Ethernet
LM100FX 100Base FX MultiMode 100Base FX MultiMode
LM100FXSM 100Base FX SingleMode 100Base FX SingleMode
Gigabit LM1000SX Gigabit 1000 Base SX Multimode
LM1000SX3 Gigabit-3 1000 Base SX Multimode - 3
1-4 Ixia Hardware Guide
IntroductionIxia Load Modules
LM1000LX Gigabit Single Mode 1000 Base LX SingleMode
LM1000GBIC GBIC GBIC
LM1000GBIC-P1 GBIC-P1 GBIC
LM1000SFPS4 1000 SFPS4 1000 Base X
USB LMUSB2 Ethernet/USB Ethernet or USB
OC12c/OC3c
LMOC12c/LMOC3c OC12c/OC3c POS OC12c/OC3c POS
LMOC12c 32MB OC12c 32MB OC12c/OC3c POS
OC48 LMOC48cPOS OC48c POS OC48c POS
LMOC48cPOS-M OC48c POS-M OC48c POS-M
LMOC48cBERT OC48c BERT OC48c BERT
LMOC48POS/BERT OC48c POS/BERT OC48c POS/BERT
LMOC48VAR OC48c POS VAR OC48c POS VAR
OC192 LMOC192cPOS OC192c POS OC192c POS
LMOC192cVSR-POS OC192c VSR POS OC192c VSR POS
LMOC192cBERT OC192c BERT OC192c BERT
LMOC192cVSR-BERT OC192c VSR BERT OC192c VSR BERT
LMOC192cPOS+BERT OC192c POS/BERT OC192c POS/BERT
LMOC192cVSR-POS+BERT
OC192c VSR POS/BERT OC192c VSR POS/BERT
LMOC192cPOS+WAN OC192c POS/10GE WAN OC192c POS/10GE WAN
LMOC192cPOS+BERT+WAN
OC192c POS/BERT/10GE WAN OC192c POS/BERT/10GE WAN
10GE LM10GEWAN 10GE WAN 10GE WAN
LM10GEWAN+BERT 10GE WAN/BERT 10GE WAN/BERT
LM10GELAN 10GE LAN 10GE LAN
LM10GELAN-M 10GE LAN-M 10GE LAN-M
LM10GEXAUI 10GE XAUI 10GE XAUI
LM10GEXAUI+BERT 10GE XAUI/BERT 10GE XAUI/BERT
LM10GEXENPAK 10GE XENPAK ZENPAK 10GE LAN
Table 1-2. Load Module to IxExplorer Name Map
Family Load Module IxExplorer Card Name IxExplorer Port Name
Ixia Hardware Guide 1-5
IntroductionIxia Load Modules1
Table 1-3. IxExplorer Name to Load Module Name Map (Alphabetical)
IxExplorer Card Name IxExplorer Port Name Load Module
10/100 10/100 Base TX LM100TX
10/100 MII 10/100 MII LM100MII
10/100 Reduced MII 10/100 Reduced MII LM100RMII
10/100 TX2 10/100 Base TX LM100TX2
10/100 TXS8 10/100 Base TX LM100TXS8
10/100-3 10/100 Base TX - 3 LM100TX3
10/100/1000 TXS4 10/1000/1000 Base T LM1000TXS4
100Base FX MultiMode 100Base FX MultiMode LM100FX
100Base FX SingleMode 100Base FX SingleMode LM100FXSM
100Base LX SingleMode 100Base LX SingleMode LM100LXSM
1000 SFPS4 1000 Base X LM1000SFPS4
10GE LAN 10GE LAN LM10GELAN
10GE LAN-M 10GE LAN-M LM10GELAN-M
10GE XAUI 10GE XAUI LM10GEXAUI
10GE WAN 10GE WAN LM10GEWan
10GE WAN/BERT 10GE WAN/BERT LM10GEWan-Bert
Copper 10/100/1000 Copper 10/100/1000 LM1000T-5
Ethernet/USB Ethernet or USB LMUSB2
GBIC GBIC LM1000GBIC
GBIC-P1 GBIC LM1000GBIC-P1
Gigabit 1000 Base SX Multimode LM1000SX
Gigabit Single Mode 1000 Base SX SingleMode LM1000LX
Gigabit-3 1000 Base SX Multimode - 3 LM1000SX3
OC12c/OC3c POS OC12c/OC3c POS LMOC12c
OC12c 32MB OC12c/OC3c POS LMOC12c 32MB
OC192c BERT OC192c BERT LMOC192cBERT
OC192c POS OC192c POS LMOC192cPOS
OC192c POS/BERT OC192c POS/BERT LMOC192cPOS+BERT
OC192c POS/BERT/WAN OC192c POS/WAN LMOC192cPOS+BERT+WAN
OC192c POS/WAN OC192c POS/WAN LMOC192cPOS+WAN
1-6 Ixia Hardware Guide
IntroductionIxia Load Module Properties
Ixia Load Module PropertiesThe Ixia load modules, or cards, support a wide range of features. The full set of supported features is described in Table 1-4 on page 1-7. The list of features sup-ported by each card type is described in Table 1-5 on page 1-11, Table 1-6 on page 1-14 and Table 1-7 on page 1-17.
OC192c VSR BERT OC192c VSR BERT LMOC192cVSR-BERT
OC192c VSR POS OC192c VSR POS LMOC192cVSR-POS
OC192c VSR POS/BERT OC192c VSR POS/BERT LMOC192cVSR-POS+BERT
OC192c XAUI OC192c XAUI LMOC192cXAUI
OC192c XAUI/BERT OC192c XAUI/BERT LMOC192cXAUI+BERT
OC192c XENPAK XENPAK OC192c LAN LMOC192cXENPAK
OC48c POS OC48c POS LMOC48cPOS
OC48c BERT OC48c BERT LMOC48cBERT
OC48c POS/BERT OC48c POS/BERT LMOC48POS/BERT
OC48c POS VAR OC48c POS VAR LMOC48VAR
Table 1-3. IxExplorer Name to Load Module Name Map (Alphabetical)
IxExplorer Card Name IxExplorer Port Name Load Module
Table 1-4. Ixia Load Module Feature Descriptions
Feature Category Feature Usage
Statistics Selection QoS Supports collection of QoS statistics.
Stream triggers Collect statistics of how often the stream filters were triggered.
Checksum errors Support generation and checking of special checksums.
Data integrity Supports data integrity generation and checking.
Tx Duration Supports the generation of a transmit duration statistic.
Receive Modes Packet groups Supports generation of packet group IDs in packets.
S&Fwd LB to FB Latency measurement offers the option of measuring the time from last data bit out to first data bit in
S&Fwd LB to FP Latency measurement offers the option of measuring the time from last data bit out to first preamble bit in
Ixia Hardware Guide 1-7
IntroductionIxia Load Module Properties1
Advanced PG Filter
A set of features which allow packet group matching to ignore or maskGroup IDSignatureFilter data
Round-trip flows Supports calculation of round-trip flows.
Data integrity Supports data integrity generation and checking.
First time stamp Supports first time stamp operation.
Sequence checking
Supports packet sequence generation and verification.
Sequence checking per packet ID
When packet groups are used, allows sequence checking generation and verification.
ISL encapsulation Receive side of port can accommodate ISL encapsulation on receive side.
Echo Will echo all received packets back to the network.
Small packets Supports the ability to capture packets smaller than a legal packet; capture data may be corrupted when this feature is used.
Transmit Modes Packet streams Supports the generation of packet streams.
Packet flows Supports the generation of packet flows.
Flow image file When packet flows are used, allows the data to come from a file.
Advanced scheduler
Supports the operation of the advanced scheduler, which allows inter-mixing of multiple packet streams.
Forced collisions Supports the insertion of forced collisions.
Data integrity Supports data integrity generation and checking.
Odd preamble Supports the ability to send a preamble with an odd number of bytes
Gap time units The inter-frame, -burst, and -stream gaps can be programmed in discreet units of time as opposed to indirectly through a percentage of maximums frame rate.
Modifiable preamble
The packet’s preamble may be modified.
Forced minimum gap
In advanced scheduler mode, a minimum gap may be enforced.
Increment frame size by N
Frame sizes may be incremented by an arbitrary value between transmitted frames.
Table 1-4. Ixia Load Module Feature Descriptions
Feature Category Feature Usage
1-8 Ixia Hardware Guide
IntroductionIxia Load Module Properties
Increment DS/SA by N
DA and SA values may be incremented by an arbitrary value between transmitted frames.
Random data on even offset only
When random data is generated within a frame’s content, the random data may only be placed at even byte boundaries.
Insert bad checksum
Supports the generation of bad checksums.
Hardware checksum
Hardware is used to generate the checksum, allowing the checksum to be correct for all combinations of generated frame overhead and contents.
Frequency offset The frequency for the card as a whole may be modified a few percent from nominal.
Echo The port echoes all received packets.
User Defined Fields (UDF)
Odd offset UDFs are allowed to start at an odd offset.
Overlap UDFs may overlap within a 4-octet boundary. Otherwise UDFs must start at least 4 octets apart.
Cascade UDFs may continue from previous stream values.
Split UDFs may be split into multiple 8-bit and 16-bit counters.
Bit mask UDFs output data may be masked with an arbitrary bit mask. Otherwise limitations on the number of changes of bits applies.
Incr By N Allows UDFs to increment by an arbitrary value.
UDF5 The port has a fifth UDF.
Advanced The port supports additional UDF features, including:Nested countersLinked listsStep sizeValue listRange list
POS / BERT POS Supports Packet over Sonet Operation.
BERT Supports Bit Error Rate Testing through the generation and verifications of patterns.
BERT error gen Supports BERT error insertion.
Error insertion list Support the insertion of Sonet errors.
SRP Supports Serial Reuse Protocol - passive receive.
SRP Full Supports Serial Reuse Protocol - active send/receive.
Table 1-4. Ixia Load Module Feature Descriptions
Feature Category Feature Usage
Ixia Hardware Guide 1-9
IntroductionIxia Load Module Properties1
Frame Relay Supports Frame Relay encapsulation.
Multiple DLCIs Supports the use of more than one DLCI in frame relay testing.
Unframed BERT Performs unframed BERT testing.
Channelized BERT
Support channelized BERT testing.
DCC Supports DCC channel operation.
10 Gigabit Ethernet WAN Supports 10 GE WAN operation.
LAN Supports 10 GE LAN operation.
XAUI Supports 10GE XAUI interface.
XENPAK Supports 10GE XENPAK interface.
Lane skew Supports the ability to skew multiple lanes.
Set pause destination address
The destination for pause control packets may be set.
Protocol Server Routing Supports advanced routing protocols, including BGP, IS-IS and OSPF.
ARP Supports ARP generation and receipt handling.
ARP rate control The rate at which multiple ARP packets are transmitted may be controlled.
IGMP rate control The rate at which multiple IGMP packets are transmitted may be controlled.
PING Supports PING generation and receipt handling.
LDP Support Label Distribution Protocol (LDP) testing.
RIPng Support RIP next generation protocol (RIPng).
Layer 2 VPN Supports Layer 2 VPNs based on LDP.
Layer 3 VPN Supports Layer 3 VPNs based on BGP4.
Local CPU Each port on the card is supported by an individual CPU for use in protocol server, IxWeb and other sophisticated operations.
IxWeb/IxRouter Supports use in IxWeb.
Table 1-4. Ixia Load Module Feature Descriptions
Feature Category Feature Usage
1-10 Ixia Hardware Guide
IntroductionIxia Load Module Properties
TABLE 1-5. Card Features Summary - Part 1
Card Name Stats Receive Modes
Qos
Stre
am tr
igge
r
Che
cksu
m e
rror
s
Dat
a in
tegr
ity
Tx D
urat
ion
Pack
et g
roup
s
S&Fw
d LB
to F
B
S&Fw
d LB
to F
P
Adv
ance
d PG
Filt
er
Rou
nd tr
ip fl
ows
Dat
a in
tegr
ity
Firs
t tim
e st
amp
Sequ
ence
che
ckin
g
Seq
Che
ck/P
GID
ISL
Enca
psul
atio
n
Smal
l Pac
kets
10/100
10/100 X X X X X X X X X
10/100-3 X X X X X X
10/100 TXS8 X X X X X X X X X
10/100 MII X X X X X X X X X
10/100 Reduced MII
X X X X X X X X X
10/100/1000
10/100/1000 TXS4 X X X X X X X X X X X
Copper 10/100/1000
X X X X X X X X X X X X
100Mbps
100Base FX MultiMode
X X X X X X X
100Base FX SingleMode
X X X X X X X
Gigabit
Gigabit X X X X X X X X X X X X
Gigabit-3 X X X X X X X
GBIC X X X X X X X X X X X X
Gigabit Single Mode
X X X X X X X X X X X X
1000 SFPS4 X X X X X X X X X X X
USB
Ethernet/USB X X X X X X X X
OC12c/OC3c
OC12c/OC3c POS X X X X X X X X X X X
OC12c POS 32MB X X X X X X X X X X
OC48
OC48c POS X X X X X X X X X X
Ixia Hardware Guide 1-11
IntroductionIxia Load Module Properties1
OC48c POS-M X X X X X X X X X X
OC48c POS VAR X X X X X X X X X X
OC48c BERT
OC48c POS/BERT X X X X X X X X X X
Unframed Bert
Single-Rate Unframed BERT
Multi-Rate Unframed BERT
OC192
OC192c POS X X X X X X X X X
OC192c BERT
OC192c POS/BERT
X X X X X X X X X
OC192c POS/10GE WAN
X X X X X X X X X X X
OC192c POS/BERT/10GE WAN
X X X X X X X X X X X
OC192c VSR POS X X X X X X X X X
OC192c VSR BERT
OC192c VSR POS/BERT
X X X X X X X X X
10GB
10GE WAN X X X X X X X X X X X
10GE BERT/WAN X X X X X X X X X X X
10GE LAN X X X X X X X X X X X
10GE LAN-M X X X X X X X X X X
10GE XAUI X X X X X X X X X X X
10GE XAUI/BERT X X X X X X X X X X X
10GE XAUI BERT
TABLE 1-5. Card Features Summary - Part 1
Card Name Stats Receive Modes
Qos
Stre
am tr
igge
r
Che
cksu
m e
rror
s
Dat
a in
tegr
ity
Tx D
urat
ion
Pack
et g
roup
s
S&Fw
d LB
to F
B
S&Fw
d LB
to F
P
Adv
ance
d PG
Filt
er
Rou
nd tr
ip fl
ows
Dat
a in
tegr
ity
Firs
t tim
e st
amp
Sequ
ence
che
ckin
g
Seq
Che
ck/P
GID
ISL
Enca
psul
atio
n
Smal
l Pac
kets
1-12 Ixia Hardware Guide
IntroductionIxia Load Module Properties
10GE XENPAK X X X X X X X X X X X
10GE XENPAK-M X X X X X X X X X X
TABLE 1-5. Card Features Summary - Part 1
Card Name Stats Receive Modes
Qos
Stre
am tr
igge
r
Che
cksu
m e
rror
s
Dat
a in
tegr
ity
Tx D
urat
ion
Pack
et g
roup
s
S&Fw
d LB
to F
B
S&Fw
d LB
to F
P
Adv
ance
d PG
Filt
er
Rou
nd tr
ip fl
ows
Dat
a in
tegr
ity
Firs
t tim
e st
amp
Sequ
ence
che
ckin
g
Seq
Che
ck/P
GID
ISL
Enca
psul
atio
n
Smal
l Pac
kets
Ixia Hardware Guide 1-13
IntroductionIxia Load Module Properties1
TABLE 1-6. Card Feature Summary - Part 2
Card Name Transmit Modes UDFs
Pack
et S
trea
ms
Pack
et F
low
sFl
ow im
age
file
Adv
ance
d Sc
hedu
ler
Forc
ed C
ollis
ions
Tx D
ata
Inte
grity
Odd
Pre
ambl
eG
ap T
ime
Uni
tsM
odifi
able
Pre
ambl
eFo
rced
Min
imum
Gap
Incr
Fra
me
Size
by
NIn
cr D
A/S
A b
y N
Ran
dom
Dat
a Ev
en O
ffset
Inse
rt B
ad C
heck
sum
sH
ardw
are
Che
cksu
mFr
eque
ncy
Offs
etEc
hoO
dd o
ffset
Ove
rlap
Cas
cade
Split
Bit
Mas
kIn
cr B
y N
UD
F5A
dvan
ced
10/100
10/100 X X X X X X X
10/100-3 X X X X X
10/100 TXS8 X X X X X X X X X X X X X
10/100 MII X X X X X X X
10/100 Reduced MII
X X X X X X X
10/100/1000
10/100/1000 TXS4 X X X X X X X X X X X X X X X X X
Copper 10/100/1000
X X X X X X X X
100Mbps
100Base FX MultiMode
X X X X X X X
100Base FX SingleMode
X X X X X X X
Gigabit
Gigabit X X X X X X X
Gigabit-3 X X X X X
GBIC X X X X X X X
Gigabit Single Mode
X X X X X X X
1000 SFPS4 X X X X X X X X X X X X X X X X X
USB
Ethernet/USB X X X X X X X
OC12c/OC3c
OC12c/OC3c POS X X X X
1-14 Ixia Hardware Guide
IntroductionIxia Load Module Properties
OC12c POS 32MB X X X X
OC48
OC48c POS X X X X X X X X X
OC48c POS-M X X X X X X X X X
OC48c POS VAR X X X X X X X X X
OC48c BERT
OC48c POS/BERT X X X X X X X X X
Unframed Bert
Single-Rate Unframed BERT
X
Multi-Rate Unframed BERT
X
OC192
OC192c POS X X X X X X X X X
OC192c BERT
OC192c POS/BERT
X X X X X X X X X
OC192c POS/10GE WAN
X X X X X X X X X X X
OC192c POS/BERT/10GE WAN
X X X X X X X X X X X
OC192c VSR POS X X X X X X X X X
OC192c VSR BERT
OC192c VSR POS/BERT
X X X X X X X X X
10GB
10GE WAN X X X X X X X X X X
10GE BERT/WAN X X X X X X X X X X
TABLE 1-6. Card Feature Summary - Part 2
Card Name Transmit Modes UDFs
Pack
et S
trea
ms
Pack
et F
low
sFl
ow im
age
file
Adv
ance
d Sc
hedu
ler
Forc
ed C
ollis
ions
Tx D
ata
Inte
grity
Odd
Pre
ambl
eG
ap T
ime
Uni
tsM
odifi
able
Pre
ambl
eFo
rced
Min
imum
Gap
Incr
Fra
me
Size
by
NIn
cr D
A/S
A b
y N
Ran
dom
Dat
a Ev
en O
ffset
Inse
rt B
ad C
heck
sum
sH
ardw
are
Che
cksu
mFr
eque
ncy
Offs
etEc
hoO
dd o
ffset
Ove
rlap
Cas
cade
Split
Bit
Mas
kIn
cr B
y N
UD
F5A
dvan
ced
Ixia Hardware Guide 1-15
IntroductionIxia Load Module Properties1
10GE LAN X X X X X X X X X X
10GE LAN-M X X X X X X X X X
10GE XAUI X X X X X X X X X X
10GE XAUI/BERT X X X X X X X X X X
10GE XAUI BERT
10GE XENPAK X X X X X X X X X X
10GE XENPAK-M X X X X X X X X X
TABLE 1-6. Card Feature Summary - Part 2
Card Name Transmit Modes UDFs
Pack
et S
trea
ms
Pack
et F
low
sFl
ow im
age
file
Adv
ance
d Sc
hedu
ler
Forc
ed C
ollis
ions
Tx D
ata
Inte
grity
Odd
Pre
ambl
eG
ap T
ime
Uni
tsM
odifi
able
Pre
ambl
eFo
rced
Min
imum
Gap
Incr
Fra
me
Size
by
NIn
cr D
A/S
A b
y N
Ran
dom
Dat
a Ev
en O
ffset
Inse
rt B
ad C
heck
sum
sH
ardw
are
Che
cksu
mFr
eque
ncy
Offs
etEc
hoO
dd o
ffset
Ove
rlap
Cas
cade
Split
Bit
Mas
kIn
cr B
y N
UD
F5A
dvan
ced
1-16 Ixia Hardware Guide
IntroductionIxia Load Module Properties
TABLE 1-7. Card Feature Summary - Part 3
Card Name POS/BERT 10GB Protocols
POS
BER
TB
ERT
err g
enEr
ror i
nser
t lis
tSR
PSR
P Fu
llM
ultip
le D
LCI
Unf
ram
ed B
ERT
Cha
nnel
ized
BER
TD
CC
WA
NLA
NXA
UI
Lane
Ske
wSe
t Pau
se D
est A
ddr
Rou
ting
AR
PA
RP
Rat
e C
ontr
olIG
MP
Rat
e C
ontr
olPI
NG
LDP
RIP
ngLa
yer 2
VPN
Laye
r 3 V
PNLo
cal C
PUIx
Web
/IxR
oute
r
10/100
10/100 X X X X X
10/100-3 X X X X
10/100 TXS8 X X X X X X X X X X
10/100 MII X X X X X
10/100 Reduced MII
X X X X X
10/100/1000
10/100/1000 TXS4 X X X X X X X X X
Copper 10/100/1000
X X X X X
100Mbps
100Base FX MultiMode
X X X X X
100Base FX SingleMode
X X X X X
Gigabit
Gigabit X X X X X
Gigabit-3 X X X X
GBIC X X X X X
Gigabit Single Mode
X X X X X
1000 SFPS4 X X X X X X X X
USB
Ethernet/USB X X X X X
OC12c/OC3c
OC12c/OC3c POS X X X X
OC12c POS 32MB X X X X
Ixia Hardware Guide 1-17
IntroductionIxia Load Module Properties1
OC48
OC48c POS X X X X X X X
OC48c POS-M X X X X X X
OC48c POS VAR X X X X X X X
OC48c BERT X X X X
OC48c POS/BERT X X X X X X X X X
Unframed Bert
Single-Rate Unframed BERT
X X X X
Multi-Rate Unframed BERT
X X X X
OC192
OC192c POS X X X X X X X X X
OC192c BERT X X X X
OC192c POS/BERT
X X X X X X X X X X X X
OC192c POS/10GE WAN
X X X X X X X X X X X X X X X X
OC192c POS/BERT/10GE WAN
X X X X X X X X X X X X X X X X X X X
OC192c VSR POS X X X X X X X X X
OC192c VSR BERT
X X X X
OC192c VSR POS/BERT
X X X X X X X X X X X X
10GB
10GE WAN X X X X X X X X X X
10GE BERT/WAN X X X X X X X X X X X X X
10GE LAN X X X X X X X X X X
10GE LAN-M X X X X X X X X X
TABLE 1-7. Card Feature Summary - Part 3
Card Name POS/BERT 10GB Protocols
POS
BER
TB
ERT
err g
enEr
ror i
nser
t lis
tSR
PSR
P Fu
llM
ultip
le D
LCI
Unf
ram
ed B
ERT
Cha
nnel
ized
BER
TD
CC
WA
NLA
NXA
UI
Lane
Ske
wSe
t Pau
se D
est A
ddr
Rou
ting
AR
PA
RP
Rat
e C
ontr
olIG
MP
Rat
e C
ontr
olPI
NG
LDP
RIP
ngLa
yer 2
VPN
Laye
r 3 V
PNLo
cal C
PUIx
Web
/IxR
oute
r
1-18 Ixia Hardware Guide
IntroductionCard Properties
Card PropertiesThe load module chapters include the card characteristics described in Table 1-8 on page 1-19.
10GE XAUI X X X X X X X X X X X
10GE XAUI/BERT X X X X X X X X X X X X X X
10GE XAUI BERT X X X X X X
10GE XENPAK X X X X X X X X X X X X
10GE XENPAK-M X X X X X X X X X X X
TABLE 1-7. Card Feature Summary - Part 3
Card Name POS/BERT 10GB Protocols
POS
BER
TB
ERT
err g
enEr
ror i
nser
t lis
tSR
PSR
P Fu
llM
ultip
le D
LCI
Unf
ram
ed B
ERT
Cha
nnel
ized
BER
TD
CC
WA
NLA
NXA
UI
Lane
Ske
wSe
t Pau
se D
est A
ddr
Rou
ting
AR
PA
RP
Rat
e C
ontr
olIG
MP
Rat
e C
ontr
olPI
NG
LDP
RIP
ngLa
yer 2
VPN
Laye
r 3 V
PNLo
cal C
PUIx
Web
/IxR
oute
r
Table 1-8. Card Specifications
Specification Usage
# ports The number of ports supported by the card(s).
-3/-M Card Available Whether a limited feature card is available.
Data Rate The choice of data rates offered by the card.
Connector/Frequency-Mode The connector type used on the card. For optical connections, the light frequency used and whether the fiber is used for singlemode or multimode.
Capture buffer size The size of each port’s capture buffer.
Captured packet size The range of packet sizes that may be captured on the card.
Streams per port The number of streams available on each port.
Flows per port The number of stream flows available on each port. If available, this is always 15,872
Advanced streams The number of advanced streams available on each port.
Preamble size: min-max The range of sizes, in bytes, for generated preambles.
Ixia Hardware Guide 1-19
IntroductionCard Properties1
One important characteristics, number of captured packets, cannot be expressed as a simple number. It is dependent on a number of factors:
• Size of the capture buffer
• Size of the captured packet
• Size of the capture slice, set by the user
• Memory used by other functions
• Memory overhead per captured packet
The general equation is:
# of captured packets = (size of capture buffer) - (memory used by other functions)
(min (captured packet, capture slice) + (per packet overhead)
To get the best idea of the memory available for packet capture, a set of simple experiments can be run. For example, the following table indicates the measured number of packets captured for different packet sizes. The type of card used was an LM100TX, which has a 2MB capture buffer. The buffer slice was set to 8191.
The experiment indicates that there is approximately1.8 MB available for data capture.
Frame size: min-max The range of sizes, in bytes, for generated frames.
Inter-frame gap: min-max The gap between frames, expressed as a range of time.
Inter-burst gap: min-max The gap between bursts of frames, expressed as a range of time.
Inter-stream gap: min-max The gap between streams, expressed as a range of time. Sometimes expressed as a percentage of the maximum rate.
latency The accuracy of latency operations.
Table 1-9. Measured Number of Packets for an LM100TX Card
Packet Size Number of Packets Captured
Memory used by Captured Packets
64 bytes 18,668 1,194,752
1K bytes 1,698 1,738,752
4K bytes 436 1,785,856
8K bytes 219 1,794,048
Table 1-8. Card Specifications
Specification Usage
1-20 Ixia Hardware Guide
IntroductionWhat’s New in Version 3.65
What’s New in Version 3.65The following items are new products or information in this Hardware Guide.
IXIA 250 The IXIA 250 is a new, portable Ixia chassis with a built-in keyboard and screen. It contains a single 10/100/1000 or 1000 port and has room to accommodate up to two Ixia load modules. Refer to:
• Chapter 6, IXIA 250 Chassis
10/100/1000 Cards A new family of cards is now available:
• LM1000TXS4 – four port, triple speed with integral processor. Refer to: Chapter 10, IXIA 10/100/1000 Load Modules.
• LM1000SFPS4 – four port fiber or copper Gigabit load module with integral processor. Refer to: Chapter 12, IXIA Gigabit Load Modules.
10GE Cards Additional cards have been added to the 10GE card family. Refer to:
• Chapter 18, IXIA 10Gigabit Ethernet Load Modules.
RMII Interface Additional details on the 10/100RMII interface have been added. Refer to:
• Appendix C, LM-RMII Interface Specification.
Ixia Hardware Guide 1-21
IntroductionWhat’s New in Version 3.651
1-22 Ixia Hardware Guide
2Chapter 2: Installation and Initial Configuration
This chapter discusses the installation and initial configuration for the Ixia Hardware.
Ixia HardwareFour Ixia Hardware chassis are available:
• IXIA 1600 Chassis–capable of holding up to 16 Ixia Load Modules.
• IXIA 1600T Chassis–capable of holding up to 16 Ixia Load Modules and equipped with extra power and fans required for some high-powered load modules.
• IXIA 400 Chassis–capable of holding up to 4 Ixia Load Modules. Revision C or higher IXIA 400 chassis are required to handle the extra power and cooling required for some of the high-powered load modules.
• Clocking - IXIA 100 and IxClock Modules–the IXIA 100 is capable of hold-ing 1 Ixia Load Module and includes a built-in GPS or CDMA receiver. Appendix A contains the specification of the GPS hardware.
Unpacking the Ixia Chassis
Each chassis comes packed in its own box. Carefully remove all of the pieces from the box and check that you have all of the components listed below:
IXIA 100, 400, 1600, 1600T or Optixia chassis Power cord Right and left ear brackets and screws, for rack mounting
(IXIA 100 and 1600 only) Y splitter cable (IXIA 100 and 400 only) Chassis sync cable The following documentation items, possibly shipped
separately: Windows 2000 certificate of authenticity
This Quickstart Guide
Ixia Hardware Guide 2-1
Installation and Initial ConfigurationInitial Configuration2
Notes and Warnings • Voltage. The Ixia chassis all utilize voltage from 100VAC to 240VAC at 50/60Hz. Current is from 20A to 2.25A.
• Power cord. Use the power cord provided or a power cord approved by the appropriate agency for use in the country where the unit is being used. The power source should be properly grounded.
• Ventilation requirements. For the IXIA 1600 and Optixia, do not block the bottom or the back. For the IXIA1600T, 400 and 100, do not block the back or sides.
• Rack mounting. Two rack-mount ears are provided which are designed to fit a generic 19” electronic rack, along with 6 black flat-head screws. First, attach the ears to the unit, and then attach the unit by the ears to the rack by a method appropriate for the rack.
• Maintenance instructions. The only user maintainable feature is changing the fuse, if it blows. Only replace the fuse with one of the same size and rating as what is installed. The fuse drawer, located near the power cord, pulls out with a small flat-bladed screwdriver. Note that repeated fuse blowing may likely indicate some internal problem; you should reporting the problem to Ixia Technical Support. Clean intake grills periodically to permit good airflow intake.
Initial ConfigurationThe Ixia Chassis comes pre-loaded with IxServer and IxExplorer software along with Windows 2000. The chassis includes an internal industry-standard PC hard-ware platform. In order to perform initial configuration, it is necessary for you to obtain the components below and to attach them to the appropriate connectors on the back of the chassis:
• SVGA monitor
• PS/2-style keyboard
• PS/2-style mouse
The TCP/IP networking on the chassis must be configured first. In order to con-figure TCP/IP, follow the steps below:
1. Attach the monitor, keyboard and mouse to the ports on the back of the 1600, 400 or 100 chassis or the front of the Optixia chassis as shown in the figures below.
NOTE: Any of the Ixia chassis must always be operated with the chassis cover closed and with all card face plates mounted.
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Installation and Initial ConfigurationInitial Configuration
Figure 2-1. Rear View of IXIA 1600 Chassis
Figure 2-2. Rear View of IXIA 400 Chassis with Serial Mouse
Mouse
Keyboard
Monitor
Serial Mouse
PS-2 Keyboard
Monitor
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Installation and Initial ConfigurationInitial Configuration2
Figure 2-3. Rear View of IXIA 400 Chassis with PS-2 Keyboard and Mouse
Figure 2-4. Front View of Optixia Chassis with PS-2 Keyboard, Mouse and Monitor
An additional ‘Y’ connector, shown in Figure 2-5 on page 2-5, is included with the IXIA 400 chassis when a PS-2 keyboard and a PS-2 mouse are both required. This is the lower pictured cable.
DIN KeyboardPS-2 Mouse
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Installation and Initial ConfigurationInitial Configuration
Figure 2-5. IXIA 100/400 Supplied Cables
Similarly, the IXIA100 has two possible sets of cable connections, based on the availability of a serial mouse. This is shown in the following two figures:
Figure 2-6. IXIA 100 Chassis with Serial Mouse
Monitor
PS-2 Keyboard
Serial Mouse Network
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Installation and Initial ConfigurationInitial Configuration2
Figure 2-7. IXIA 100 Chassis with PS-2 Mouse
Figure 2-8. IXIA 100 Chassis Antenna Connection
2. Attach the power cord to the chassis and then to the wall socket. Switch the master power switch to ‘1’ (on).
3. Power on the chassis by depressing the power button on the front of the chas-sis.
4. Verify that the monitor screen appears as shown below
PS-2 Keyboard
PS-2 Mouse
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Installation and Initial ConfigurationWindows 95 Configuration
Figure 2-9. Initial Screen Display from Locally Connected Monitor
Windows 95 Configuration
Windows 95 TCP/IP Configuration
The network address of the chassis must now be set, even if the network will not be used.
1. To do this right click on the Network Neighborhood icon and select Properties with the left mouse button:
Figure 2-10. Mouse Clicks to Invoke Network Properties Dialog
2. The Network Menu is then displayed and is shown below. Select the Identifi-cation tab.:
Right Click
Left Click
Ixia Hardware Guide 2-7
Installation and Initial ConfigurationWindows 95 Configuration2
Figure 2-11. Network Properties Dialog - Configuration
3. The Identification tab is shown below. Note the value in the ‘Computer Name’ field - we will refer to this as the Host ID at a later time when running the IxExplorer. Press OK and go back to the Configuration tab.
Figure 2-12. Network Properties Dialog - Identification
4. Now double left click on the TCP/IP entry to get the TCP/IP dialog shown below.
Figure 2-13. IP Address Dialog
5. This setting reflects the default factory setup for your chassis. It is configured to utilize DHCP in order to discover all network aspects for your chassis. If you have a DHCP server on the network attached to the chassis, then this is
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Installation and Initial ConfigurationWindows 95 Configuration
the appropriate configuration of your chassis; skip the remainder of this sec-tion. If no DHCP server is found on the network, then your chassis will not be accessible from your network. Again this might be appropriate for your net-work.
6. If the chassis is to be attached to an existing network, then obtain the values shown in the table of IP values from your network administrator and enter them on the appropriate TCP/IP Properties sheet. Only a subset of all of the parameters are shown here, your administrator might suggest other options. The IP address is an important quantity that you will need; write it down for later use. Plug your network cable into the RJ-45 plug pictured above. [Note: the Ixia chassis will generate a great deal of network traffic when applying input sequences and sensing results. It may not be wise to connect one or more chassis to a widely used network without the aid of a network switch, bridge or similar device.
The table of TCP/IP Networking Parameters is shown below:
7. Click OK and Windows will ask you if you wish to reboot. Answer ‘YES’.
Table 2-1. TCP/IP Networking Parameters
Property Sheet Parameter Usage
IP Address IP Address Single IP address for the chassis. Note: DHCP may not be used to set the IP address of the chassis.
IP Address Subnet Mask Subnet mask for the IP address.
Gateway New Gateways The IP addresses of the gateways for the network.
DNS Configuration
Disable/Enable DNS Resolution
If your network uses the Domain Name Service for name resolution, then enable it here.
DNS Configuration
Host / Domain The assigned host name and IP domain that the chassis will operate within.
DNS Configuration
DNS Search Order An ordered list of DNS servers to be used for name lookups.
WINS Configuration
Disable/Enable WINS Resolution
If your network uses Microsoft Windows Name Service, then enable it here.
WINSConfiguration
Primary/Secondary WINS Servers
Values for the primary and (optional) secondary WINS servers.
Bindings Client for Microsoft Networks
If information on other networked systems is to be accessed via Microsoft file sharing, this should be checked.
Bindings File and printer sharing for Microsoft Networks
If information or printers are to be shared via Microsoft file sharing, this should be checked
Ixia Hardware Guide 2-9
Installation and Initial ConfigurationWindows 95 Configuration2
Windows 95 General Configuration
The Windows 95 initial configuration includes some features which make the chassis more robust and easier to use:
1. The time zone of the computer has been set to GMT, with Daylight Saving Time disabled. To change this, right-click on the time in the lower left corner of the screen and then left-click on Adjust Date/Time, as shown in Figure 2-14.
Figure 2-14. Accessing the Time Zone Dialog
The Date / Time Properties dialog, as shown in Figure 2-15, is displayed.
Figure 2-15. Date/Time Properties Dialog
2. First select the Time Zone tab from the dialog and adjust the time zone and daylight savings time settings as appropriate, as shown in Figure 2-16, then return to the Date & Time tab to set the current time in your time zone.
Right Click
Left Click
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Installation and Initial ConfigurationWindows 2000 Configuration
Figure 2-16. Date/Time Properties - Time Zone Tab
3. An anti-virus scanner is installed and scheduled to run a full system scan every Saturday morning at 4AM. If this interferes with tests which run during this period, then the schedule may be changed by double clicking on the tool-bar icon as shown in Figure 2-17.
Figure 2-17. Accessing Anti-Virus Configuration
Windows 2000 Configuration
Windows 2000 TCP/IP Configuration
The network address of the chassis must now be set, even if the network will not be used.
1. To do this left click on the following sequence of items: Start (in the lower-left hand corner of your screen), Settings, Network and Dialup Connections and Local Area Connection, as shown below:
Double Click
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Installation and Initial ConfigurationWindows 2000 Configuration2
Figure 2-18. Mouse Clicks to Invoke Network Properties Dialog
2. The Local Area Connection Status dialog will open, as shown below.
Figure 2-19. Local Area Connection Status Dialog
3. Click the Properties button, and the Local Area Connection Properties dialog will open, as shown below:.
Figure 2-20. Local Area Connection Properties Dialog
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Installation and Initial ConfigurationWindows 2000 Configuration
4. In the Local Area Connection Properties dialog, check the boxes for the fol-lowing items:
• Internet Protocol (TCP/IP) - required
• Client for Microsoft Networks - if information on other networked systems is to be accessed via Microsoft file sharing, this should be checked.
• File and printer sharing for Microsoft Networks - if information or printers are to be shared via Microsoft file sharing, this should be checked.
5. Double click on the Internet Protocol TCP/IP entry or press the Properties button to open the Internet Protocol (TCP/IP) Properties dialog shown below:
Figure 2-21. Default Internet Protocol (TCP/IP) Properties
6. This setting reflects the default factory setup for your chassis. It is configured to utilize DHCP in order to discover all network aspects for your chassis. If you have a DHCP server on the network attached to the chassis, then this is the appropriate configuration of your chassis; proceed to step 11. If no DHCP server is found on the network, then Windows 2000 will automatically assign a unique IP address in the 169.254.0.0–169.254.255.255 range. Again this might be appropriate for your network. If you need to assign a particular IP address to your chassis, then fill in the fields as shown below and explained in the following table:
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Installation and Initial ConfigurationWindows 2000 Configuration2
Figure 2-22. Internet Protocol (TCP/IP) Properties for a Static Address
Table 2-2. Internet Protocol (TCP/IP) Settings
Property Sheet
Category Parameter Usage
General Obtain an IP address automatically
If selected, the fields for IP address are disabled, and the button for Obtain DNS server address automatically is selected.
Use the following IP address:
If selected, the fields below become active for manual configuration of the IP address information.
IP Address The single IP address for this chassis.
Subnet Mask The IP subnet mask to be used with this IP address.
Default Gateway
The IP address of the gateway for the network.
Obtain DNS server address automatically
If selected, the IP address for the server providing Domain Name Service for name resolution is obtained automatically from the local DHCP server.
Use the following DNS server addresses
If selected, the fields below become active for manual entry of the IP addresses for the DNS servers.
Preferred DNS server:
The IP address for the preferred DNS server.
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Installation and Initial ConfigurationWindows 2000 Configuration
7. You will need to refer to the Host ID at a later time when running IxExplorer. This name must be assigned in the My Computer > Identification Changes Window. First right-click on the My Computer icon on the desktop to display the popup menu, as shown below.
Figure 2-23. Mouse Clicks to Invoke System Properties Dialog
8. Left-click on Properties to display the System Properties dialog as shown below.
Figure 2-24. System Properties Dialog - Network Identification Tab
9. On the Network Identification tab, press the Properties button to display the Identification Changes dialog shown below.
Alternate DNS server:
The IP address for an alternate DNS server.
Advanced When this button is pressed, the Advanced TCP/IP Settings dialog is displayed. These settings are not covered here.
Table 2-2. Internet Protocol (TCP/IP) Settings
Property Sheet
Category Parameter Usage
Right Click
Left Click
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Installation and Initial ConfigurationWindows 2000 Configuration2
Figure 2-25. Identification Changes
10. The Computer Name shown in Figure 2-25 is an example of the pre-config-ured name assigned to each chassis. Each chassis’ name is of the form <TYPE>-<SERIALNO>. <TYPE> is either 100, 400, 1600 or Optixia corre-sponding to the type of chassis. <SERIALNO> is the chassis serial number and is always six digits long. By default, each chassis is also a member of the IXIA workgroup. This may be changed at this time to another workgroup or as a member of a Windows NT/2000 domain. If any changes have been made, Windows will ask you if you wish to reboot. Answer ‘YES’.
Windows 2000 General Configuration
The Windows 2000 initial configuration includes some features which make the chassis more robust:
1. Windows 2000 Service Pack 1 has been applied. This Microsoft Certified software increases the operating system security.
2. The time zone of the computer has been set to GMT, with Daylight Saving Time disabled. To change this, right-click on the time in the lower left corner of the screen and then select Adjust Date/Time.
Figure 2-26. Accessing the Time Zone Dialog
The Date / Time Properties dialog, as shown in Figure 2-27, is displayed.
Right Click
Left Click
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Installation and Initial ConfigurationWindows 2000 Configuration
Figure 2-27. Date/Time Properties Dialog
First select the Time Zone tab from the dialog and adjust the time zone and daylight savings time settings as appropriate, as shown in Figure 2-28, then return to the Date & Time tab to set the current time in your time zone.
Figure 2-28. Date/Time Properties - Time Zone Tab
3. An NTP (Network Time Protocol) service automatically runs. If your chassis is connected to the Internet, it will keep the system clock on your chassis accurate. If your chassis is not connected to the Internet, the NTP service will have no adverse effects.
4. An anti-virus scanner is installed and scheduled to run a full system scan every Saturday morning at 4AM. If this interferes with tests which run during this period, then the schedule may be changed by double clicking on the tool-bar icon as shown in Figure 2-29.
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Installation and Initial ConfigurationWindows 2000 Configuration2
Figure 2-29. Accessing Anti-Virus Configuration
Windows 2000 Security Settings
This section includes some important notes on passwords and other security set-tings.
1. The password for the Administrator account is the word ixia (all lower case). The Administrator account is responsible for system maintenance and may perform any operation on the system. It is strongly suggested that this pass-word be changed as soon as you receive your chassis. To perform this opera-tion, select the Manage dialog from the My Computer icon, as shown in Figure 2-30.
Figure 2-30. Accessing Computer Management
Followed by a selection of Users on the management screen, as shown in Figure 2-31.
Figure 2-31. Change Password for Administrator
2. In the dialog (shown in Figure 2-31), select the Administrator entry, right-click and select Set Password. In the form that pops up, set the new password twice and press OK.
3. A user account has also been created for use during normal test operation. It is named IXIA-<SERIALNO>, where <SERIALNO> is the serial number of the chassis. This user is automatically logged in when the chassis is powered on. This user account does not have a password associated with it. If you wish to
Double Click
Right Click
Select
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Installation and Initial ConfigurationLocal/Remote Operation
change the password for this account, you must do two things. First, change the password as discussed in Step 2. Second, set the password into the system entry used for the automatic login at boot time. This is accomplished through the use of Tweak UI which can be accessed through the Start button as shown in Figure 2-32.
Figure 2-32. Accessing Tweak UI
Tweak UI allows a number of different items to be adjusted. Select the Logon tab in the dialog and set the same password used for the IXIA-<SERIALNO> user into this dialog. This is shown in Figure 2-33.
Figure 2-33. Setting the Password Associated with the Default User
4. When accessing the chassis’ disk drive remotely via another computer’s Net-work Neighborhood choice in a Windows Explorer window, a user account and password must be given. Use the IXIA-<SERIALNO> account and pass-word defined above (or empty if it has not been changed).
Local/Remote OperationThe IxExplorer software is the user’s primary tool for navigation, configuration, and control of the Ixia hardware. You may use IxExplorer either from the monitor attached directly to the chassis or from a system connected to the network attached to the chassis. After initial configuration, the monitor, keyboard and mouse need not remain attached to the chassis. If the IxExplorer software is to be used from a remote system, the software must be installed there; this is covered below.
Ixia Hardware Guide 2-19
Installation and Initial ConfigurationPowering Up2
Powering UpTo power up the chassis, press the power button on the front of the chassis. If a monitor is connected to the chassis, then the initial screen should be as pictured in Figure 2-9 on page 2-7.
The IxServer software is the agent that interfaces directly to the hardware of the chassis. It is started automatically at power-up and the software’s viewable out-put is primarily intended as a diagnostic tool for the Ixia hardware. IxExplorer can now be started locally by double-clicking on the IxExplorer icon on the Win-dows desktop, shown below:
Shutting DownTo shut down the chassis, if you are using the monitor attached to the chassis itself, you can use any of the three following techniques:
• From IxExplorer, select the chassis in the tree view, click on “Tools” and choose “Shutdown”
• Close IxExplorer, and shut down Windows normally by using the “Shut-down” option from the Start menu
• Depress the power button on the front of the chassis
If you are using IxExplorer remotely, you can shut down the chassis by:
• From IxExplorer, select the chassis in the tree view, click on “Tools” and choose “Shutdown”
If no monitor attached directly to the chassis, you can also:
• Depress the power button on the front of the chassis
All of these options will invoke a graceful shutdown of Windows, and turn off the power supply in the chassis. When the chassis is powered off but still getting AC power, the green “Standby” LED on the front of the chassis will be lit. Try to avoid powering down the unit by removing AC power or turning off the power switch at the AC power input module on the rear of the chassis, as this may cause file system problems.
File-SharingIxia chassis are shipped with File Sharing to its disk enabled, but set to Read-Only mode. If the chassis is connected to a network, care should be taken to pro-tect the contents of the disk as with any computer system. No non-essential soft-
NOTE: The chassis must be powered off before installing or removing load modules.
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Installation and Initial ConfigurationChassis Chaining
ware should be installed, nor should the type of File Sharing be set to Read-Write without restricting the scope of file sharing and/or establishing procedures to ensure that the system is used properly and that it can be restored from a known-good backup.
Chassis ChainingRegardless of which Ixia chassis you have, up to 256 chassis may be linked together into a chassis chain. In order to chain any two chassis together, use only the Ixia supplied cables to connect the Sync Out from one chassis to the Sync In of the next chassis in the chain, as shown below. The chassis whose Sync In is not connected is the Master of the chain. The IxExplorer software automatically determines the master in the chain and the chain order.
Figure 2-34. Chassis Chaining Using Sync Out / Sync In Ports
Sync Out
Sync In
NOTE: Chained chassis are sensitive to the order in which chassis are brought up and to any disconnection of sync cables. Always bring up chained chassis in the order in which they are chained. If a sync cable is disconnected, reconnect the cable and shutdown all chassis and bring them up in the same order.
Ixia Hardware Guide 2-21
Installation and Initial ConfigurationChassis Chaining2
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3Chapter 3: IXIA 1600 Chassis
The Ixia 1600 chassis has 16 slots for Ixia Load Modules. It is shown in Figure 3-1.
Figure 3-1. Ixia 1600 Chassis
SpecificationsThe chassis specifications are contained in Table 3-1.Table 3-1. Ixia 1600 Chassis Specifications
General Fully integrated PC with 10/100 NIC.
Physical
Load Module Slots 16
Size 17.5”w x 9.6”h x 20.4”d (44.5cm x 24cm x 52cm)
Weight (empty) 25.5lbs (11.6kg)
Avg. Shipping Wt. 29lbs (13.2kg)
Ixia Hardware Guide 3-1
IXIA 1600 ChassisSpecifications3
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 50°F to 104°F, (10°C to 40°C)
Storage 50°F to 122°F, (10°C to 50°C)
Humidity
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing
Clearance Rear: 4 in (10 cm); fan openings should be clear of all cables or other obstructions. Bottom: 3/4 in (1.75cm). Top and sides: none.
Front Panel Switches On/Off momentary power push button
Back Panel Switches On/Off rocker switch
Front Panel Indicators Power, Standby, Master, External Clock
Back Panel Connectors
Power Male receptacle6 AMP @110V or 3AMP @ 220V, 60/50Hz
Mouse PS/2 6-pin DIN
Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100Mbps
Serial 2 male DB9 ports
Table 3-1. Ixia 1600 Chassis Specifications
3-2 Ixia Hardware Guide
4Chapter 4: IXIA 1600T Chassis
The IXIA 1600T chassis has 16 slots for Ixia Load Modules, but may also be used to support the high-powered load modules, including all OC192 and 10GB modules. The IXIA 1600T Chassis is specifically designed to accommodate up to eight OC192 Load Modules. It has an enhanced power supply, providing more than three times the power of the standard IXIA 1600. Additional cooling fans have been added to the 1600T to meet the requirements of the OC192 modules. The IXIA 1600T is shown in Figure 4-1.
Figure 4-1. Ixia 1600T Chassis
Ixia Hardware Guide 4-1
IXIA 1600T ChassisSpecifications4
SpecificationsThe chassis specifications are contained in Table 4-1.Table 4-1. Ixia 1600T Chassis Specifications
General Fully integrated PC with 10/100 NIC.
Physical
Load Module Slots 16
Size 17.5”w x 15.7”h x 20.4”d (44.5cm x 39.9cm x 52cm)
Weight (empty) 47lbs (21kg)
Avg. Shipping Wt. 51lbs (23kg)
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 50°F to 104°F, (10°C to 40°C)
Storage 50°F to 122°F, (10°C to 50°C)
Humidity
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing
Clearance Rear: 4 in (10 cm); fan openings should be clear of all cables or other obstructions. Bottom: 1 in (2.5cm). Top and sides: none.
Front Panel Switches On/Off momentary power push button
Back Panel Switches On/Off rocker switch
Front Panel Indicators Power, Standby, Master, External Clock
Back Panel Connectors
Power Male receptacle20 AMP @110V or 10AMP @ 220V, 60/50Hz
Mouse PS/2 6-pin DIN
Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100Mbps
Serial 2 male DB9 ports
4-2 Ixia Hardware Guide
IXIA 1600T ChassisInstalling Filler Panels
Installing Filler PanelsWhen using the IXIA 1600T for fewer than eight OC192 modules, it is best to redirect the airflow to the installed load modules in order to optimize operating conditions. Consequently, 1-slot and 4-slot 1600T cover plates have been designed to redirect the airflow to the installed load modules from empty slots.
The following components are included with each IXIA 1600T:
• Three 4-slot wide 1600T Filler Panel units (p/n 652-0118)
• Two 1-slot wide 1600T Filler Panel units (p/n 652-0117)
• Screws for attaching the panel faceplates to the chassis
Prerequisites for Baffle Unit Installation:
WARNING: Power to the chassis must be OFF!
• The technician should use industry-standard grounding techniques, such as wrist and ankle grounding straps, to prevent damage to electronic compo-nents on the OC192 Load Modules.
• The chassis should be placed in a horizontal position, in a well-lighted work area.
• The OC192 Load Module(s) must have been previously installed, per the instructions, and with the installation order in the following table.
Insert one or more OC192 modules into the chassis as indicated by the Table 4-2 on page 4-4.
The filler panels are required when there are empty slots in the chassis. However, any other Ixia load modules, such as 10/100, Gigabit, OC12/3c, and OC48c, can be installed in the chassis, alongside the OC192c load modules. First, insert the OC192c load modules into the respective slots, as described in the second col-
Table 4-2. Slot Preferences for Installing Multiple OC192 Load Modules
Module Slots Filler Panels Required
1st 11 & 12 (3) 4-slot and (2) 1-slot
2nd 5 & 6 (3) 4-slot
3rd 8 & 9 (2) 4-slot and (2) 1-slot
4th 14 & 15 (1) 4-slot and (4) 1-slot
5th 2 & 3 (6) 1-slot
6th 1 & 2 (4) 1-slot (shift the 5th module to slots 3 & 4)
7th 7 & 8 (2) 1-slot (shift the 3rd module to slots 9 & 10)
8th 13 & 14 None (shift the 4th module to slots 15 & 16)
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IXIA 1600T ChassisInstalling Filler Panels4
umn of the table above. Second, install any other load modules in any empty slots. Last, fill the remaining slots with the filler panels.
Baffle Unit Installation Procedure:
ESD WARNING:Use industry-standard grounding techniques to prevent Elec-trostatic Damage to the delicate electronic components on the OC192 Load Mod-ules.
1. Verify that the chassis is powered OFF and the power cable is unplugged.
2. To install a 4-slot filler panel:
Example: Slide the 4-slot filler panel, with the Ixia logo at the top, into Slots 1 through 4, or as indicated in the Slot Preference table above. The panel slides in on the slot rails in the chassis. (See Figure 4-2 on page 4-4) Secure the faceplate of the filler panel to the chassis with 4 of the supplied screws.
Use Extreme Care to prevent damage to delicate electronic components on the load module.
Figure 4-2. Installing a 4-Slot Filler Panel
3. To install a 1-slot filler panel:
Example: Slide the 1-slot filler panel, with the Ixia logo at the top, into the correct slot, per the Slot Preference table above. The panel slides in on the slot rails in the chassis. (See Figure 4-3 on page 4-5.) Secure the faceplate of the filler panel to the chassis with 2 of the supplied screws.
Use Extreme Care to prevent damage to delicate electronic components on the load module.
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IXIA 1600T ChassisInstalling Filler Panels
Figure 4-3. Installing a 1-Slot Filler Panel
Ixia Hardware Guide 4-5
IXIA 1600T ChassisInstalling Filler Panels4
4-6 Ixia Hardware Guide
5Chapter 5: IXIA 400 Chassis
The IXIA 400 chassis has 4 slots for Ixia Load Modules The IXIA 400 is shown in Figure 5-1 on page 5-1. Revision C or higher is required to support high-pow-ered load modules, including OC192, 10GB and 10/100TSX8 modules. Rev C or higher will handle one, one-port card and Rev L or higher will support one two-port card.
Figure 5-1. Ixia 400 Chassis
Ixia Hardware Guide 5-1
IXIA 400 ChassisSpecifications5
SpecificationsThe chassis specifications are contained in Table 5-1 on page 5-2.Table 5-1. Ixia 400 Chassis Specifications
General Fully integrated PC with 10/100 NIC.
Physical
Load Module Slots 4
Size 10.25”w x 5.75”h x 16”d (26.1cm x 14.6cm x 40.6cm)
Weight (empty) 10lbs (4.5kg)
Avg. Shipping Wt. 16lbs (7.3kg)
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 50°F to 104°F, (10°C to 40°C)
Storage 50°F to 122°F, (10°C to 50°C)
Humidity
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing
Front Panel Switches On/Off momentary power push button
Back Panel Switches On/Off rocker switch
Front Panel Indicators Power, Master, External Clock
Back Panel Connectors
Power Male receptacle
Mouse & Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100Mbps
Serial 2 male DB9 ports
5-2 Ixia Hardware Guide
6Chapter 6: IXIA 250 Chassis
The IXIA 250 is a Field Service Unit (FSU) chassis with a built-in 10/100/1000 port and an additional 2 slots for Ixia Load Modules The IXIA 250 is shown in Figure 6-1.
Figure 6-1. IXIA 250 Chassis
Ixia Hardware Guide 6-1
IXIA 250 ChassisOperation6
Operation
Setup The IXIA 250 incorporates an adjustable support, shown collapsed in Figure 6-2 and extended in Figure 6-3.
Figure 6-2. IXIA 250 Integrated Support (Collapsed)
Figure 6-3. IXIA 250 Integrated Support (Extended)
The support is extended by placing your thumbs in the recesses at the top and pushing down as shown in Figure 6-4. Make sure that the stand is stable in one of its available locking positions.
6-2 Ixia Hardware Guide
IXIA 250 ChassisOperation
Figure 6-4. IXIA 250 Integrated Support Operation
The keyboard is released by pressing on the button at the top of the chassis, as shown in Figure 6-5.
Figure 6-5. IXIA 250 Keyboard Release
Power is applied to the unit by plugging it in and toggling the “1/0” switch as shown in Figure 6-6.
Ixia Hardware Guide 6-3
IXIA 250 ChassisOperation6
Figure 6-6. IXIA 250 Power
This applies power to the chassis, but does not turn on the computer within. The separate Standby switch must be pressed, as shown in Figure 6-7. This may also be used to put the computer into standby mode at a later time. Should the IXIA 250 experience a power failure, it will not automatically boot the operating sys-tem.
Figure 6-7. IXIA 250 Standby Switch
Computer Operation
The computer on the IXIA 250 is operated as with any other computer system running Windows 2000. The keyboard is used for all typed input. The touchpad at the bottom of the keyboard, as shown in Figure 6-8, is used to position the cur-sor and ‘click’ the left and right mouse buttons.
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IXIA 250 ChassisOperation
Figure 6-8. IXIA 250 Keyboard and Touchpad
Just put your index finger on the touchpad and move it around, following the cur-sor on the screen. Use the buttons under the touchpad as you would the left and right mouse buttons on a mouse. Double tapping on the keyboard is equivalent to a double-mouse click. Pressing in the shaded area at the top-right of the touchpad is equivalent to a right mouse button click.
The intensity of the LCD screen is controlled by the slide switch at the top right of the keyboard.
In addition to the use of the touchpad, an external mouse may be connected to the Keyboard/Mouse port at the back of the chassis. Further, the LCD screen is touch sensitive and may be used as an alternative to the touchpad or mouse. Touching the screen is equivalent to pressing and holding the left mouse button at that point and taking your finger off the screen is equivalent to releasing the mouse button.
An external keyboard may be attached to the Keyboard/Mouse port at the back of the chassis. When both an external mouse and keyboard are required, they may be attached with the use of the supplied ‘Y’ adapter, as shown in Figure 6-9. Attach the keyboard and mouse to either connector.
Figure 6-9. IXIA 250 Keyboard/Mouse ‘Y’ Adapter
Touchpad
Left buttonRight button
LCD Brightness
Right button
Keyboard ormouse connectors
Ixia Hardware Guide 6-5
IXIA 250 ChassisOperation6
The rear panel of the IXIA 250 contains additional connectors for external devices. This is shown in Figure 6-11 and further explained in Table 6-1.
A floppy drive and access to the hard disk is provided on the left rear of the chas-sis, as shown in Figure 6-10.
Figure 6-10. IXIA 250 Floppy and Hard Drive Access
Test Operation Device testing may be accomplished using the built-in port or by plugging in additional Ixia load modules. Figure 6-11 shows two additional boards in an IXIA 250 chassis.
Table 6-1. IXIA 250 Computer Connections
Connector Usage
Keyboard/Mouse Used to connect an external mouse and/or keyboard.
VGA An external monitor may be attached to this connector. The monitor must have at least a 1024 x 768 resolution.
Parallel Port May be used for an external printer.
COM1 May be used to communicate with an external serial device.
10/100 Management A 10/100 Ethernet port used for remote management of the chassis. Three LEDs are provided: Activity, Link and 10/100. Link and 10/100 glow a steady green when link has been established and the port is operating in 100Mbps mode, respectively. The Activity light blinks green as data is sent or received.
Floppy
Hard Disk
CDMA/GPS
InputAntenna
6-6 Ixia Hardware Guide
IXIA 250 ChassisSpecifications
Figure 6-11. IXIA 250 with Additional Load Modules
The IXIA 250 will accept any two single-wide or one double-wide load module. See the remaining chapters of this manual for a discussion of available load mod-ules. When using Ixia software to access the load modules, the cards are num-bered as shown in Figure 6-11. That is, the built-in port is card number 1, the lower card in the chassis is card number 2 and the card above that is card number 3.
When the IXIA 250 is ordered with the Gigabit-only option, then one of two optional connectors may be attached to the Test Port. The connectors are either copper (RJ-45) or fibre optic (LC). The module to which the connector is attached is hot-swappable. Merely press the release button to the left of the con-nector and pull out the connector.
Sync-in/Sync-out connectors are provided to daisy chain the IXIA 250 with other chassis.
When the CDMA or GPS option is installed an appropriate antenna should be attached to the rear panel, as shown in Figure 6-10. Refer to Clocking - IXIA 100 and IxClock Modules for a full discussion of the use of the CDMA/GPS feature. LEDs are provided to indicate the status of the CDMA/GPS time lock; the afore-mentioned chapter has a discussion of their interpretation.
Specifications
Computer System The computer specifications are contained in Table 6-1.
Card #1
Card #2
Card #3
Table 6-2. IXIA 250 Computer Specifications
CPU Intel Celeron 850Mhz
Memory 256 MB
Disk Removable IDE disk: 20 GB
Operating System Windows 2000
Keyboard Integrated keyboard
External keyboard Via external connector: PS/2 6-pin DIN with or without Y-connector
Ixia Hardware Guide 6-7
IXIA 250 ChassisSpecifications6
Test System The test system specifications are contained in Table 6-3 on page 6-8.
General Specification
The general specifications are contained in Table 6-4 on page 6-8.
Mouse Integrated touchpad
External mouse Via external connector: PS/2 6-pin DIN with or without Y-connector
LCD Integrated:• 1024 x 768 resolution• Touchscreen• Adjustable brightness
External monitor Via external connector: HD-DB15 Super VGA
Printer Via external connector: Female DB25 parallel port
Ethernet Built-in with connector: RJ-45 10/100Mbps
Serial Via external connector: 1 male DB9 port
Table 6-2. IXIA 250 Computer Specifications
Table 6-3. IXIA 250 Computer Specifications
Built-in Load Module
1-port of LM1000TXS4 load module with 10/100/1000 capability. Refer to Chapter 10, IXIA 10/100/1000 Load Modules for a description of the port characteristics. Load module must be ordered with a copper or SFP connector. This port is available as card 1, port 1 in Ixia software.
Load Module Slots 2. Any of Ixia’s single-wide or double-wide modules may be used. Load modules are hot-swappable. These cards are available as cards 2 and 3 in Ixia software.
CDMA Optional CDMA clock synchronization module.
Table 6-4. IXIA 250 Chassis Specifications
Physical
Load Module Slots 2
Size 17.5” x 11.25” x 7” (44.5cm x 28.5cm x 17.8cm)
Weight (empty) 20 lb. (9 kg)
Avg. Shipping Wt. 22 lb. (10 kg)
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 50°F to 104°F, (10°C to 40°C)
Storage 50°F to 122°F, (10°C to 50°C)
Humidity
6-8 Ixia Hardware Guide
IXIA 250 ChassisSpecifications
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing
Front Panel Switches LCD brightness slide switch
Back Panel Switches On/Off rocker switch
Momentary power-on
Back Panel Indicators Power, Master, External Clock, CDMA/GPS status
Back Panel Connectors
Power Male receptacle
Mouse & Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100Mbps
Serial Male DB9 ports
Test port RJ-45 or LC
Sync In/Out 2 - RJ45
Table 6-4. IXIA 250 Chassis Specifications
Ixia Hardware Guide 6-9
IXIA 250 ChassisSpecifications6
6-10 Ixia Hardware Guide
7Chapter 7: Optixia Chassis
The Optixia chassis has 10 slots for Ixia Load Modules. Each slot either accom-modates one high-density card or up to two smaller cards on a special carrier. Optixia may also be used to support the high-powered load modules, including all OC192 and 10GB modules. For double-wide load modules such as the OC-192, a double-wide carrier are provided. This allows the Optixia to accommodate all existing load modules.
When using high-powered load modules, it is important to insert the supplied baffle panels in all used slots, maintaining proper air flow over the load modules.
The Optixia uses four redundant power supplies, providing continuous long term operation. It also supports hot-swapping of Load Modules, allowing dynamic re-configuration. The Optixia is shown in Figure 7-1 on page 7-1.
Figure 7-1. Optixia Chassis
Ixia Hardware Guide 7-1
Optixia ChassisSpecifications7
SpecificationsThe chassis specifications are contained in Table 7-1 on page 7-2.Table 7-1. Optixia Chassis Specifications
General Fully integrated PC with 10/100 NIC.
Physical
Load Module Slots 10 (high-density) or 20 with carriers
Size 17.5”w x 35.5”h x 22.5”d (44.5cm x 90.5cm x 57.5cm)
Weight (empty) 150lbs (68kg)
Avg. Shipping Wt. 160lbs (72.5kg)
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 32°F to 104°F, (0°C to 40°C)
Storage 0°F to 110°F, (-20°C to 43°C)
Humidity
Operating 10% to 90%, non-condensing
Storage 5% to 95%, non-condensing
Front Panel Switches On/Off momentary power push button
Back Panel Switches None
Front Panel Indicators SystemSystem ReadySystem FaultSystem TemperatureSystem PowerCPU Power
GPS EnabledTime Stamp 1, 2, 3Satellite Lock
ArmOKLock
SyncMasterExt. Sync.
CDROM
Front Panel Connectors
7-2 Ixia Hardware Guide
Optixia ChassisSpecifications
Power Nema 6-20r receptacle. Two 15A, 220VAC 50/60Hz connections for full redundancyor direct connection to -48VDC.
Mouse PS/2 6-pin DIN
Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100Mbps
Serial 1 - male DB9 ports
USB 2 - USB Master Connector
Sync In, Sync Out RJ-45
GPS Antenna BNC
Trigger In BNC
Table 7-1. Optixia Chassis Specifications
Ixia Hardware Guide 7-3
Optixia ChassisSpecifications7
7-4 Ixia Hardware Guide
8Chapter 8: Clocking - IXIA 100 and IxClock Modules
Ixia 100The IXIA 100 chassis has 1 slot for Ixia Load Modules and includes either an integral GPS unit (IXIA 100 GPS) or CDMA unit (IXIA 100 CDMA). The IXIA 100 is shown in Figure 8-1 on page 8-1.
Figure 8-1. Ixia 100 Chassis
The IXIA 100 with Integrated Global Positioning System (GPS) or Code-Divi-sion Multiple Access (CDMA) technology is designed for distributed end-to-end performance measurements of key metrics, including point-to-point latency and jitter.
IxClockThe IxClock module provides the means for accurate world-wide timing using a number of different reference inputs. It includes an integral GPS unit. The IxClock module is shown in Figure 8-2 on page 8-1.
Figure 8-2. IxClock Module
The IxClock module may be used in conjunction with any of the standard IXIA chassis (100, 400, 1600 and 1600T). The IxClock module and the Ixia 100 chas-
Ixia Hardware Guide 8-1
Clocking - IXIA 100 and IxClock ModulesBackground–Chassis Synchronization8
sis have a number of characteristics in common and are discussed together in the following section.
Background–Chassis SynchronizationMeasurement of unidirectional latency and jitter in the transmission of data from a transmit port to a receive port requires that the relationship between the time at the ports is known. This is not required for measuring roundtrip properties since the same port sends and receives the data. This can be accomplished by providing one of the following signals between chassis:
• Clock (frequency standard): this allows chassis to phase-lock their frequency standards so that a cycle counter on any chassis will count the same number of cycles during the same time interval. Each Ixia port maintains such a counter from a common chassis-wide frequency standard.
• Reset: Phase-locking the frequency standards between chassis allows ports on different chassis to count the same number of cycles during a given time interval. However, this does not allow the transmission delay to be calculated. A means of either discovering the fixed offset between their counters or simultaneously setting the counters to a known value must exist. It is concep-tually easy to think of this as the zero reset.
In widely distributed applications, such as monitoring traffic characteristics over a WAN, these signals cannot be transmitted between chassis over a physical con-nection because of unknown delay characteristics. An alternative means is required to satisfy these requirements.
Ixia has provided facilities that allow for the synchronization of independent Ixia chassis located anywhere in the world by replacing the existing inter-chassis sync cables with a widely available frequency and time standard supplied from an external source. Accurate timing can be used to obtain accurate latency and other measurements in a live global network. When geographically dispersed chassis are connected in this way, the combination is called a ‘virtual chassis chain’.
8-2 Ixia Hardware Guide
Clocking - IXIA 100 and IxClock ModulesBackground–Chassis Synchronization
Worldwide Synchronization
Two or more Ixia 100 chassis and/or IxClock modules may be distributed world-wide forming a virtual chassis chain based on GPS and/or CDMA timing. One possible configuration is shown in Figure 8-3 on page 8-3.
Figure 8-3. Worldwide Deployment of Synchronized Chassis
The ports on all of the chassis may be shared by one or more Ixia software users located likewise anywhere in the world. Where GPS and CDMA sources are used, all of the sources must have good quality time values in order to for the trigger to be transmitted.
Once the timing features of the chassis is configured, operating a worldwide set of Ixia chassis is the same as local operation. The Ixia hardware and software programs the clocks such that they all send a master trigger pulse to all Ixia chas-sis, within a tolerance of ±80 ns with GPS and ±100 us for CDMA.
Ixia chassis timing operates by setting a time-of-day from one source and then maintaining the time accuracy through a potentially different means. Table 8-1 on page 8-3 describes the full set of options available and their approximate rela-tive accuracies.
SO
Ixia 1600
Ixia 100 IxClock
Ixia 400Ixia 1600SI
SOSI
SOSI
Ixia 100
NYC Paris Tokyo
Miami San Jose
IxExplorer ScriptMate
Chicago
TCL
Table 8-1. Summary of Timing Options
Available on Devices
Timing Option Time of Day Accuracy
Frequency Source
Frequency Accuracy
Ixia 100, 400, 1600 Synchronous N/A Internal PC clock 1 microsecond / second
Ixia 100, 400, 1600 CDMA 100 microseconds from GMT
CDMA Stratum 1
Ixia 100, IxClock GPS (with attached antenna)
150 nanoseconds from GMT
GPS Stratum 1
IxClock GPS (with T1/E1 or 1PPS input)
150 nanoseconds T1/E1 or 1PPS Dependent on the accuracy of the selected frequency source
IxClock GPS (with no fixed input)
150 nanoseconds, degrading to 1 ms over 1-3 months
Internal rubidium oscillator
1 nanosecond / second
Ixia Hardware Guide 8-3
Clocking - IXIA 100 and IxClock ModulesBackground–Chassis Synchronization8
The specifications of the GPS unit are detailed in Appendix A, Time and Frequency Module.
Three scenarios are discussed below:
• Independent Operation – each Ixia 400, 1600 or Optixia chassis chain gener-ates its own timing.
• Ixia 100 – a one-slot chassis which includes a GPS receiver.
• IxClock – a separate module which generates a timing signal from multiple sources.
Independent Operation
Independent Ixia 400, 1600 or Optixia chassis may synchronize themselves with other chassis as shown in Figure 8-4 on page 8-4.The timing choices are explained in Table 8-2 on page 8-4.
Figure 8-4. Independent Chassis Timing
Ixia 100 If the two chassis are separated by any significant distance, a sync-out/sync-in cable cannot be used to connect them. In this case, two Ixia 100 chassis with built-in Global Positioning Satellite (GPS) or Code Division Multiple Access (CDMA) are attached to each chassis through sync-out/sync-in cables, as shown in Figure 8-5 on page 8-5. The Ixia 100s maintains an accuracy of less than 150 nanoseconds when attached to a GPS antenna or 100 microseconds when attached to a CDMA receiver and provide chassis to chassis synchronization.
Other Time Source
Internal Sync
SO SI
Ixia 1600 Ixia 400
Table 8-2. Independent Chassis Timing Choices
Choice Usage
Internal Sync (Synchronous)
If a chassis is used in a stand-alone manner or the master of a chassis chain, it may generate its own start signal. In general, there is insufficient timing accuracy between timing masters for measurements over any distance. This is also known as synchronous timing.
Sync-In (SI) If a chassis is a slave, either directly connected to the master chassis or further down the chain, it will derive its timing from the previous chassis’ Sync-Out (SO) signal.
CDMA The CDMA cellular network transmits an accurate time signal.
Other Time Source (PC Clock)
An inaccurate method which may be used for initial configuration. One of the other modes should be used for actual testing.
8-4 Ixia Hardware Guide
Clocking - IXIA 100 and IxClock ModulesBackground–Chassis Synchronization
Figure 8-5. Chassis Timing Using an Ixia 100
The Ixia 100 chassis contains one slot for an Ixia card module. The additional timing features available with the Ixia 100 are shown in Table 8-3 on page 8-5.
The Sync-Out from the Ixia 100 is used to master a chassis chain at a specific geographic location. Since the Ixia 100 chassis has all other functions provided by the other Ixia chassis, it may also use independent timing when not used to synchronize with other chassis at other locations.
IxClock The final choice involves the use of an IxClock chassis. This is shown in Figure 8-6 on page 8-6.
Table 8-3. Ixia 100 Chassis Timing Choices
Choice Usage
GPS The Ixia 100 requires connection to an external GPS antenna in order to ‘capture’ multiple GPS satellites. It will maintain an accuracy of less than 150 nano-seconds
CDMA The CDMA cellular network transmits an accurate time signal. CDMA (Code Division Multiple Access) cellular base-stations effectively act as GPS repeaters. The Ixia 100-CDMA has a built-in CDMA receiver with a small antenna on the back on the chassis that receives the CDMA signals passively (you do not need to subscribe to any service) and decodes the embedded GPS signal. Using this approach, the Ixia 100 can be time-synched to GPS - with NO EXTERNAL ANTENNA ON THE ROOF.
Ixia Hardware Guide 8-5
Clocking - IXIA 100 and IxClock ModulesIxClock Components and Procedures8
Figure 8-6. IxClock Chassis Timing Choices
The IxClock module is a separate rack-mountable chassis for use in isolated envi-ronments where GPS or CDMA antenna placement is not possible. The IxClock includes provisions for multiple reference sources. At the heart of the IxClock chassis is a GPS unit. This GPS unit, with its battery pack, may be taken outside and attached to an included antenna in order to obtain an accurate time lock. Once a time value is obtained, the IxClock unit may be brought inside where it will maintain a better than 1 millisecond accuracy for up to 1-3 months depend-ing on the IxClock version used. The clock accuracy is maintained by a 1 rubid-ium oscillator. The IxClock may, of course, be permanently connected to the antenna to maintain a 150 nanosecond accuracy. The functions of the IxClock module are controlled via a serial link from the chassis chain master. The full set of timing choices available are shown in Table 8-4 on page 8-6.
IxClock Components and ProceduresThe complete set of components of the IxClock module are shown in Figure 8-7 on page 8-7. The use of each of these components is described in the following sections.
Table 8-4. IxClock Chassis Timing Choices
Choice Usage
Standalone Timing is provided autonomously by the IxClock unit by virtue of a permanently connected GPS or a temporary GPS connection maintained by a rubidium oscillator.
E1/T1 Time of day is set by the GPS unit and the time base is maintained by a E1/T1 signal connected to an IxClock connector.
1PPS Time of day is set by the GPS unit and the time is maintained by a 1 pulse per second signal connected to the IxClock front serial I/O connector.
8-6 Ixia Hardware Guide
Clocking - IXIA 100 and IxClock ModulesIxClock Components and Procedures
Figure 8-7. IxClock Components
IxClock Connectors The front and rear connectors on the IxClock module are shown in Figure 8-8 on page 8-7.
Figure 8-8. IxClock Front and Rear Connectors
The use of connectors is described in Table 8-5 on page 8-7.
Carrying CaseGPS Antenna
Rack Mount
Rack Mount Adapter
IxClockBattery Cable
Battery Charger
Battery
on/off switch control
GPS antennaE1/T1
sync out
48VDC powersync outAC power
48VDC power controlsync out
FRONT
REAR
input
select switch
Table 8-5. IxClock Front and Rear Connector Usage
Connector Usage
on / off switch Controls AC power to the unit. This should be left on before attaching the rack mount adapter.
AC power Receives AC power from 90VAC to 220VAC, 50Hz or 60Hz power.
48VDC power Receives 48v (battery) or -48v (Telco standard) DC power.
control Provides an interface to the IXIA 400, 1600 or Optixia chassis it is supporting.The supported chassis controls the IxClock configuration and operation via the RS-232 control interface. The front connector is used in preference to the rear connector if they are both connected.
Ixia Hardware Guide 8-7
Clocking - IXIA 100 and IxClock ModulesIxClock Components and Procedures8
Rack Mounting If the IxClock module is to be rack mounted, then the rack mount adapter must be attached to the back of IxClock as shown in Figure 8-9 on page 8-8. Four con-nectors from the rack mount adapter must be attached to the back of the IxClock chassis; each connector’s mate is clear and unambiguous. If AC power is to be used, the on/off switch should be left on. Also, the position of the slide switch should be determined at this time based on rack installation and expected usage; refer to Table 8-5 on page 8-7.
Figure 8-9. Connecting the IxClock Chassis to the Rack Mount Adapter
The rack mount adapter is then attached to the IxClock chassis by tightening six screws, as shown in Figure 8-10 on page 8-8.
Figure 8-10. Attaching the IxClock Chassis to the Rack Mount Adapter
GPS antenna Connects to the GPS antenna.
E1/T1 Connects to a BITS or other device which provides E1 or T1 timing.
sync out The sync out connects to an Ixia chassis as the master in a timing chain. The output goes to the front or rear connector based on the position of the slide switch.
slide switch If the slide switch is in the up position, the sync out in the rear of the chassis is enabled. If the slide switch is in the down position, the sync out in the front of the chassis is enabled.
Table 8-5. IxClock Front and Rear Connector Usage
Connector Usage
Rack Mount
IxClock ChassisAdapter
TightenScrews
8-8 Ixia Hardware Guide
Clocking - IXIA 100 and IxClock ModulesIxClock Components and Procedures
The IxClock, with the rack mount adapter is then slid into the rack mount (which is presumed to be mounted in a rack) as shown in Figure 8-11 on page 8-9.
Figure 8-11. Placing the IxClock in the Rack Mount
The rear of the rack mount is shown in Figure 8-12 on page 8-9.
Figure 8-12. Rack Mount Rear Connector
Making the IxClock Chassis Portable
When it is not possible to connect the GPS antenna to the IxClock permanently, the IxClock may be placed in its carrying case and taken outside in order to obtain a GPS time lock. The unit may be operated up to 2 hours from a fully charged battery. The location of the battery, battery charger and carrying case is shown in Figure 8-13 on page 8-9.
Figure 8-13. Battery, Battery Charger and GPS Antenna Location in IxClock Carrying Case
Rack Mount
IxClock Chassis
AdapterRack Mount
120VAC Power -48VDC Power Control Sync Out
GPS Antenna Battery
Battery Charger
Ixia Hardware Guide 8-9
Clocking - IXIA 100 and IxClock ModulesIxClock Components and Procedures8
The supplied GPS antenna should be mounted in the left, front pocket of the case and the battery should go in the middle compartment. When the battery charger is in use, the charger should be plugged into a wall socket and the longer cable con-nected to the top of the battery unit. The battery’s rotary switch should be set to the Charge position. A battery will reach full charge within 8 hours.
In order to prepare the unit for portable use, the power extension battery cable should be connected to the battery as shown in Figure 8-14 on page 8-10.
Figure 8-14. Battery Cable Connection
The battery cable should be connected to the battery with the case itself; there is a cutout between the left and center compartments to accommodate the cable con-nector. Both the battery cable and the GPS antenna cable should be threaded to the rear compartment through a grommet located at the bottom of the left pocket of the case, as shown from the rear in Figure 8-15 on page 8-10.
Figure 8-15. Threading Cables From Front to Rear of Case
The battery and antenna cables are then attached to the front of the IxClock unit as shown in Figure 8-16 on page 8-11. Note that if the rack mount adapter has been attached to the IxClock chassis, it need not be removed in order to place it in the case.
Battery Cable
Grommet
Battery andGPS cables
8-10 Ixia Hardware Guide
Clocking - IXIA 100 and IxClock ModulesIxClock Components and Procedures
Figure 8-16. Front Connections for IxClock in Portable Case
All zippers and velcro straps may now be closed. For best results, the case should be taken to a place that has a clear view of the sky. The battery should be set to the Discharge position and kept in that position until it is connected to a perma-nent power source. When the battery is set to discharge, the Lock and Pwr lights will be lit while the unit performs a self-test. The Lock light will then extinguish until a GPS lock has occurred at which point, it will blink at a 1/2 hz rate. The first time a lock is obtained, it may require up to 30 minutes. Subsequent locks may be obtained within 15 minutes, if the unit has been moved less than 1/4 mile. The time to obtain a lock can be reduced by choosing a location with an unob-structed view of the sky.
The unit should then be moved to its permanent position and AC or DC power applied to one of the rear connectors, either on the IxClock unit itself or to the rack-mount, if appropriate. The GPS antenna may be detached at any point in this process, but the front 48VDC connector should not be removed until a rear power source is attached.
Ixia Chassis Connections
To complete the connections, the Sync Out port on the front or rear (depending on the slide switch - see Table 8-5 on page 8-7) and a 9-pin RS-232 cable from the front or rear to the first Ixia chassis which will hold load modules. A null-modem cable is required. The rear control connector is normally used for rack-mount applications. The front connector may be used instead or in addition to supply the 1PPS input. The pin-out for the front control connector is shown in Table 8-6 on page 8-11.
Battery Cable GPS Antenna
Table 8-6. IxClock Front Control Connector Pin-Out
Pin Usage
1 Do not connect to this pin.
2 Receive Data In (if pins 4 and 5 are shorted)
3 Transmit Data Out (if pins 4 and 5 are shorted)
4 12VDC GND. Short this pin to pin 5 if the RS-232 signals are to be used from the front connector.
5 RX / TX GND. Short this pin to pin 4 if the RS-232 signals are to be used from the front connector.
6 Do not connect to this pin.
7 Do not connect to this pin.
Ixia Hardware Guide 8-11
Clocking - IXIA 100 and IxClock ModulesIXIA 100 Specifications8
Thus, if the front control connector is to be used for connection to an Ixia chassis, a null modem cable which shorts pins 4 and 5 should be used. A 1PPS timing source may be connected through the use of pins 8 and 9 on the connector.
A number of LEDs are available on the IXIA 100’s front panel, as described in Table 8-7 on page 8-12.
IXIA 100 SpecificationsThe IXIA 100 chassis specifications are contained in Table 8-8 on page 8-12.
8 +1PPS Signal
9 -1PPS Signal
Table 8-7. IXIA 100 Front Panel LEDs
LED Usage
Set Lock Three LED’s indicate three separate status events:• 1 – indicates that the GPS is tracking satellites.• 2 – indicates that the antenna is correctly connected.• 3 – indicates that the chassis is armed for a GPS sync event.
Time Stamp The number of LEDs lit indicates the time quality available from the GPS unit. Three LEDs lit indicates best quality.
Shutdown The chassis is in the process of being shut down.
Power Power is applied to the chassis.
Table 8-6. IxClock Front Control Connector Pin-Out
Pin Usage
Table 8-8. Ixia 100 Chassis Specifications
General Fully integrated PC with 10/100 NIC.
Physical
Load Module Slots 1
Size 17.5”w x 1.75”h x 20.15”d (44.5cm x 4.5cm x 38.1cm)
Weight 14lbs (6.4kg)
Avg. Shipping Wt. 16lbs (7.3kg)
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 32°F to 104°F, (0°C to 40°C)
Storage 32°F to 122°F, (0°C to 50°C)
Humidity
8-12 Ixia Hardware Guide
Clocking - IXIA 100 and IxClock ModulesIxClock Specifications
IxClock SpecificationsThe module specifications are contained in Table 8-9 on page 8-13.
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing
Front Panel Switches On/Off momentary power push button
Back Panel Switches On/Off rocker switch–48 VDC version only
Front Panel Indicators Power, Satellite Lock, Time Stamp
Front Panel Connectors
Mouse & Keyboard PS/2 6-pin DIN
Monitor HD-DB15 Super VGA
Printer Female DB25 parallel port
Ethernet RJ-45 10/100Mbps
Com1 Port 2 male DB9 ports
Back Panel Connectors
Power IEC320 AC inlet
Table 8-8. Ixia 100 Chassis Specifications
Table 8-9. IxClock Specifications
General Rack-mounted
Physical
Size 13”w x 1.65”h x 12”d (33cm x 4.2cm x 30.5cm)
Weight (empty) 5lbs (2.2kg)
Avg. Shipping Wt. 12lbs (5.3kg)
Environmental
Temperature
Operating 50°F to 104°F, (10°C to 40°C)
Storage 50°F to 122°F, (10°C to 50°C)
Humidity
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing
Front Panel Switches Reset.
Back Panel Switches On/Off AC power rocker switch
Ixia Hardware Guide 8-13
Clocking - IXIA 100 and IxClock ModulesIxClock Specifications8
Slide switch to control sync out front/rear usage
Front Panel Indicators Lock, Power
Front Panel Connectors
Power 48V/-48V DC Battery/Telco Power In
Sync out RJ14
GPS antenna BNC
E1/T1 RJ-45 E1 / T1 timing
Com1 Port 1 female DB9
Back Panel Connectors
Power 48V/-48V DC Battery/Telco Power In
Power 90-220V AC Power In
Sync out RJ14
Com1 Port 1 female DB9
Table 8-9. IxClock Specifications
8-14 Ixia Hardware Guide
9Chapter 9: IXIA 10/100 Load Modules
The 10/100 family of load modules implements Ethernet interfaces that may run at 10Mbps or 100Mbps. Different numbers of ports and interfaces are available for the different board types. The features available for these load modules are included in three tables starting with Table 1-5 on page 1-11.
One of the family’s modules (the LM100TXS8) is shown in Figure 9-1 on page 9-1. The face plate for the same module (populated with 4 ports) is shown in Figure 9-2 on page 9-1.
Figure 9-1. LM100TXS8 Load Module
Figure 9-2. LM100TXS8 Face Plate (with 4 ports)
Ixia Hardware Guide 9-1
IXIA 10/100 Load ModulesSpecifications9
SpecificationsThe load module specifications are contained in Table 9-1 on page 9-2. Note that the -3 modules are not included in the table; their limitations versus the non-3 version are discussed in Ixia Load Modules on page 1-3.
Table 9-1. 10/100 Load Module Specifications
LM100TXS8 LM100TXLM100TX2
LM100MII LM100RMII
# ports 8 4 (LM100TX)2 (LM100TX2)
2 4
-3 Card Available? N Y N N
Data Rate 10 / 100 Mbps 10 / 100 Mbps 10 / 100 Mbps 10 / 100 Mbps
Connector RJ-45 RJ-45 MII1 RMII2
Capture buffer size 6MB 2MB 2MB 2MB
Captured packet size 12-13k bytes 12-64k bytes 12-64k bytes 12-64k bytes
Streams per port 255 255 255 255
Flows per port 15872 15872 15872
Advanced Streams 128
Preamble size: min-max
2-255 bytes 2-255 bytes 2-255 bytes 2-255 bytes
Frame size: min-max 12-64k bytes 12-64k bytes 12-64k bytes 12-64k bytes
Inter-frame gap: min-max
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
Inter-burst gap: min-max
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
Inter-stream gap:min-max
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
10Mbps: 800ns-17sec in 400ns steps100Mbps: 80ns-170sec in 40ns steps
Latency 40ns resolution 40ns resolution 40ns resolution 40ns resolution1. AMPLIMITE Subminiature D connector 787170-4.2. AMPLIMITE Subminiature D connector 787170-7.
9-2 Ixia Hardware Guide
IXIA 10/100 Load ModulesPort LEDs
Port LEDsEach LM100TXS8 port incorporates a set of 2 LEDs, as described in Table 9-3 on page 9-3.
All other 10/100 ports incorporate a set of 6 LEDs, as described in Table 9-3 on page 9-3.
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 9-4 on page 9-3.
Table 9-2. LM100TXS8 Port LEDs
LED Color Usage
Upper Orange Collision
Green Transmitting
Yellow Link
Lower Orange Receive error
Green Receiving
Yellow 100 Mb/sec speed
Table 9-3. 10/100 Port LEDs
LED Label Usage
Link Green if link established. For Mii and RMii boards, Red if no transceiver is detected.
10/100 Mbps Green for 100Mbps.
Half Green for half duplex operation.
Tx/Col Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors received.
Trig Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Table 9-4. 10/100 Trigger Out Signals
Pin Signal
1 Port 1 – 40 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2 – 40 ns high pulse for each packet matching User Defined Statistic 1
3 Port 3 – 40 ns high pulse for each packet matching User Defined Statistic 1
4 Port 4 – 40 ns high pulse for each packet matching User Defined Statistic 1
Ixia Hardware Guide 9-3
IXIA 10/100 Load ModulesStatistics9
StatisticsStatistics for 10/100 cards, for various modes of operation may be found in Table E-8 on page E-28.
9-4 Ixia Hardware Guide
10Chapter 10: IXIA 10/100/1000 Load Modules
The 10/100/1000 family of load modules implements Ethernet interfaces that run at 10Mbps, 100Mbps or Gigabit (1000 Mbps) speeds. Different numbers of ports and interfaces are available for the different board types. The features available for these load modules are included in three tables starting with Table 1-5 on page 1-11.
One of the modules in this family, the LM1000TXS4, is shown in Figure 10-1 on page 10-1.
Figure 10-1. LM1000TXS Load Module
Ixia Hardware Guide 10-1
IXIA 10/100/1000 Load ModulesSpecifications10
SpecificationsThe load module specifications are contained in Table 10-2 on page 10-3. Note that the -3 modules are not included in the table; their limitations versus the non-3 version are discussed in Ixia Load Modules on page 1-3.Table 10-1. 10/100/1000 Load Module Specifications
LM1000T-5 LM1000TXS4
# ports 2 4
-3 Card Available N N
Data Rate 10 / 100 / 1000 Mbps 10 / 100 / 1000 Mbps
Connector RJ-45 RJ-45
Capture buffer size 4MB 8MB
Captured packet size 32000 32 -16k
Streams per port 255 255
Advanced scheduler streams per port
128
Flows per port 15872
Preamble size: min-max
2-255 bytes 12-124 bytes (10/100)24-124 bytes (1000)
Frame size: min-max 40-13k bytes 12-13k bytes (10/100)24-13k bytes (1000)
Inter-frame gap: min-max
64ns-60sec in 16ns steps
Basic scheduler:10: 160ns-43sec in 40ns steps100: 16ns-4.3sec in 4ns steps1000: 1.6ns-0.43sec in 1.6ns stepsAdvanced scheduler:10: 640ns-327,670nsec in 40ns steps100: 64ns-32,767nsec in 4ns steps1000: 6.4ns-3,276.6sec in 1.6ns steps
10-2 Ixia Hardware Guide
IXIA 10/100/1000 Load ModulesPort LEDs
Port LEDsEach LM1000T-5 port incorporates a set of 8 LEDs, as described in Table 10-2 on page 10-3.
Inter-burst gap: min-max
64ns-60sec in 16ns steps
Basic scheduler:10: 160ns-43sec in 40ns steps100: 16ns-4.3sec in 4ns steps1000: 1.6ns-0.43sec in 1.6ns stepsAdvanced scheduler:10: 640ns-327,670nsec in 40ns steps100: 64ns-32,767nsec in 4ns steps1000: 6.4ns-3,276.6sec in 1.6ns steps
Inter-stream gap:min-max
64ns-60sec in 16ns steps
Basic scheduler:10: 160ns-43sec in 40ns steps100: 16ns-4.3sec in 4ns steps1000: 1.6ns-0.43sec in 1.6ns stepsAdvanced scheduler:10: 640ns-327,670nsec in 40ns steps100: 64ns-32,767nsec in 4ns steps1000: 6.4ns-3,276.6sec in 1.6ns steps
Latency 20ns resolution 40ns resolution
Table 10-1. 10/100/1000 Load Module Specifications
LM1000T-5 LM1000TXS4
Table 10-2. 10/100/1000 Port LEDs
LED Label Usage
Mstr Green if the port is the master in a Gigabit connection.
Half Green for half duplex operation.
1000 Green if the port is configured for Gigabit operation.
100 Green if the port is configured for 100Mbps operation.
10 Green if the port is configured for 10Mbps operation.
Tx/Col Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors received.
Trigger Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Ixia Hardware Guide 10-3
IXIA 10/100/1000 Load ModulesTrigger Out Values10
Each LM1000TXS4 port incorporates a set of 6 LEDs, as described in Table 10-3 on page 10-4.
Trigger Out ValuesThe signals available on the trigger out pins for the LM1000T5 card is described in Table 10-4 on page 10-4.
The LM1000TXS4 sends a 660ns negative pulse when user defined statistic 1 is true.
StatisticsStatistics for 10/100/1000 cards, under various modes of operation may be found in Table E-8 on page E-28, Table E-9 on page E-30 and Table E-12 on page E-40.
Table 10-3. 10/100/1000 Port LEDs
LED Label Usage
Slave Green for slave mode in a Gigabit connection.
Half Green for half duplex operation.
Link Green for 1000 Mbps link, alternating green and orange for 100 Mbps link, orange for 10 Mbps link and off for no link.
Tx/Col Green during data transmission and red during collisions.
Rx/Err Green during error free reception and red if errors are received.
Trigger Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Table 10-4. 10/100/1000 Trigger Out Signals
Pin Signal
1 Port 1 – 10 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2 – 10 ns high pulse for each packet matching User Defined Statistic 1
3 Port 1 – low during transmit of frame, otherwise high
4 Port 2 – low during transmit of frame, otherwise high
10-4 Ixia Hardware Guide
11Chapter 11: IXIA 100 Load Modules
The 100 family of load modules implements Ethernet interfaces that may run at 100Mbps. Different numbers of ports and interfaces are available for the differ-ent board types. The features available for these load modules are included in three tables starting with Table 1-5 on page 1-11.
One of the modules in this family (the LM100FX) is shown in Figure 11-1 on page 11-1. The face plate for the same module is shown in Figure 11-2 on page 11-1.
Figure 11-1. LM100FX Load Module
Figure 11-2. LM100FX Face Plate
Ixia Hardware Guide 11-1
IXIA 100 Load ModulesSpecifications11
SpecificationsThe load module specifications are contained in Table 11-2 on page 11-2. Note that the -3 modules are not included in the table; their limitations versus the non-3 version are discussed in Ixia Load Modules on page 1-3.
Port LEDsEach 100 port incorporates a set of 6 LEDs, as described in Table 11-2 on page 11-2.
Table 11-1. 100 Load Module Specifications
LM100FX LM100FXSM
# ports 4 4
-3 Card Available N N
Data Rate 100 Mbps 100 Mbps
Connector MT-RJ (Multimode) MT-RJ (Singlemode)
Capture buffer size 2MB 2MB
Captured packet size 12-64k bytes 12-64k bytes
Streams per port 255 255
Flows per port 15872 15872
Preamble size: min-max 2-255 bytes 2-255 bytes
Frame size: min-max 12-64k bytes 12-64k bytes
Inter-frame gap: min-max
80ns-170sec in 40ns steps
80ns-170sec in 40ns steps
Inter-burst gap: min-max 80ns-170sec in 40ns steps
80ns-170sec in 40ns steps
Inter-stream gap:min-max
80ns-170sec in 40ns steps
80ns-170sec in 40ns steps
Latency 40ns resolution 40ns resolution
Table 11-2. 100 Port LEDs
LED Label Usage
Link Green if link established. For Mii and RMii boards, Red if no transceiver is detected.
100 Mbps Green for 100Mbps.
Half Green for half duplex operation.
Tx/Col Green during data transmission. Red during collisions.
11-2 Ixia Hardware Guide
IXIA 100 Load ModulesTrigger Out Values
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 11-3 on page 11-3.
StatisticsStatistics for 100Mbps cards, under various modes of operation may be found in Table E-8 on page E-28.
Rx/Err Green during error free reception. Red if errors received.
Trig Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Table 11-2. 100 Port LEDs
LED Label Usage
Table 11-3. 100 Trigger Out Signals
Pin Signal
1 Port 1 – 40 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2 – 40 ns high pulse for each packet matching User Defined Statistic 1
3 Port 3 – 40 ns high pulse for each packet matching User Defined Statistic 1
4 Port 4 – 40 ns high pulse for each packet matching User Defined Statistic 1
Ixia Hardware Guide 11-3
IXIA 100 Load ModulesStatistics11
11-4 Ixia Hardware Guide
12Chapter 12: IXIA Gigabit Load Modules
The Gigabit family of load modules implements copper and fiber Ethernet inter-faces that may run at 1000Mbps. Different numbers of ports and interfaces are available for the different board types. The features available for these modules are included in three tables starting with Table 1-5 on page 1-11.
One of the modules in this family, the LM1000SX, is shown in Figure 12-1 on page 12-1. The face plate for the same module is shown in Figure 12-2 on page 12-1.
Figure 12-1. LM1000SX Load Module
Figure 12-2. LM1000SX Face Plate
Ixia Hardware Guide 12-1
IXIA Gigabit Load ModulesSpecifications12
SpecificationsThe load module specifications are contained in Table 12-2 on page 12-3. Note that the -3 modules are not included in the table; their limitations versus the non-3 version are discussed in Ixia Load Modules on page 1-3. A special capability of Gigabit modules is the ability to echo all received packets back out to the net-work. This feature should never be used in a live network, as it will likely crash the network.
Table 12-1. Gigabit Load Module Specifications
LM1000SX
LM1000LX LM1000GBICLM1000GBIC-P1
LM1000SFPS4
# ports 2 2 1 (LM1000GBIC-P1)2 (LM1000 GBIC)
4
-3 Card Available Y Y N N
Data Rate 1000 Mbps 1000 Mbps 1000 Mbps 1000 Mbps
Connector SC Multimode
SC Multimode
GBIC Multimode and/or Singlemode
LC or MT-RJ (SFP)
Capture buffer size 4MB 4MB 4MB 8MB
Captured packet size 12-64k bytes
12-64k bytes
12-64k bytes 32 -16k
Streams per port 255 255 255 255
Flows per port 15872 15872 15872 128
Preamble size: min-max 6-255 bytes
6-255 bytes
6-255 bytes
Frame size: min-max 40-64k bytes
40-64k bytes
40-64k bytes 24-124 bytes (10/100)
Inter-frame gap: min-max
64ns-60sec in 16ns steps
64ns-60sec in 16ns steps
64ns-60sec in 16ns steps
Basic scheduler:10: 160ns-43sec in 40ns steps100: 16ns-4.3sec in 4ns steps1000: 1.6ns-0.43sec in 1.6ns stepsAdvanced scheduler:10: 640ns-327,670nsec in 40ns steps100: 64ns-32,767nsec in 4ns steps1000: 6.4ns-3,276.6sec in 1.6ns steps
12-2 Ixia Hardware Guide
IXIA Gigabit Load ModulesPort LEDs
Port LEDsEach Gigabit port incorporates a set of 8 LEDs, as described in Table 12-2 on page 12-3.
Inter-burst gap: min-max
64ns-60sec in 16ns steps
64ns-60sec in 16ns steps
64ns-60sec in 16ns steps
Basic scheduler:10: 160ns-43sec in 40ns steps100: 16ns-4.3sec in 4ns steps1000: 1.6ns-0.43sec in 1.6ns stepsAdvanced scheduler:10: 640ns-327,670nsec in 40ns steps100: 64ns-32,767nsec in 4ns steps1000: 6.4ns-3,276.6sec in 1.6ns steps
Inter-stream gap:min-max
64ns-60sec in 16ns steps
64ns-60sec in 16ns steps
64ns-60sec in 16ns steps
Basic scheduler:10: 160ns-43sec in 40ns steps100: 16ns-4.3sec in 4ns steps1000: 1.6ns-0.43sec in 1.6ns stepsAdvanced scheduler:10: 640ns-327,670nsec in 40ns steps100: 64ns-32,767nsec in 4ns steps1000: 6.4ns-3,276.6sec in 1.6ns steps
Latency 40ns resolution
40ns resolution
40ns resolution 96ns-60sec in 16ns steps
Table 12-1. Gigabit Load Module Specifications
LM1000SX
LM1000LX LM1000GBICLM1000GBIC-P1
LM1000SFPS4
Table 12-2. Gigabit Port LEDs
LED Label Usage
Link Green if link established.
Line Green if an alignment, disparity, or symbol error has been detected. (Not available on the LM1000SFPS4).
Half Green for half duplex operation. (Not available on the LM1000SFPS4).
Tx/Col Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors received.
Trig Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Ixia Hardware Guide 12-3
IXIA Gigabit Load ModulesTrigger Out Values12
Trigger Out ValuesThe signals on the trigger out pins for cards in this category are described in Table 12-3 on page 12-4.
StatisticsStatistics for Gigabit cards, under various modes of operation may be found in Table E-12 on page E-40 and Table E-9 on page E-30.
Table 12-3. Gigabit Trigger Out Signals
Pin Signal
1 Port 1 – 10 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2 – 10 ns high pulse for each packet matching User Defined Statistic 1
3 Port 1 – low during transmit of frame, otherwise high
4 Port 2 – low during transmit of frame, otherwise high
12-4 Ixia Hardware Guide
13Chapter 13: IXIA Ethernet/USB Load Modules
The Ethernet/USB load module implements USB and Ethernet interfaces that may run at USB speeds (12Mbps) or 10Mbps. The features available for this load modules is shown in three tables starting with Table 1-5 on page 1-11.
The LMUSB2 is shown in Figure 13-1 on page 13-1. The face plate for the same module is shown in Figure 13-2 on page 13-1.
Figure 13-1. LMUSB2 Load Module
Figure 13-2. LMUSB2 Face Plate
Ixia Hardware Guide 13-1
IXIA Ethernet/USB Load ModulesSpecifications13
SpecificationsThe load module specifications are contained in Table 13-2 on page 13-2. Note that the -3 modules are not included in the table; their limitations versus the non-3 version are discussed in Ixia Load Modules on page 1-3.
Port LEDsEach USB port incorporates a set of 4 or 6 LEDs, as described in Table 13-2 on page 13-2 and Table 13-3 on page 13-3.
Table 13-1. USB Load Module Specifications
LMUSB2 - USB Mode LMUSB2 - Ethernet Mode
# ports 4 4
-3 Card Available N N
Data Rate USB (12Mbps) USB (12Mbps) or Ethernet (10Mbps)
Connector USB Type A USB Type A + RJ-45 (Ethernet)
Capture buffer size 2 MB 2 MB
Captured packet size 12-8k bytes 12-8k bytes
Streams per port 255 255
Flows per port 15872 15872
Preamble size: min-max 2-255 bytes 2-255 bytes
Frame size: min-max 60-1514 bytes 12-64k bytes
Inter-frame gap: min-max
1 - 15792 packets per second
80ns-180sec in 40ns steps
Inter-burst gap: min-max N/A 80ns-180sec in 40ns steps
Inter-stream gap:min-max
N/A 80ns-180sec in 40ns steps
Latency 40ns resolution 40ns resolution
Table 13-2. USB Port LEDs – USB Mode
LED Label
Usage
USB Green when port is in USB mode, off otherwise.
Tx/Col Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors received.
Link Green if link established, off otherwise.
13-2 Ixia Hardware Guide
IXIA Ethernet/USB Load ModulesTrigger Out Values
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 13-4 on page 13-3.
StatisticsStatistics for USB cards, under various modes of operation may be found in Table E-8 on page E-28 and Table E-11 on page E-36.
Table 13-3. USB Port LEDs – Ethernet Mode
LED Label Usage
Link Green if link established.
10/100 Green for 100Mbps.
Full Green for full duplex operation.
Trig Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Tx/Col Green during data transmission. Red during collisions.
Rx/Err Green during error free reception. Red if errors received.
Table 13-4. USB Trigger Out Signals
Pin Signal
1 Port 1 – 40 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2 – 40 ns high pulse for each packet matching User Defined Statistic 1
3 Port 3 – 40 ns high pulse for each packet matching User Defined Statistic 1
4 Port 4 – 40 ns high pulse for each packet matching User Defined Statistic 1
Ixia Hardware Guide 13-3
IXIA Ethernet/USB Load ModulesStatistics13
13-4 Ixia Hardware Guide
14Chapter 14: IXIA OC12c/OC3c Load Modules
The OC21c/OC3c family of load modules implements Optical Carrier interfaces that may run at OC12 or OC3 speeds. Both interfaces operate in concatenated mode, as opposed to channelized mode. Different numbers of ports and interfaces are available for the different board types. The features available for these load modules are included in three tables starting with Table 1-5 on page 1-11.
One of the modules in this family, the LMOC12c, is shown in Figure 14-1 on page 14-1. The face plate for the same module is shown in Figure 14-2 on page 14-1.
Figure 14-1. LMOC12c Load Module
Figure 14-2. LMOC12c Face Plate
Ixia Hardware Guide 14-1
IXIA OC12c/OC3c Load ModulesSpecifications14
SpecificationsThe load module specifications are contained in Table 14-4 on page 14-3.
1. Captured Packet Size Note: at 100% line rate. Smaller values are possible at lower line rates.
2. Requires that packets be larger than 70 bytes when operating at full line rate.
3. Correct data rates can only be maintained with a minimum number of packet, depending on packet size. For OC12 operation, the numbers of packets are required for the indicated ranges of packet sizes:
Table 14-1. OC12c/OC3c Load Module Specifications
LMOC12c / LMOC12cSM
# ports 2
-3 Card Available N
Data Rate 1-100% of OC12/OC3 speeds (See note 3)
Connector SC-Singlemode or Multimode
Capture buffer size 16MB
Captured packet size 49 - 15K bytes (See note 1)
Streams per port 255
Flows per port N/A
Preamble size: min-max N/A
Frame size: min-max 34-64K bytes
Inter-frame gap: min-max N/A
Inter-burst gap: min-max 1µs - 85secs
Inter-stream gap: min-max 1µs - 85secs
Latency 20ns resolution (See note 2)
Table 14-2. OC12 Minimum Number of Packets
Packet Size Minimum Number of Packets per Stream
45 or less 30
46 - 47 8
48 - 54 7
55 - 63 6
64 - 84 5
85 - 129 4
130 - 199 3
14-2 Ixia Hardware Guide
IXIA OC12c/OC3c Load ModulesPort LEDs
For OC3 operation, the numbers of packets are required for the indicated ranges of packet sizes:
Port LEDsEach OC12c/OC3c port incorporates a set of 4 or 6 LEDs, as described in Table 14-4 on page 14-3.
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 14-5 on page 14-3.
200 - 499 2
500+ 0
Table 14-3. OC3 Minimum Number of Packets
Packet Size Minimum Number of Packets per Stream
34 or less 4
35 - 64 3
65 - 274 2
275+ 0
Table 14-2. OC12 Minimum Number of Packets
Packet Size Minimum Number of Packets per Stream
Table 14-4. LMOC12c Port LEDs
LED Label Usage
LOS Red during Loss of Signal.
LOF Red during Loss of Frame
Error Red on any POS error.
Tx Green while data is transmitted.
Rx Green while data is received.
Trig Follows the state of the Trigger Out pin.
Table 14-5. OC12c/OC3c Trigger Out Signals
Pin Signal
1 Port 1 – 10 ns high pulse for each packet matching User Defined Statistic 1
2 Port 2 – 10 ns high pulse for each packet matching User Defined Statistic 1
Ixia Hardware Guide 14-3
IXIA OC12c/OC3c Load ModulesOptical Specifications14
Optical SpecificationsThe optical characteristics for the OC12c/OC3c cards are described in Table 14-6 on page 14-4.
StatisticsStatistics for OC12c cards, under various modes of operation may be found in Table E-13 on page E-43.
3 Port 1 – low during transmit of frame, otherwise high
4 Port 2 – low during transmit of frame, otherwise high
Table 14-5. OC12c/OC3c Trigger Out Signals
Pin Signal
Table 14-6. LMOC12c Optical Specifications
Specification OC12c/OC3c Multimode OC12c/OC3c Singlemode
Manufacturer Agilent MRV
Average Output Power– Min/Max -19 dBM / -14 dBM -15 dBM / -8 dBM
Transmit Center Wavelength– Min/Max
1270 nm / 1380 nm 1293 nm / 1310 nm
Receive Center Wavelength–Min/Max
1270 nm / 1380 nm 1200 nm / 1550 nm
Receive Sensitive–Min/Max -26 dBM / -14 dBM -28 dBM / -5 dBM
Safety Led based Class 1 Laser
14-4 Ixia Hardware Guide
15Chapter 15: IXIA OC48c Load Modules
The OC48c family of load modules implements Optical Carrier interfaces that runs at OC48 speeds. The interface operates in concatenated mode, as opposed to channelized mode. Different numbers of ports and interfaces are available for the different board types. Cards are available that perform Packet Over Sonet testing, Bit Error Rate Testing or both. A POS card with variable timing support is also available. The features available for these load modules are included in three tables starting with Table 1-5 on page 1-11.
One of the modules in this family, the LMOC48cBert, is shown in Figure 15-1 on page 15-1. The face plate for the same module is shown in Figure 15-2 on page 15-1.
Figure 15-1. LMOC48cBert Load Module
Figure 15-2. LMOC48cBert Face Plate
Ixia Hardware Guide 15-1
IXIA OC48c Load ModulesSpecifications15
The currently available part numbers are shown in Table 15-1 on page 15-2.
SpecificationsThe load module specifications are contained in Table 15-3 on page 15-4. Note that the -3 modules are not included in the table; their limitations versus the non-3 version are discussed in Ixia Load Modules on page 1-3.
Table 15-1. Currently Available OC48 modules
Part Number Description
LMOC48c (LMOC48111)
POS-Fixed Clock, 1-port, intermediate reach, 1310nm, singlemode
LMOC48c3(LMOC48111M)
POS-Fixed Clock, 1-port, intermediate reach, 1310nm, singlemode, manufacturing mode
LMOC48VAR(LMOC48211)
POS-Variable Clock, 1-port, intermediate reach, 1310nm, singlemode
LMOC48112 POS-Fixed Clock, 1-port, intermediate reach, 1550nm, singlemode
LMOC48112M POS-Fixed Clock, 1-port, intermediate reach, 1550nm, singlemode, manufacturing version
LMOC48311 BERT, 1-port, intermediate reach, 1310nm, singlemode
LMOC48311F BERT, 1-port, intermediate reach, 1310nm, singlemode, non-upgradeable to POS
LMOC48312 BERT, 1-port, intermediate reach, 1550nm, singlemode
LMOC48312F BERT, 1-port, intermediate reach, 1550nm, singlemode, non-upgradeable to POS
LMOC48411 POS-Fixed Clock with BERT, 1-port, 1310nm, singlemode
LMOC48411M POS-Fixed Clock with BERT, 1-port, 1310nm, singlemode, manufacturing mode
LMOC48412 POS-Fixed Clock with BERT, 1-port, 1550nm, singlemode
LMOC48412M POS-Fixed Clock with BERT, 1-port, 1550nm, singlemode, manufacturing mode
LMOC48888N Receive-only BERT, 1-port, non-upgradeable
Table 15-2. OC48 Load Module Specifications
LMOC48c LMOC48cBERTLMOC48cBERTRx
LMOC48cPOS+BERT1
LMOC48VAR
# ports 1 1 1 1
-3/-M Card Available Y N N N
Data Rate 1-100% of OC48 speeds
2.488 Gbps 1-100% of OC48 speeds
15-2 Ixia Hardware Guide
IXIA OC48c Load ModulesOC48c VAR Calibration
OC48c VAR CalibrationThis procedure allows the OC48 VAR module’s transmission frequency to be varied in order to test compliance of devices to the limits of the specification.
Frequency Adjustment
The OC48 VAR allows a variation of +/- 100 parts per million (ppm) from the clock source’s nominal frequency, via a DC voltage input into the BNC jack marked “DC IN” on the front panel. The variation is from the lowest frequency when DC IN is 0 V, to highest frequency when DC IN is 3.3 V. The input voltage should be used only within this range, although the DC IN circuitry is designed to withstand +/- 30 V in the case of accidental overdrive from a function generator. The input has a single-pole low pass at 16 Hz to keep injected noise from causing a violation of OC48 jitter specifications. As a result, the system should be given 50 to 100 milliseconds to settle after a voltage step at DC IN.
Frequency Monitoring
The frequency may be monitored via the BNC marked “Freq Monitor.” This out-put provides the OC48 line clock divided by 16. The center frequency is 155.52 MHz. The voltage is 70 mV peak-to-peak into 50 ohms, suitable for direct con-nection into a frequency counter (such as an HP53181A) via 50 ohm coaxial cable. The frequency counter should be set for 50 ohm termination in a suitably sensitive mode
Connector/ Frequency-Mode SC / 1310nm or 1550nm Singlemode
SC / 1310nm Singlemode
SC / 1310nm Singlemode
Capture buffer size 32MB N/A 32MB
Captured packet size 26-64k N/A 26-64k
Streams per port 255 N/A 255
Flows per port N/A N/A N/A
Advanced Streams 160 160
Preamble size: min-max N/A N/A N/A
Frame size: min-max 26-65,535 N/A 26-65,535
Inter-frame gap: min-max N/A N/A N/A
Inter-burst gap: min-max 1µs - 42secs N/A 1µs - 42secs
Inter-stream gap: min-max 1µs - 42secs N/A 1µs - 42secs
Latency 20ns resolution N/A 20ns resolution1. Refer to the LMOC48cPOS and LMOC48cBERT columns for the characteristics of this card when its port is in POS or
BERT mode, respectively.
Table 15-2. OC48 Load Module Specifications
LMOC48c LMOC48cBERTLMOC48cBERTRx
LMOC48cPOS+BERT1
LMOC48VAR
Ixia Hardware Guide 15-3
IXIA OC48c Load ModulesPort LEDs15
Port LEDsEach OC48c port incorporates a set of LEDs, as described in Table 15-3 on page 15-4.
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 15-4 on page 15-4.
Optical SpecificationsThe optical characteristics for the OC48c cards are described in Table 15-5 on page 15-4.
Table 15-3. LMOC48c Port LEDs
LED Label Usage
PPP Green if a PPP link has been established. Red otherwise.
Option 1 Reserved for future use.
Option 2 Reserved for future use.
LOS Red during Loss of Signal.
LOF Red during Loss of Frame
Error Red on any POS error.
Tx Green while data is transmitted.
Rx Green while data is received.
Trig Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Table 15-4. 10/100/1000 Trigger Out Signals
Pin Signal
1 Always high (no trigger available)
2 Always high (no trigger available)
3 Always high (no trigger available)
4 Always high (no trigger available)
Table 15-5. LMOC48c Optical Specifications
Specification OC48c Singlemode
Manufacturer Sumitomo
Average Output Power–Min/Max -10 dBM / -3 dBM
15-4 Ixia Hardware Guide
IXIA OC48c Load ModulesStatistics
StatisticsStatistics for OC48 cards, under various modes of operation may be found in Table E-14 on page E-48.
Transmit Center Wavelength–Min/Max 1266 nm / 1360 nm
Receive Center Wavelength–Min/Max 1260 nm / 1580 nm
Receive Sensitive–Min/Max -18 dBM / -3 dBM
Safety Class 1 Laser
Table 15-5. LMOC48c Optical Specifications
Specification OC48c Singlemode
Ixia Hardware Guide 15-5
IXIA OC48c Load ModulesStatistics15
15-6 Ixia Hardware Guide
16Chapter 16: IXIA Unframed BERT Load Modules
The unframed BERT family of load modules implements Optical Carrier inter-faces that runs at multiple rates. Rates vary from OC-3 to OC-48, including Fibre Channel and Gigabit Ethernet. A single-rate version that supports OC-3/OC-12 only is also available.
One of the modules in this family, the LMUB1MOC48P8, is shown in Figure 16-1 on page 16-1. The faceplate of this module is shown in and a close-up of the last two ports and additional connectors is shown in Figure 16-1.
Figure 16-1. LMUB1MOC48P8 Load Module
Figure 16-2. LMUB1MOC48P8 Face Plate
Ixia Hardware Guide 16-1
IXIA Unframed BERT Load Modules16
Figure 16-3. Close-up of LMUB1MOC48P8 Face Plate
Note that the connectors for odd versus even port numbers are reversed with respect to each other. For odd numbered ports, the transmit port is on the top. For even numbered ports, the transmit port is on the bottom. The labels on the face plate relate to the Tx, Rx and LOS LEDs which are next to the connectors, not to the connectors themselves.
The currently available part numbers are shown in Table 16-1 on page 16-2.
Transmit port
Receive port
Transmit port
Receive port
Table 16-1. Currently Available OC48 modules
Part Number Description
LMUB1MOC48P8 8-port, multi-rate unframed BERT, 1310nm
LMUB1SOC3P8 8-port, single-rate unframed BERT, 1310nm
LMUB2MOC48P8 8-port, multi-rate unframed BERT, 1550nm
LMUB0MOC48P8 8-port, multi-rate unframed BERT, no optical transceivers
16-2 Ixia Hardware Guide
IXIA Unframed BERT Load ModulesSpecifications
SpecificationsThe load module specifications are contained in Table 16-2 on page 16-3.
Table 16-2. Unframed BERT Load Module Specifications
LMUB1MOC48P8LMUB2MOC48P8
LMUB0MOC48P8 LMUB1SOC3P8
# ports 8 8 8
-3/-M Card Available N N N
Data Rate 2.488Gbps (OC-48)2.67Gbps (OC-48 w/FEC)622.08Mbps (OC-12)666.51Mbps (OC-12 w/FEC)155.52Mbps (OC-3)166.63Mbps (OC-3 w/FEC)1.062Mbps (Fibre Channel)2.125Gbps (2xFibre Channel)1.25Gbps (Gigabit Ethernet)
2.488Gbps (OC-48)2.67Gbps (OC-48 w/FEC)622.08Mbps (OC-12)666.51Mbps (OC-12 w/FEC)155.52Mbps (OC-3)166.63Mbps (OC-3 w/FEC)1.062Mbps (Fibre Channel)2.125Gbps (2xFibre Channel)1.25Gbps (Gigabit Ethernet)
622.08Mbps (OC-12)155.52Mbps (OC-3)
Connector/Frequency-Mode1
1310nm (LMUB1MOC48P8) 1550nm (LMUB2MOC48P8) SFP LC Singlemode
N/A 1310nm SFP LC Singlemode
Capture buffer size N/A N/A N/A
Captured packet size N/A N/A N/A
Streams per port N/A N/A N/A
Flows per port N/A N/A N/A
Advanced Streams N/A N/A N/A
Preamble size: min-max N/A N/A N/A
Frame size: min-max N/A N/A N/A
Inter-frame gap: min-max
N/A N/A N/A
Inter-burst gap: min-max N/A N/A N/A
Inter-stream gap:min-max
N/A N/A N/A
Latency N/A N/A N/A1. See Clock-in / Clock-out Connectors below for a discussion of the auxiliary clock-in/clock-out connectors.
Ixia Hardware Guide 16-3
IXIA Unframed BERT Load ModulesClock-in / Clock-out Connectors16
Clock-in / Clock-out ConnectorsTwo additional SMA connectors are used for external clock in and clock out. The use of these signals is described in .
LEDsThe lower portion of the card displays a set of LEDs, as seen in Table 16-3 on page 16-2 and described in Table 16-4 on page 16-4.
Table 16-3. Unframed Bert Clock-in/Clock-out Signal Usage
Card Type Clock-in Clock-out
Single-Rate 77.76MHz ± 20PPM with 1V peak-to-peak maximum input.
Transmit rate from port 1 divided by 8. Output frequency stability for all values is ± 20PPM.
Multi-Rate 132.75MHz to 166.63MHz ± 100PPM with 1V peak-to-peak maximum input.
Transmit rate from port 1 divided by 16. Output frequency stability for all values is ± 20PPM.
Table 16-4. Unframed Bert Card-Level LEDs
LED Label Usage
Status One of three states:• Green–normal operation• Off–busy during configuration• Red–error condition
Int (Clock) Off if the external clock is selected. Blinks green to indicate the clock speed selected:• SONET: 1 time then pauses• SONET FEC: 2 times then pauses• Fibre Channel: 3 times then pauses• Gigabit Ethernet: 4 times then pauses
Ext (Clock) Green when the External Clock is selected, and off otherwise.
16-4 Ixia Hardware Guide
IXIA Unframed BERT Load ModulesOptical Specifications
Each unframed Bert port incorporates a set of LEDs, as described in Table 16-5 on page 16-5.
Optical SpecificationsThe optical characteristics for the unframed Bert cards are described in Table 16-6 on page 16-5.
StatisticsStatistics for unframed Bert cards may be found in Table E-14 on page E-48.
Table 16-5. Unframed Bert Per-Port LEDs
LED Label Usage
Tx Shows green when port is transmitting; this is true as soon as the card is configured since the port is always transmitting.
Rx Will show one of three states:• Green–a pattern has been locked onto and no errors have
been detected.• Red–a pattern has been locked onto, but errors have been
detected.• Off–no pattern has been locked onto.
LOS Will show one of two states:• Off–a pattern has been locked onto.• Red–no pattern has been locked onto.
Table 16-6. Unframed Bert Optical Specifications
Specification At 1310nm At 1550nm
Extinction Ratio–Min 8.2db 9db
Average Output Power–Min/Max -10 dBM / -3 dBM -5 dBM / 0 dBM
Receive Sensitive–Typical/Max -22 dBM / -3 dBM -25.5 dBM / 0 dBM
Safety Class 1 Laser Class 1 Laser
Ixia Hardware Guide 16-5
IXIA Unframed BERT Load ModulesStatistics16
16-6 Ixia Hardware Guide
17Chapter 17: IXIA OC192c Load Modules
The OC192c family of load modules implements Optical Carrier interfaces that run at OC192 speeds. The interface operates in concatenated mode, as opposed to channelized mode. Different numbers of ports and interfaces are available for the different board types. Cards are available that perform Packet Over Sonet testing, Bit Error Rate Testing or both. The features available for these load modules are included in are included in three tables starting with Table 1-5 on page 1-11.
The Ixia VSR modules, which were developed in accordance with the OIF Implementation Agreement VSR-1, use twelve parallel multi-mode fiber optic lines operating at 1.25Gbps per channel, instead of existing 1310nm or 1550nm serial optics. VSR optics are designed to drive signals over distances less than 300 meters, which is sufficient for interconnecting devices within a service pro-vider's Point-of-Presence (POP). Over these short distances, VSR optics offer a significant cost savings compared to intermediate and long-reach serial lasers.
One of the modules in this family (the LMOC192cPOS) is shown in Figure 17-1 on page 17-1. The face plate for the same module is shown in Figure 17-2 on page 17-2.
Figure 17-1. LMOC192c Load Module
Ixia Hardware Guide 17-1
IXIA OC192c Load ModulesPart Numbering Scheme17
Figure 17-2. LMOC192c Face Plate
Part Numbering SchemeThe OC192 cards come with a number of options. All part numbers are of the form:
LMOC192HTOS or
LMFOC192HTOS
where H is the hundreds designator, T is the tens designator, O is the ones desig-nator and S is the suffix.
LMF boards have no fiber optic interface. It allows for quick validation of serial-izer and deserializer designs for WAN Packet over Sonet/SDH products operat-ing at the STS-192c/STM-64 level. The LMF interface is a 300 pin MegaArray BERG connector, which is an industry standard MSA interface and is compliant per OIF1999.102.8, SFI-4 specification. A reference clock can be supplied through this interface ranging in frequency from 25MhHz to 622 MHz. The spec-ification of this interface may be found in Appendix B, OC192c Emulator Board (LMF) Interface Specification.
The currently available part numbers are shown in Table 17-1 on page 17-2.Table 17-1. Currently Available OC192 modules
Part Number Description
LMOC192101 POS, 1-port, intermediate reach (SR1), 1310nm, singlemode
LMOC192111 POS, 1-port, intermediate reach, 1310nm, singlemode
LMOC192112 POS, 1-port, intermediate reach, 1550nm, singlemode
LMOC192141 POS, 2-port, intermediate reach, 1310nm, singlemode
LMOC192142 POS, 2-port, intermediate reach, 1550nm, singlemode
LMOC192168 POS, 1-port, VSR optics, parallel interface
LMF192188 POS, 1-port, no optics
LMF192198 POS, 2-port, no optics
LMOC192311 BERT, 1-port, intermediate reach, 1310nm, singlemode
LMOC192312 BERT, 1-port, intermediate reach, 1550nm, singlemode
17-2 Ixia Hardware Guide
IXIA OC192c Load ModulesSpecifications
SpecificationsThe load module specifications are contained in Table 17-3 on page 17-4. Note that the -M modules are not included in the table; their limitations versus the non-M version are discussed in Ixia Load Modules on page 1-3.
LMOC192341 BERT, 2-port, intermediate reach, 1310nm, singlemode
LMOC192342 BERT, 2-port, intermediate reach, 1550nm, singlemode
LMOC192368 BERT, 1-port, VSR optics, parallel interface
LMOC192378 BERT, 2-port, VSR optics, parallel interface
LMOC192411 POS with BERT, 1-port, intermediate reach, 1310nm, singlemode
LMOC192412 POS with BERT, 1-port, intermediate reach, 1550nm, singlemode
LMOC192441 POS with BERT, 2-port, intermediate reach, 1310nm, singlemode
LMOC192442 POS with BERT, 2-port, intermediate reach, 1550nm, singlemode
LMOC192468 POS with BERT, 1-port, VSR optics
LMOC192611 POS+WAN, 1-port, intermediate reach, 1310nm, singlemode
LMOC192612 POS+WAN, 2-port, intermediate reach, 1550nm, singlemode
LMOC192711 POS+BERT+WAN, 1-port, intermediate reach, 1310nm, singlemode
LMOC192712 POS+BERT+WAN, 1-port, intermediate reach, 1550nm, singlemode
LMOC192898N Receive-only BERT, 2-port, non-upgradeable
Table 17-1. Currently Available OC192 modules
Part Number Description
Table 17-2. OC192 Load Module Specifications
LMOC192cPOS LMOC192cBERT LMOC192cPOS+BERT1
# ports 1 or 2 1 or 2
-M Card Available Y N
Data Rate 1-100% of OC192 speeds
N/A
Connector/Frequency-Mode
SC / 1310nm or 1550nm Singlemode
SC / 1310nm or 1550nm Singlemode
SC / 1310nm or 1550nm Singlemode
Capture buffer size 32MB N/A
Ixia Hardware Guide 17-3
IXIA OC192c Load ModulesPort LEDs17
Port LEDsEach OC192c port incorporates a set of 10 LEDs, as described in Table 17-3 on page 17-4.
Captured packet size 33-64k N/A
Streams per port 255 N/A
Flows per port N/A N/A
Advanced streams 160 N/A
Preamble size: min-max
N/A N/A
Frame size: min-max 54-1600 N/A
Inter-frame gap: min-max
N/A N/A
Inter-burst gap: min-max
N/A N/A
Inter-stream gap:min-max
4ns - 42secs N/A
Latency 20ns resolution N/A1. Refer to the LMOC192cPOS and LMOC192cBERT columns for the characteristics of
this card when its port is in POS or BERT mode, respectively.
Table 17-2. OC192 Load Module Specifications
LMOC192cPOS LMOC192cBERT LMOC192cPOS+BERT1
Table 17-3. LMOC192cPOS Port LEDs
LED Label Usage
LOS Red during Loss of Signal.
LOF Red during Loss of Frame
PPP Green if a PPP link has been established. Red otherwise.
Tx Green while data is transmitted.
Rx Green while data is received.
Error Red on any POS error.
Trigger Follows the state of the Trigger Out pin, which is programmed via User Defined Statistic 1.
Option 1 Reserved for future use.
Option 2 Reserved for future use.
LASER ON Green when the port’s laser is turned on.
17-4 Ixia Hardware Guide
IXIA OC192c Load ModulesTrigger Out Values
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 17-4 on page 17-5.Table 17-4. OC192 Trigger Out Signals
Pin Signal
1 Port 1 – RX_TOH_CLK – clock synchronous to the receive SONET transport overhead
2 Port 2 – RX_TOH_CLK – clock synchronous to the receive SONET transport overhead
Ixia Hardware Guide 17-5
IXIA OC192c Load ModulesOptical Specifications17
Optical SpecificationsThe optical characteristics for the OC192c cards are described in Table 17-5 on page 17-6.
StatisticsStatistics for OC192 cards, under various modes of operation may be found in Table E-15 on page E-52.
Table 17-5. LMOC192c Optical Specifications
Specification OC192c 1310nm OC192c 1550nm OC192c VSR-1
Manufacturer GTRAN GTRAN Gore
Average Output Power–Min/Max -4 dBM / 0 dBM -4 dBM / 0 dBM -10 dBM / -4 dBM
Transmit Center Wavelength–Min/Max 1300 nm / 1320 nm 1530 nm / 1565 nm 830 nm / 860 nm
Receive Center Wavelength–Min/Max 1280 nm / 1580 nm 1280 nm / 1580 nm 770 nm / 860 nm
Receive Sensitive–Min/Max -16 dBM / 0 dBM -15 dBM / 0 dBM -16 dBM / 0 dBM
Safety Class 1 Laser Class 1 Laser Class 1 Laser
17-6 Ixia Hardware Guide
18Chapter 18: IXIA 10Gigabit Ethernet Load Modules
The 10 Gigabit Ethernet (10GE) family of load modules implements five of the seven IEEE 8.2.3ae compliant interfaces that run at 10Gbit/second. Cards are available which offer the following interfaces:
• 10GBASE-R (LAN): 10GBASE-SR, 10GBASE-LR, 10GBASE-ER
• 10GBASE-W(WAN): 10GBASE-LW and 10GBASE-EW
• XAUI
• XENPAK
In addition, a triple mode card is available which offers combined software selectable 10GBASE-W (WAN), OC192 POS and BERT functionality. The fea-tures available for these load modules are included in three tables starting with Table 1-5 on page 1-11.
Figure 18-1 on page 18-2 is a picture of four of the load module in the family.
Ixia Hardware Guide 18-1
IXIA 10Gigabit Ethernet Load Modules18
Figure 18-1. 10GE Load Modules
The currently available part numbers are shown in Table 18-1 on page 18-2. Refer to Table 17-1 on page 17-2 as well for a listing of OC192c / 10GBASE combination modules.Table 18-1. Currently Available 10GE modules
Part Number Description
LM10GE123F 10GBASE-LW (WAN), 1-port, 1310nm, singlemode
LM10GE124F 10GBASE-EW (WAN), 1-port, 1550nm, singlemode
LM10GE221F 10GBASE-SR (LAN), 1-port, 850nm, multimode
LM10GE221M 10GBASE-SR (LAN), 1-port, 850nm, multimode, manufacturing mode
LM10GE223F 10GBASE-LR (LAN), 1-port, 1310nm, singlemode
LM10GE223M 10GBASE-LR (LAN), 1-port, 1310nm, singlemode, manufacturing mode
LM10GE224F 10GBASE-ER, (LAN) 1-port, 1310nm, singlemode
18-2 Ixia Hardware Guide
IXIA 10Gigabit Ethernet Load Modules
The following additional XAUI accessories are also available. These items are discussed in Appendix D, XAUI Connector Specifications
LM10GE224M 10GBASE-ER (LAN), 1-port, 1310nm, singlemode, manufacturing mode
LM10GE500F1 10GBASE (XAUI), 1 port
LM10GE500F1B 10GBASE (XAUI), Ethernet/BERT, 1 port
LM10GE500M1B 10GBASE (XAUI), BERT, 1 port
LM10GE623F 10GBASE-LW, BERT (WAN), 1-port, 1310nm, singlemode
LM10GE624F 10GBASE-EW, BERT (WAN), 1-port, 1550nm, singlemode
LM10GE700F1 10GE (XENPAK), Ethernet, 1-port
LM10GE700M1 10GE (XENPAK), Ethernet, 1-port, manufacturing mode
Table 18-2. 10GE XAUI Accessories
Part Number Description
CAB10GE500S1 XAUI cable, 20 inch, standard pinout
CAB10GE500S2 XAUI cable, 40 inch, standard pinout
BOB10GE500 XAUI SMA break-out box
CON10GE500 XAUI Fujitsu MicroGiGa connector
LPG10GE500 XAUI front panel loopback connector
FXN10GE500 XAUI Fujitsu to XENPAK Adapter
FTY10GE500 XAUI Tyco interoperability backplane HM-Zd adapter
Table 18-1. Currently Available 10GE modules
Part Number Description
Ixia Hardware Guide 18-3
IXIA 10Gigabit Ethernet Load ModulesSpecifications18
SpecificationsThe load module specifications are contained in Table 18-4 on page 18-5.
Table 18-3. 10GB Load Module Specifications
10GBASE-W (WAN)
10GBASE-W (WAN/BERT)
10GBASE-R (LAN)
10GBASE (XAUI)
10GBASE (XAUI/BERT)
10GBASE (XENPAK)
# ports 1 1 1 1 1 1
-M Card Available N N Y N N Y
Data Rate 1-100% of 10Gbps speeds
N/A 10GB 10GB N/A 10GB
Connector/Frequency-Mode
SC / 1310nm or 1550nm Singlemode
SC / 1310nm or 1550nm Singlemode
SC / 850 multimode, 1310nm or 1550nm Singlemode
See XAUI Connectors on page 18-6
See XAUI Connectors on page 18-6
See .XENPAK Connectors on page 18-9
Capture buffer size 32MB N/A 32MB 32MB N/A 32MB
Captured packet size
24-65,535 bytes
N/A 24-65,535 bytes
24-65,535 bytes
N/A 24-65,535 bytes
Streams per port 255 N/A 25532 (-M version)
255 N/A 25532 (-M version)
Flows per port N/A N/A N/A N/A N/A N/A
Advanced streams 160 N/A 16016 (-M version)
160 N/A 160
Preamble size: min-max
4-252 N/A 4-252 4-252 N/A 4-252
Frame size: min-max
24-65,535 N/A 24-65,535 24-65,535 N/A 24-65,535
Inter-frame gap: min-max
3/4ns - 43sec in 3.4ns steps
N/A 3.2ns - 42sec in 3.2ns steps
3.2ns - 42sec in 3.2ns steps
N/A 3.2ns - 42secin 3.2ns steps
Inter-burst gap: min-max
3/4ns - 43sec in 3.4ns steps
N/A 3.2ns - 42sec in 3.2ns steps
3.2ns - 42sec in 3.2ns steps
N/A 3.2ns - 42secin 3.2ns steps
Inter-stream gap:min-max
3/4ns - 43sec in 3.4ns steps
N/A 3.2ns - 42sec in 3.2ns steps
3.2ns - 42sec in 3.2ns steps
N/A 3.2ns - 42secin 3.2ns steps
Latency 20ns resolution
N/A 20ns resolution
20ns resolution
N/A 20ns resolution
18-4 Ixia Hardware Guide
IXIA 10Gigabit Ethernet Load ModulesPort LEDs
The LAN and XAUI manufacturing mode boards include a set of features expanded from other manufacturing mode boards. The LAN-M, XAUI-M boards includes all of the features of the LAN/XAUI board with the following excep-tions:
• No support for routing protocols
• No real-time latency, but timestamps are included
• 32 streams in packet stream mode
• 16 streams in advanced scheduler mode
Port LEDsEach 10GB port incorporates a set of LEDs, as described in the following tables.Table 18-4. WAN Port LEDs
LED Label Usage
LOS Red during Loss of Signal.
LOF Red during Loss of Frame
Link Green if Ethernet link has been established. Red otherwise.
Tx Green while data is transmitted.
Rx Green while data is received.
Error Red on any Ethernet error.
Trigger See below.
Option Reserved for future use.
LASER ON Green when the port’s laser is turned on.
Table 18-5. LAN/XAUI/XENPAK Port LEDs
LED Label Usage
Link Green if Ethernet link has been established, red otherwise. Link may be down due to no signal or no PCS lock.
Tx/Pause Green while data is transmitted. Red while flow control frames are received. Off if no traffic is passing in either direction.
Rx/Error Green while data is received. Red on any Ethernet error. Off if no frames are received.
Trigger See below.
Option Reserved for future use.
Ixia Hardware Guide 18-5
IXIA 10Gigabit Ethernet Load ModulesOptical Specifications18
Optical SpecificationsThe optical characteristics for the 10GE cards are described in Table 18-6 on page 18-6.
XAUI ConnectorsThe following connectors and adapters are available for the XAUI Load Modules and are discussed in Appendix D, XAUI Connector Specifications.
• Standard Connector Specifications–the signals carried on the Load Module’s XAUI connector.
• Front Panel Loopback Connector–a connector used to loopback XAUI sig-nals at the external connector.
• Standard Cable Specification–the CAB10GE500S1 (20”) and CAB10GE500S2 (40”) cables.
• SMA Break-Out Box–the BOB10GE500 SMA break-out box.
• XAUI Fujitsu to XENPAK Adapter–an adapter used with Ixia XENPAK load modules to create a XAUI interface.
• XAUI Tyco Interoperability Backplane HM-Zd Adapter–an adapter used to connect to the Tyco Interoperability Backplane.
MDIO A Management Data Input/Output (MDIO) interface is provided to the user. The Ixia Load Module acts as the Station Management entity (STA), and can control one or more MDIO Manageable Devices (MMD) in the users system. Multiple MMDs can be attached to the interface. The user can set/read the MDIO control/status registers inside a MMD via a graphical user interface.
The connector used for the MDIO interface is a 15-pin female D-sub and pro-vides the user with the ability to add up to two external Mii interfaces compliant to either 802.3 clause 22 or 802.3ae clause 45. The connector pin assignments,
Table 18-6. 10GE Optical Specifications
Specification 10GBASE-SR (LAN) 850nm
10GBASE-LR (LAN) 1310nm
10GBASE-ER (LAN) 1550nm
10GBASE-LW (LAN) 1310nm
10GBASE-EW (LAN) 1550nm
Tx Power (dBm) -5 to -1 -6 to 2 -4 to 0 -4 to 0 -4 to 0
Rx Sensitivity (dBm)
-7 to -1 -11 to -1 -5 to 2 -17 to 2 -17 to 2
Safety Class 1 Laser Class 1 Laser Class 1 Laser Class 1 Laser Class 1 Laser
18-6 Ixia Hardware Guide
IXIA 10Gigabit Ethernet Load ModulesXAUI Connectors
Mii Interface, signal names, and functional descriptions are listed in Table 18-7 on page 18-7.
Figure 18-2. MDC/MDIO D-sub Connector Pin Assignments
The MDIO/MDC interface has a clock line (MDC) and bi-directional data line (MDIO) as defined in IEEE 802.3ae. In addition to these, a +5Vdc supply, and data direction control line (DIR) are provided to make interfacing easier for the user. The +5Vdc output is intended to power buffers and/or optocouplers at the
Table 18-7. MDC/MDIO Connector Pin Assignments
Pin No. Mii Interface Signal Name Functional Description
1 External 2 DIR Data direction control.
2 External 2 MDC Clock.
3 External 2 MDIO Bi-directional data.
4 External 2 +5V +5Vdc supply.
5 External 1 +5V +5Vdc supply.
6 External 1 MDIO Bi-directional data.
7 External 1 MDC Clock.
8 External 1 DIR Data direction control.
9-15 GND GND Ground
WARNING: The MDIO on the Ixia XAUI Load Module is 3.3V while the Ixia XENPAK Load Module, when used with the adapter for XAUI, is 1.2V. The reason for the difference is that the XENPAK MSA requires 1.2V for MDIO whereas most XAUI SerDes chips require 3.3V (LVTTL). Therefore, when using the XAUI Load Module to test a XENPAK transceiver or SerDes, which require 1.2V, a level shifter is needed to convert 3.3V to 1.2V.
Ixia Hardware Guide 18-7
IXIA 10Gigabit Ethernet Load ModulesXAUI Connectors18
user-end of the cable. This supply can be turned ON or OFF under software con-trol through the GUI.
The +5Vdc supply is OFF when the chassis is initially powered-up, or following a reset.
Reference Clock In/Out
The XAUI load module provides coaxial connectors for clock input and clock output to allow the DUT to phase-lock with the XAUI interface. When running off an external clock, the clock input signal must meet the requirements listed in Table 18-8 on page 18-8 in order to ensure proper performance of the load mod-ule.
The clock in/out electrical interface parameters are defined in Table 18-9.
The load module contains a phase-locked loop (PLL) that reduces the jitter of the input clock, either from the internal or external clock source. The output of this PLL is driven out on the REF CLK OUT connector. The bandwidth of the PLL is approximately 1kHz. The user can modulate the REF CLK IN frequency up to 1kHz, but it is not recommended, as some degradation of the load module’s per-formance may result.
Table 18-8. XAUI Reference Clock Input Requirements
Parameter Characteristic
Frequency 156.25 MHZ ±100ppm
Jitter ±150ps max. cycle to cycle, >1kHz
Amplitude 1.3 Vpp minimum, into 50 Ω
Duty cycle 40 to 60%
Edge rates (20% to 80%) 600ps maximum, into 50 Ω
Table 18-9. Clock In/Out Electrical Interface Parameters
Parameter Characteristic
ClockInput
Connector Female SMA
Impedance 50 ohm ± 5%, DC coupled
Absolute max input 6V (DC plus half AC peak-to-peak
ClockOutput
Connector Female SMA
Impedance 50 ohm ± 5%, AC coupled
Amplitude 1.3 Vpp minimum, into 50 Ω. (1.5 Vpp typical)
Edge rates 200ps to 340ps (20% to 80%) into 50Ω
Duty cycle 45% to 55%
Jitter 20ps max cycle to cycle, >1kHz
Frequency 156.25 MHz ±20ppm (internal clock mode)
18-8 Ixia Hardware Guide
IXIA 10Gigabit Ethernet Load Modules.XENPAK Connectors
Trigger Out Values The Load Module provides two outputs that can be used to trigger to external equipment for the purpose of capturing events. The Trigger-A and Trigger-B events are independent, TTL pulse and user-defined through IxExplorer or TCL API.
.XENPAK Connectors
Clock In/Out Two coaxial connectors provide clock input and clock output to allow the user to phase-lock the XAUI interface with the DUT.
Power Sequencing Specification
The Xenpak 2.1 MSA does not specify any particular power sequencing for the various Xenpak power supply rails (3.3V, 5V, and APS).
When Xenpak Power is enabled, power sequencing is as follows:
• The 5V rail comes up first, with a ramp-up time of approximately 2.25 ms.
• The 3.3V and APS rails both start to come up about 500 us after 5V rail is up.
• The 3.3V supply has a ramp-up time of approximately 2 ms.
• The APS supply ramp-up time varies, according to level required by APS Set resistor, but will be no more than 2 ms. When no Xenpak module is inserted into the Load Module, APS voltage is less than 150 mV.
Reset Hardware asserts a Reset by bringing Xenpak connector pin 10 low whenever either of the following conditions is true:
• The Xenpak module is not inserted into the load module; i.e. Xenpak pin 14 is high.
• Xenpak power is turned off.
The hardware continues to assert Reset until both of these items are false. Once Xenpak Power is asserted, or if a Xenpak is hot-plugged, the system waits 5 sec-onds for Xenpak initialization (per MSA 2.1). Reset is then de-asserted, and the system waits an additional 500 ms for any vendor-based reset management to complete initialization. After this final 500 ms delay, the load module assumes the Xenpak module is ready for MII access or to transmit and receive.
Trigger Out ValuesThe signals available on the trigger out pins for all cards in this category are described in Table 18-10 on page 18-9.Table 18-10. 10GE Trigger Out Signals
Pin Signal
1 Always high (no trigger available)
2 Always high (no trigger available)
Ixia Hardware Guide 18-9
IXIA 10Gigabit Ethernet Load ModulesStatistics18
StatisticsStatistics for 10GB cards, under various modes of operation may be found in Table E-16 on page E-57.
3 Always high (no trigger available)
4 Always high (no trigger available)
Table 18-10. 10GE Trigger Out Signals
Pin Signal
18-10 Ixia Hardware Guide
AAppendix A: Time and Frequency Module
Time and Frequency ModuleThe Time and Frequency Module (TFM) provides extremely accurate TIME and FREQUENCY that is traceable to the UNITED STATES NAVAL OBSERVA-TORY (USNO) by use of the NAVSTAR Global Positioning System (GPS).
The purpose of the TFM is to provide accurate time, frequency and position as derived from Coarse Acquisition (C/A) Link 1 (L1) signals transmitted by the NAVSTAR Global Positioning System (GPS) satellites. The TFM is usable on a world-wide basis under any weather conditions.
The TFM is completely automatic in satellite acquisition and time and frequency synchronization.
The TFM receiver will operate when the satellites are 10 degrees above the hori-zon and their signals are not obstructed. Whenever entered position information is less accurate than 10 m, the TFM will first have to accurately ascertain its antenna position by tracking four or more satellites and performing a long term (24 hours) average of position fixes in order to maintain time and frequency accuracy and stability within specification. From that point on, the TFM will require only one satellite (above 10 degrees) to maintain valid time and fre-quency. However, operation to specified stability requires four or more satellites. When no satellites are in view, the TFM will continue to output its signals using the internal disciplined oscillator.
The Time and Frequency Module (TFM) consists of a receiver, antenna unit and cable. Since the on-board oscillator is a Temperature Compensated Crystal Oscil-lator (TCXO), it is essential that it be isolated from rapid fluctuations in air tem-perature. For this reason, operation of the TFM mounted in an enclosure is required in order to obtain specified stability performance levels.
Ixia Hardware Guide A-1
Time and Frequency ModuleA
SpecificationsTable A-11. Time and Frequency Module Specifications
TFM
Size: 3.99 in x 6.30 in (13 cm x 16 cm)
Weight: 0.25 lb. (0.11 kg)
Power: +12 VDC, 220 mA (no antenna)
Power Consumption: <6 W
Standard Antenna
Size: 2.625 in dia. x 1.5 in (6.67 cm dia. x 3.81 cm)
Weight: 0.70 lb. (0.318 kg) (including mounting mast)
Power Regulated: +12 VDC @ <30 mA
Frequency (L1): 1575.42 MHz Coarse Acquisition (C/A) Code
Optional Down/Up Converter
Down Converter Antenna Size: 4.4 in dia. x 2.1 in (11.17 cm dia. x 6.85 cm)
Down Converter Antenna Weight: 0.60 lb. (0.272 kg) (including mounting mast)
Down Converter Antenna Power Regulated:
+12 VDC @ <135 mA ±10%
Up Converter Size: 6.8 in x 4.2 in x 1.8 in (17.27 cm x 10.67 cm x 4.57 cm)
Up Converter Weight: 1.5 lb. (0.68 kg)
Up Converter Power Regulated: +12 VDC @ 200 mA ±10% (including down converter)
Antenna Cable (for Standard Antenna)
Type: RG-59Attenuation at 1.575 G should be no more than 10.5 dB per 100 ft. (Belden 9104 or equivalent)
Length: 50 ft. (available in lengths up to 200 ft.)
Weight: 1.2 lb. (0.545 kg)
Antenna Cable (for Down/Up Converter Antenna)
Type: RG-58
Length: available in lengths 150 to 1500 ft.
A-2 Ixia Hardware Guide
Time and Frequency Module
Environmental Specifications
Timing/Frequency Performance Specifications
All performance specifications are valid when the antenna’s geodetic position is known within 10 m in WGS-84 and four or more satellites are being tracked. In addition, in order to achieve the stated accuracy, the receiver must be mounted in an enclosure that will eliminate exposure of the internal oscillator to rapid temperature fluctuations due to air currents.
WARNING: Antenna and Antenna Down/Up Converter Units are mounted on a 12 inch long PVC mast with 3/4-inch Male Pipe Thread (MPT) on both ends. The above specified overall lengths of the Antenna and Antenna Down Converter Units are therefore increased by approximately 11.25 inches when the mounting mast is included.
Table A-12. Environmental Specifications
Operating Temperature
TFM: 0 to +50 °C (+32 to +122 °F)
Antenna or Antenna Down/Up Converter: –40 to +70 °C (–40 to +158 °F)
Storage Temperature
TFM: –40 to +85 °C (–40 to +185 °F)
Antenna or Antenna Down/Up Converter: –55 to +85 °C (–67 to +185 °F)
Humidity
TFM: 95%, non-condensing
Antenna or Ant. Down Converter: 100%, condensing
Table A-13. Timing/Frequency Performance Specifications
TFM Specifications
Frequency: 1575.42 MHz (L1 signal)
Code: Coarse Acquisition (C/A) code
Tracking: Up to eight satellites
Acquisition Time: Less than 2 minutes if satellites visible, position correct within 1 km. Position error greater than 1 km may require 15 minutes or longer with satellites visible. See Section 3.
Single Fix Position Accuracy:
Within 25 m (SEP) referred to WGS84 when sequentially tracking four or more satellites with a PDOP ≤6; 100 m (2 arms) if SA is enabled.
24 Hour Averaged Position Accuracy:
<10 m
Accuracy: UTC-USNO <40 ns rms (150 ns peak)
Ixia Hardware Guide A-3
Time and Frequency ModuleA
Procedure The TFM antenna unit should have an unobstructed view of the sky. Connect the cable between the Antenna unit and TFM antenna input connector. If satellites are visible and the TFM has an accurate position, lock should be achieved within two minutes.
Satellite Acquisition Time to first satellite acquisition is dependent upon many factors. The following paragraphs describe some of the possible events which affect satellite acquisition times. Note that satellite visibility at the receiver site will affect acquisition times.
If the Time and Frequency receiver was tracking satellites immediately prior to a momentary power interruption, satellite re-acquisition will be almost immediate with valid UTC time available within two minutes.
If the current position is unknown or in error by more than 100 km, acquisition typically requires from 3 to 15 additional minutes to locate current antenna posi-tion, reacquire satellite almanac and ephemeris data, and deliver UTC time.
If internal almanac data is lost, the time to first satellite acquisition will depend upon which satellites are visible at the time of power-on. The TFM will attempt to acquire satellites not knowing which satellites are visible. The satellite search will be expanded until a satellite is acquired. After first satellite acquisition, time will be acquired from the satellite and the receiver will return to normal opera-tion. This procedure may take as little as three minutes to as long as 15 minutes depending upon current satellite visibility.
Frequency Output Accuracy:
<3 x 10-12
Frequency & Timing Stability:
Allan Deviation1 x 10-9 @1 sec.3 x 10-10 @10 sec.3 x 10-10 @100 sec.3 x 10-12 @1 day
Oscillator Stability: 2 x 10-6, over 0°C to 50°C when not tracking satellites
Table A-13. Timing/Frequency Performance Specifications
A-4 Ixia Hardware Guide
BAppendix B: OC192c Emulator Board (LMF) Interface Specification
DescriptionThe Customers Interface Module (CIM) must provide the transmit reference clock (TX_PCLK P/N) and the receive clock (RX_POCLK P/N). These clocks have been tested down to 700KHz but should be able to work at lower frequen-cies.
TX_PCLK P/N provides the AMCC Ganges SONET Framer with a transmit ref-erence clock source that the Ganges uses to send out both clock (TX_PICLK P/N) and data (TX_DATA P/N). Data is valid on the rising edge of “TX_PICLK P/N”.
The “RX_POCLK P/N” provides the Ganges with a receive clock with which it will sample the receive data (RX_DATA P/N). Data should be valid on the falling edge of “RX_POCLK P/N”.
SpecificationsThe specifications given below are the requirements of a fiber optic transponder, which is normally installed in the 300 pin Berg location. Keeping to these speci-fications will insure proper operation.
Electrical PerformanceTable B-1. Power Supply Characteristics
No. Parameter Symbol. Min. Typ. Max. Units Remarks
1 Supply Voltage
VCC 4.75 5.0 5.25 V
2 Supply Voltage
VDD 3.13 3.3 3.47 V
3 Supply Voltage
VEE -4.94 -5.2 -5.45 V
Ixia Hardware Guide B-1
SpecificationsB
4 Supply Current
ICC - - 0.8 A +5 V
5 Supply Current
IDD - - 2.0 A +3.3 V
6 Supply Current
IEE - - 1.8 A -5.2 V
7 Power Consumption
PDS - 9.5 14 W
Table B-1. Power Supply Characteristics
No. Parameter Symbol. Min. Typ. Max. Units Remarks
Table B-2. LVTTL Level
No. Parameter Symbol Min. Typ. Max. Unit Remarks
1 Input High Voltage
VIH 2. 0 - - V -
2 Input Low Voltage
VIL - - 0.8 V -
3 Output High Voltage
VOH 2.0 - - V -
4 Output Low Voltage
VOL - - 0.8 V
Table B-3. Transmitter Electrical I/O Characteristics
No. Parameter Symbol Min. Typ. Max. Unit Remarks
1 Data and Clock Input Level
TxDinTxPICLK
LVDS Compatible
Differential Swing 200 - - mV
Voltage Range 800 - 2400 mV
Differential Impedance 80 120
2 Clock Output Voltage TxPCLK LVDS CompatibleRload 100 ohmHigh 1.1 - 1.8 V
Low 0.85 - 1.5 V
Differential Swing 250 - 1100 mV
B-2 Ixia Hardware Guide
Specifications
Mechanical Dimensions
Figure B-1. HS Interface
Table B-4. Receiver Electrical I/O Characteristics
No. Parameter Symbol Min. Typ. Max. Unit Remarks
1 Data and Clock Output Level RxDoutRxPOCLK
LVDS Compatible
High 1.1 1.8 V
Low 0.85 1.5 V
Differential Swing 250 1100 mV
Table B-5. Electrical Interface
No. Part Name Manufacturer Remarks
1 84501 or 84502 FCI Module
2 84500 FCI Ixia
TX_DATAP
TX_DATAN
FR_PICLK P
FR_PICLK N
REFCLK
SYS_REFCLKIN+
SYS_REFCLKIN-
RX_DATAP
RX_DATAN
RX_CLKI+
RX_CLKI-
TXDATA P[15:0]
TXDATA N[15:0]
TX_PICLK P
TX_PICLK N
TX_PCLKP
TX_PCLKN
RXDATA P[15:0]
RXDATA N[15:0]
RXPOCLKP
RXPOCLKN
TX_REFCLK P
TX_REFCLK N
RXMCLKP
RXMCLKN
RXREFCLKP
RXREFCLKN
TX_DATA and TX_PICLK to be equal length +/- 0
RX_DATA and FOM_RXPOCLK to be equal length +/- 0
TX_DATA [P/N - 15:0]
TX_PICLK [P/N]
SYS_REFCLKIN[+/-] FOM_PCLK [P/N]
RX_DATA [P/N - 15:0]
FOM_RXPOCLK [P/N]
Ixia Hardware Guide B-3
SpecificationsB
Table B-6. Pin Configuration
K J H G F E D C B A
1 +5V Analog TBD Frame GND RxDout12P TBD RxDout8P Digital GND RxDout4P Digital GND RxDout0P
2 +5V Analog TBD Frame GND RxDout12N TBD RxDout8N Digital GND RxDout4N Digital GND RxDout0N
3 Reserved FFU Reserved FFU TBD Digital GND RxLOPMON Digital GND TBD Digital GND TBD Digital GND
4 +3.3V Analog TBD Frame GND RxDout13P +3.3V Digital RxDout9P Digital GND RxDout5P Digital GND RxDout1P
5 +3.3V Analog TBD Frame GND RxDout13N +3.3V Digital RxDout9N Digital GND RxDout5N Digital GND RxDout1N
6 RxReset Reserved FFU TBD Digital GND Reserved FFU Digital GND TBD Digital GND TBD Digital GND
7 TBD TBD Analog GND RxDout14P +3.3V Digital RxDout10P Digital GND RxDout6P Digital GND RxDout2P
8 TBD TBD Analog GND RxDout14N +3.3V Digital RxDout10N Digital GND RxDout6N Digital GND RxDout2N
9 Reserved FFU Reserved FFU TBD Digital GND Reserved FFU Digital GND Reserved FFU Digital GND RxLCKREF Digital GND
10 -5.2V Analog TBD Analog GND RxDout15P +3.3V Digital RxDout11P Digital GND RxDout7P Digital GND RxDout3P
11 -5.2V Analog TBD Analog GND RxDout15N +3.3V Digital RxDout11N Digital GND RxDout7N Digital GND RxDout3N
12 Reserved FFU Reserved FFU TBD Digital GND Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND
13 -5.2V Analog TBD Analog GND TBD -5.2V Digital RxPOCLKP Digital GND Reserved FFU Digital GND RxREFCLKP
14 -5.2V Analog TBD Analog GND TBD -5.2V Digital RxPOCLKN Digital GND Reserved FFU Digital GND RxREFCLKN
15 Reserved FFU Reserved FFU TBD Digital GND Reserved FFU Digital GND Reserved FFU Digital GND RxLCKREF Digital GND
16 -5V Analog TBD Analog GND TxDin12P TBD TxDin8P Digital GND TxDin4P Digital GND TxDin0P
17 -5V Analog TBD Analog GND TxDin12N TBD TxDin8N Digital GND TxDin4N Digital GND TxDin0N
18 Reserved FFU Reserved FFU Reserved FFU Digital GND LsBIASMON Digital GND LsPOWMON Digital GND Reserved FFU Digital GND
19 +3.3V Analog TBD Analog GND TxDin13P TBD TxDin9P Digital GND TxDin5P Digital GND TxDin1P
20 +3.3V Analog TBD Analog GND TxDin13N TBD TxDin9N Digital GND TxDin5N Digital GND TxDin1N
21 Reserved FFU Reserved FFU Reserved FFU Digital GND LsENABLE Digital GND Reserved FFU Digital GND Reserved FFU Digital GND
22 +3.3V Analog TBD Analog GND TxDin14P +3.3V Digital TxDin10P Digital GND TxDin6P Digital GND TxDin2P
23 +3.3V Analog TBD Analog GND TxDin14N +3.3V Digital TxDin10N Digital GND TxDin6N Digital GND TxDin2N
24 TxRESET Reserved FFU Reserved FFU Digital GND LsBIASALM Digital GND Reserved FFU Digital GND Reserved FFU Digital GND
25 -5.2V Analog TBD Frame GND TxDin15P -5.2V Digital TxDin11P Digital GND TxDin7P Digital GND TxDin3P
26 -5.2V Analog TBD Frame GND TxDin15N -5.2V Digital TxDin11N Digital GND TxDin7N Digital GND TxDin3N
27 Reserved FFU Reserved FFU TBD Digital GND LsTEMPALM Digital GND Reserved FFU Digital GND Reserved FFU Digital GND
28 -5.2V Analog TBD Frame GND TxPICLKP -5.2V Digital TxPCLKP Digital GND Reserved FFU Digital GND TxREFCLKP
29 -5.2V Analog TBD Frame GND TxPICLKN -5.2V Digital TxPCLKN Digital GND Reserved FFU Digital GND TxREFCLKN
30 Reserved FFU Reserved FFU TxLINESEL Digital GND TxREFSEL0 Digital GND Reserved FFU Digital GND TxLOCKERR Digital GND
Table B-7. A Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
A1 RxDout0P O LVDS Receiver 622 Mbit/s Data Output LSB
A2 RxDout0N O LVDS Receiver 622 Mbit/s Data Output LSB
B-4 Ixia Hardware Guide
Specifications
A3 Digital GND I Supply Receiver Digital Ground
A4 RxDout1P O LVDS Receiver 622 Mbit/s Data Output
A5 RxDout1N O LVDS Receiver 622 Mbit/s Data Output
A6 Digital GND I Supply Receiver Digital Ground
A7 RxDout2P O LVDS Receiver 622 Mbit/s Data Output
A8 RxDout2N O LVDS Receiver 622 Mbit/s Data Output
A9 Digital GND I Supply Receiver Digital Ground
A10 RxDout3P O LVDS Receiver 622 Mbit/s Data Output
A11 RxDout3N O LVDS Receiver 622 Mbit/s Data Output
A12 Digital GND I Supply Receiver Digital Ground
A13 RxREFCLKP I LVDS Receiver Reference Clock
A14 RxREFCLKN I LVDS Receiver Reference Clock
A15 Digital GND I Supply Receiver Digital Ground
A16 TxDin0P I LVDS Receiver 622 Mbit/s Data Input LSB
A17 TxDin0N I LVDS Receiver 622 Mbit/s Data Input LSB
A18 Digital GND I Supply Receiver Digital Ground
A19 TxDin1P I LVDS Receiver 622 Mbit/s Data Input
A20 TxDin1N I LVDS Receiver 622 Mbit/s Data Input
A21 Digital GND I Supply Receiver Digital Ground
A22 TxDin2P I LVDS Receiver 622 Mbit/s Data Input
A23 TxDin2N I LVDS Receiver 622 Mbit/s Data Input
A24 Digital GND I Supply Receiver Digital Ground
A25 TxDin3P I LVDS Receiver 622 Mbit/s Data Input
A26 TxDin3N I LVDS Receiver 622 Mbit/s Data Input
A27 Digital GND I Supply Receiver Digital Ground
A28 TxREFCLKP I AC Transmitter Reference Clock
A29 TxREFCLKN I AC Transmitter Reference Clock
A30 Digital GND I Supply Transmitter Digital Ground
Table B-7. A Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
Ixia Hardware Guide B-5
SpecificationsB
Table B-8. B Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
B1 Digital GND I Supply Receiver Digital Ground
B2 Digital GND I Supply Receiver Digital Ground
B3 TBD - - To be determined Spare pin
B4 Digital GND I Supply Receiver Digital Ground
B5 Digital GND I Supply Receiver Digital Ground
B6 TBD - - To be determined Spare pin
B7 Digital GND I Supply Receiver Digital Ground
B8 Digital GND I Supply Receiver Digital Ground
B9 RxLCKREF I LVTTL Locks RxPOCLK to RxREFCLK Active low
B10 Digital GND I Supply Receiver Digital Ground
B11 Digital GND I Supply Receiver Digital Ground
B12 Reserved FFU - - Reserved for future use
B13 Digital GND I Supply Receiver Reference Clock
B14 Digital GND I Supply Receiver Reference Clock
B15 RxLCKREF O LVTTL Indicates loss of Rx PLL locks Active low
B16 Digital GND I Supply Transmitter Digital Ground
B17 Digital GND I Supply Transmitter Digital Ground
B18 Reserved FFU - - Reserved for future use
B19 Digital GND I Supply Transmitter Digital Ground
B20 Digital GND I Supply Transmitter Digital Ground
B21 Reserved FFU - - Reserved for future use
B22 Digital GND I Supply Transmitter Digital Ground
B23 Digital GND I Supply Transmitter Digital Ground
B24 Reserved FFU - - Reserved for future use
B25 Digital GND I Supply Transmitter Digital Ground
B26 Digital GND I Supply Transmitter Digital Ground
B27 Reserved FFU - - Reserved for future use
B28 Digital GND I Supply Transmitter Digital Ground
B29 Digital GND I Supply Transmitter Digital Ground
B30 TxLOCKERR O LVTTL Indicates loss of Tx PLL locks Active low
B-6 Ixia Hardware Guide
Specifications
Table B-9. C Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
C1 RxDout4P O LVDS Receiver 622 Mbit/s Data Output
C2 RxDout4N O LVDS Receiver 622 Mbit/s Data Output
C3 Digital GND I Supply Receiver Digital Ground
C4 RxDout5P O LVDS Receiver 622 Mbit/s Data Output
C5 RxDout5N O LVDS Receiver 622 Mbit/s Data Output
C6 Digital GND I Supply Receiver Digital Ground
C7 RxDout6P O LVDS Receiver 622 Mbit/s Data Output
C8 RxDout6N O LVDS Receiver 622 Mbit/s Data Output
C9 Digital GND I Supply Receiver Digital Ground
C10 RxDout7P O LVDS Receiver 622 Mbit/s Data Output
C11 RxDout7N O LVDS Receiver 622 Mbit/s Data Output
C12 Digital GND I Supply Receiver Digital Ground
C13 Reserved FFU - - Reserved for future use
C14 Reserved FFU - - Reserved for future use
C15 Digital GND I Supply Receiver Digital Ground
C16 TxDin4P I LVDS Receiver 622 Mbit/s Data Input
C17 TxDin4N I LVDS Receiver 622 Mbit/s Data Input
C18 Digital GND I Supply Receiver Digital Ground
C19 TxDin5P I LVDS Receiver 622 Mbit/s Data Input
C20 TxDin5N I LVDS Receiver 622 Mbit/s Data Input
C21 Digital GND I Supply Receiver Digital Ground
C22 TxDin6P I LVDS Receiver 622 Mbit/s Data Input
C23 TxDin6N I LVDS Receiver 622 Mbit/s Data Input
C24 Digital GND I Supply Receiver Digital Ground
C25 TxDin7P I LVDS Receiver 622 Mbit/s Data Input
C26 TxDin7N I LVDS Receiver 622 Mbit/s Data Input
C27 Digital GND I Supply Receiver Digital Ground
C28 Reserved FFU - - Reserved for future use
C29 Reserved FFU - - Reserved for future use
C30 Digital GND I Supply Transmitter Digital Ground
Ixia Hardware Guide B-7
SpecificationsB
Table B-10. E Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
E1 RxDout4P O LVDS Receiver 622 Mbit/s Data Output
E2 RxDout4N O LVDS Receiver 622 Mbit/s Data Output
E3 Digital GND I Supply Receiver Digital Ground
E4 RxDout5P O LVDS Receiver 622 Mbit/s Data Output
E5 RxDout5N O LVDS Receiver 622 Mbit/s Data Output
E6 Digital GND I Supply Receiver Digital Ground
E7 RxDout6P O LVDS Receiver 622 Mbit/s Data Output
E8 RxDout6N O LVDS Receiver 622 Mbit/s Data Output
E9 Digital GND I Supply Receiver Digital Ground
E10 RxDout7P O LVDS Receiver 622 Mbit/s Data Output
E11 RxDout7N O LVDS Receiver 622 Mbit/s Data Output
E12 Digital GND I Supply Receiver Digital Ground
E13 Reserved FFU - - Reserved for future use
E14 Reserved FFU - - Reserved for future use
E15 Digital GND I Supply Receiver Digital Ground
E16 TxDin4P I LVDS Receiver 622 Mbit/s Data Input
E17 TxDin4N I LVDS Receiver 622 Mbit/s Data Input
E18 Digital GND I Supply Receiver Digital Ground
E19 TxDin5P I LVDS Receiver 622 Mbit/s Data Input
E20 TxDin5N I LVDS Receiver 622 Mbit/s Data Input
E21 Digital GND I Supply Receiver Digital Ground
E22 TxDin6P I LVDS Receiver 622 Mbit/s Data Input
E23 TxDin6N I LVDS Receiver 622 Mbit/s Data Input
E24 Digital GND I Supply Receiver Digital Ground
E25 TxDin7P I LVDS Receiver 622 Mbit/s Data Input
E26 TxDin7N I LVDS Receiver 622 Mbit/s Data Input
E27 Digital GND I Supply Receiver Digital Ground
E28 Reserved FFU - - Reserved for future use
E29 Reserved FFU - - Reserved for future use
E30 Digital GND I Supply Transmitter Digital Ground
B-8 Ixia Hardware Guide
Specifications
Table B-11. F Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
F1 TBD - - To be determined Spare pin
F2 TBD - - To be determined Spare pin
F3 RxLOPMON O Analog Receive power monitor
F4 +3.3V Digital I Supply Receiver Digital Power
F5 +3.3V Digital I Supply Receiver Digital Power
F6 Reserved FFU - - Reserved for future use
F7 +3.3V Digital I Supply Receiver Digital Power
F8 +3.3V Digital I Supply Receiver Digital Power
F9 Reserved FFU - - Reserved for future use
F10 +3.3V Digital I Supply Receiver Digital Power
F11 +3.3V Digital I Supply Receiver Digital Power
F12 Reserved FFU - - Reserved for future use
F13 -5.2V Digital I Supply Receiver Digital Power
F14 -5.2V Digital I Supply Receiver Digital Power
F15 Reserved FFU - - Reserved for future use
F16 TBD - - To be determined Spare pin
F17 TBD - - To be determined Spare pin
F18 LsBIASMON O Analog Laser bias current monitor
F19 TBD I Supply Transmitter Digital Power
F20 TBD I Supply Transmitter Digital Power
F21 LsENABLE I LVTTL Laser enable (disable is inverse) Active low
F22 +3.3V Digital I Supply Transmitter Digital Power
F23 +3.3V Digital I Supply Transmitter Digital Power
F24 LsBIASALM O LVTTL Laser bias current alarm Active low
F25 -5.2V Digital I Supply Transmitter Digital Power
F26 -5.2V Digital I Supply Transmitter Digital Power
F27 LsTEMPALM O LVTTL Laser temperature alarm Active low
F28 -5.2V Digital I Supply Transmitter Digital Power
F29 -5.2V Digital I Supply Transmitter Digital Power
F30 TxREFSEL0 I LVTTL Selects TxREFCLK Frequency
Ixia Hardware Guide B-9
SpecificationsB
Table B-12. G Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
G1 RxDout12P O LVDS Receiver 622 Mbit/s Data Output
G2 RxDout12N O LVDS Receiver 622 Mbit/s Data Output
G3 Digital GND I Supply Receiver Digital Ground
G4 RxDout13P O LVDS Receiver 622 Mbit/s Data Output
G5 RxDout13N O LVDS Receiver 622 Mbit/s Data Output
G6 Digital GND I Supply Receiver Digital Ground
G7 RxDout14P O LVDS Receiver 622 Mbit/s Data Output
G8 RxDout14N O LVDS Receiver 622 Mbit/s Data Output
G9 Digital GND I Supply Receiver Digital Ground
G10 RxDout15P O LVDS Receiver 622 Mbit/s Data Output MSB
G11 RxDout15N O LVDS Receiver 622 Mbit/s Data Output MSB
G12 Digital GND I Supply Receiver Digital Ground
G13 TBD - - To be determined Spare pin
G14 TBD - - To be determined Spare pin
G15 Digital GND I Supply Receiver Digital Ground
G16 TxDin12P I LVDS Transmitter 622 Mbit/s Data Input
G17 TxDin12N I LVDS Transmitter 622 Mbit/s Data Input
G18 Digital GND I Supply Transmitter Digital Ground
G19 TxDin13P I LVDS Transmitter 622 Mbit/s Data Input
G20 TxDin13N I LVDS Transmitter 622 Mbit/s Data Input
G21 Digital GND I Supply Transmitter Digital Ground
G22 TxDin14P I LVDS Transmitter 622 Mbit/s Data Input
G23 TxDin14N I LVDS Transmitter 622 Mbit/s Data Input
G24 Digital GND I Supply Transmitter Digital Ground
G25 TxDin15P I LVDS Transmitter 622 Mbit/s Data Input MSB
G26 TxDin15N I LVDS Transmitter 622 Mbit/s Data Input MSB
G27 Digital GND I Supply Transmitter Digital Ground
G28 TxPICLKP I LVDS Transmitter parallel input clock
G29 TxPICLKN I LVDS Transmitter parallel input clock
G30 Digital GND I Supply Transmitter Digital Ground
B-10 Ixia Hardware Guide
Specifications
Table B-13. H Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
H1 Frame GND I Supply Receiver Digital Ground
H2 Frame GND I Supply Receiver Digital Ground
H3 TBD - - To be determined Spare pin
H4 Frame GND I Supply Receiver Digital Ground
H5 Frame GND I Supply Receiver Digital Ground
H6 TBD - - To be determined Spare pin
H7 Analog GND I Supply Receiver Digital Ground
H8 Analog GND I Supply Receiver Digital Ground
H9 TBD - - To be determined Spare pin
H10 Analog GND I Supply Receiver Digital Ground
H11 Analog GND I Supply Receiver Digital Ground
H12 TBD - - To be determined Spare pin
H13 Analog GND I Supply Receiver Reference Clock
H14 Analog GND I Supply Receiver Reference Clock
H15 TBD - - To be determined Spare pin
H16 Analog GND I Supply Transmitter Digital Ground
H17 Analog GND I Supply Transmitter Digital Ground
H18 Reserved FFU - - Reserved for future use
H19 Analog GND I Supply Transmitter Digital Ground
H20 Analog GND I Supply Transmitter Digital Ground
H21 Reserved FFU - - Reserved for future use
H22 Analog GND I Supply Transmitter Digital Ground
H23 Analog GND I Supply Transmitter Digital Ground
H24 Reserved FFU - - Reserved for future use
H25 Frame GND I Supply Transmitter Digital Ground
H26 Frame GND I Supply Transmitter Digital Ground
H27 TBD - - To be determined Spare pin
H28 Frame GND I Supply Transmitter Digital Ground
H29 Frame GND I Supply Transmitter Digital Ground
H30 TxLINESEL I LVTTL Selects line timing Active low
Ixia Hardware Guide B-11
SpecificationsB
Table B-14. J Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
J1 TBD - - To be determined Spare pin
J2 TBD - - To be determined Spare pin
J3 Reserved FFU - - Reserved for future use
J4 TBD - - To be determined Spare pin
J5 TBD - - To be determined Spare pin
J6 Reserved FFU - - Reserved for future use
J7 TBD - - To be determined Spare pin
J8 TBD - - To be determined Spare pin
J9 Reserved FFU - - Reserved for future use
J10 TBD - - To be determined Spare pin
J11 TBD - - To be determined Spare pin
J12 Reserved FFU - - Reserved for future use
J13 TBD - - To be determined Spare pin
J14 TBD - - To be determined Spare pin
J15 Reserved FFU - - Reserved for future use
J16 TBD - - To be determined Spare pin
J17 TBD - - To be determined Spare pin
J18 Reserved FFU - - Reserved for future use
J19 TBD - - To be determined Spare pin
J20 TBD - - To be determined Spare pin
J21 Reserved FFU - - Reserved for future use
J22 TBD - - To be determined Spare pin
J23 TBD - - To be determined Spare pin
J24 Reserved FFU - - Reserved for future use
J25 TBD - - To be determined Spare pin
J26 TBD - - To be determined Spare pin
J27 Reserved FFU - - Reserved for future use
J28 TBD - - To be determined Spare pin
J29 TBD - - To be determined Spare pin
J30 Reserved FFU - - Reserved for future use
B-12 Ixia Hardware Guide
Specifications
Table B-15. K Pin Descriptions
Pin # Symbol I/O Logic Description Remarks
K1 +5V Analog I Supply Receiver Analog Power
K2 +5V Analog I Supply Receiver Analog Power
K3 Reserved FFU - - Reserved for future use
K4 +3.3V Analog I Supply Receiver Analog Power
K5 +3.3V Analog I Supply Receiver Analog Power
K6 RxReset I LVTTL Receiver Asynchronous system reset Active low
K7 TBD - - To be determined Spare pin
K8 TBD - - To be determined Spare pin
K9 Reserved FFU - - Reserved for future use
K10 -5.2V Analog I Supply Receiver Digital Power
K11 -5.2V Analog I Supply Receiver Digital Power
K12 Reserved FFU - - Reserved for future use
K13 -5.2V Analog I Supply Receiver Digital Power
K14 -5.2V Analog I Supply Receiver Digital Power
K15 Reserved FFU - - Reserved for future use
K16 -5V Analog I Supply Transmitter Analog Power
K17 -5V Analog I Supply Transmitter Analog Power
K18 Reserved FFU - - Reserved for future use
K19 +3.3V Analog I Supply Transmitter Analog Power
K20 +3.3V Analog I Supply Transmitter Analog Power
K21 Reserved FFU - - Reserved for future use
K22 +3.3V Analog I Supply Transmitter Analog Power
K23 +3.3V Analog I Supply Transmitter Analog Power
K24 TxRESET I LVTTL Transmitter Asynchronous system reset Active low
K25 -5.2V Analog I Supply Transmitter Analog Power
K26 -5.2V Analog I Supply Transmitter Analog Power
K27 Reserved FFU - - Reserved for future use
K28 -5.2V Analog I Supply Transmitter Analog Power
K29 -5.2V Analog I Supply Transmitter Analog Power
K30 Reserved FFU - - Reserved for future use
Ixia Hardware Guide B-13
SpecificationsB
Timing Figure B-2. Timing
B-14 Ixia Hardware Guide
CAppendix C: LM-RMII Interface Specification
DescriptionThe IXIA RMII Test Board can interface with up to 4 RMII channels within one or more RMII PHYs running on the same reference clock. The connector type is from the AMP AMPLIMITE family and is the same type used in the regular MII interface, but with 68 contacts. Except for the reference clock all signals are TTL compatible with safe levels for 3.3V only inputs on the target board under test. The reference clock is an LVDS type, described in more detail below. Except for the reference clock all of the signals use a serial resistor of 51 ohm for termina-tion. No parallel termination is provided for input signals, since it is expected that they should also be driven using serial resistors.
MDC/MDIOThe MDC/MDIO signals operate in the same manner as in a conventional MII PHY. The user designates the PHY addresses present which will be used to com-municate with each of the PHYs. Note that all 4 ports controlled by a single IXIA RMII Test Board must have the same upper 3 PHY address bits, i.e. within a group of 4 PHYs controlled by an IXIA RMII Test Board, the PHY entities are selected with the least significant 2 bits of the PHY address.
The IXIA RMII Test Board recognizes that a transceiver module is attached by a pull up/pull down scheme similar to that specified for the conventional MII. The Test Board has a 24K pull down on the MDIO line and the device under test must have a 1K pull up on that line.
Once a transceiver module is detected, the IXIA RMII Test Board will scan the present PHYs. The PHYs can then be loaded with the desired configuration for that channel. The PHYs will also be continuously polled for link. When link is found, the respective channel transmit section can then be enabled for RMII transmission. The receive channel is always enabled.
Ixia Hardware Guide C-1
ConnectorC
ConnectorIXIA RMII Test Board connector part number (female): AMP 787170-7 AMPLIMITE,.050 Series, 68 pin Mating Connector (male, PCB Mount, Right Angle): AMP 2-174341-5 (Use this only if you plan to plug the target directly into the IXIA RMII Test Board without a cable)
There are three ways to connect the evaluation board to the IXIA RMII Test Board:
1. Using the male connector mentioned above, and plugging the evaluation board directly to the IXIA RMII Test Board without a cable.
2. Using the same female connector used on the IXIA RMII Test Board (or a vertical version of it), with a 1’ male to male cable. This cable is a standard SCSI-3 cable that is available from AMP, part number: 319285-4 (product description: 68 pos. Amplimite .050”, 1’). Figure 1a illustrates the signal positions on this connector.
3. Using the Ixia RMII Adapter Cable that translates the 68 pin Amplimite con-nector to a 38 pin Mictor connector via a very flexible 50 ohm controlled impedance flat cable. The Mictor connector on the cable is of the plug type, thus the board under test must have the Mictor receptacle type. Figure 1b illustrates the signal positions on this connector.
Figure C-1 illustrates the signal positions on the IXIA RMII Test Board connec-tor (the 68 pin Amplimite type). The 4 channels are suffixed 0 through 3 on the RMII signals described in the specification of the RMII consortium.
Notes: 1. There is no standard male to female cable and therefore extending a board
(with a cable) that uses option 1 (male connector) is not easily possible. 2. Good signals have been received from CMOS devices driving the 1’ cable
directly via 33 ohm resistors. These devices were specified to drive only 5ma max DC. However, their dynamic drive capability is unknown to us. We mention this to help our customers decide whether or not to use buffers to drive the cable.
C-2 Ixia Hardware Guide
Connector
Figure C-1. IXIA RMII Test Board Connector Pinout
Ixia Hardware Guide C-3
ExpansionC
Figure C-2. IXIA RMII Mictor Pinout
A board under test can use a 38 pin Receptacle Mictor Connector with this pin assignment.
ExpansionThe IXIA RMII Test Boards can be expanded to support up to 32 PHY’s in a sin-gle evaluation board. This may be done by using several connectors on the evalu-ation board, and connecting them via cables to several adjacent IXIA RMII Test Boards. Via the IxExplorer GUI or TCL API, the PHY addresses for each RMII Test Board may be entered. If the reference clock is to originate from the test equipment, then a single IXIA RMII Test Board designated as board_1 must be
C-4 Ixia Hardware Guide
Power
configured via jumpers as the reference clock source, whereas the other boards must be configured to receive the reference clock. The evaluation board should assign one connector as connector_1, whose function is to receive the clock from board_1 via an LVDS receiver. The output of this LVDS receiver becomes the reference 50MHz clock of the evaluation board. The rest of the connectors must repeat the reference clock via LVDS transmitters using one device per connector.
If the reference clock is to originate from the evaluation board, then each of the RMII connectors must be assigned an LVDS driver to deliver the clock to the respective IXIA RMII Test Board. All the IXIA RMII Test Boards must be con-figured to receive the reference clock.
The MDC signal must originate from only one IXIA RMII Test Board. The sig-nal must not be driven toward other IXIA RMII Test Boards because all the MDC signals in a single IXIA chassis are identical. The MDIO signal should be bussed across all connectors.
PowerFour pins on the connector are tied to MII_PWR, which can supply up to 1 amp of current to the unit under test. The voltage is selectable between 3.3V or 5V by a jumper JP3 as indicated in Table C-1. The front panel LEDs will confirm the selection.
Reference ClockThe 50 MHz reference clock can sourced from either the IXIA RMII Test Board or the DUT. The clock is driven (or received) differentially using an LVDS driver/receiver chip. The recommended part is the National Semiconductor DS92LV010A with a termination resistor of 100 ohm. The same part can either drive or receive. Jumpers JP2 and JP1 control the direction as depicted in Table C-2.
Table C-1. Voltage Selection Jumper Configuration
Desired Voltage JP3 Configuration
5 volts Jumper pins 1 & 2
3.3 volts Jumper pins 2 & 3
Table C-2. Selection of Reference Clock Source
Reference Clock Source
JP2 Configuration JP1 Configuration
IXIA RMII Test Board Open Jumper pins 1 & 2
Device Under Test Closed (jumpered) Jumper pins 3 & 2
Ixia Hardware Guide C-5
Timing ConsiderationsC
Timing ConsiderationsFigure C-3 shows the timing for outgoing data under typical delay conditions. The diagram assumes that the IXIA RMII Test Board clocks data on the falling edge of the clock, which can be selected via the IxExplorer GUI or TCL API. As the diagram indicates, a setup of 8ns and a hold time of 12ns is provided under these typical circumstances. If these delays are grossly different in a particular system, the edge which clocks outgoing data may be changed.
A very similar scenario occurs with the receive data clocked out of the PHY board. If the user suspects that there may be a setup/hold violation on the RMII Test Board, the user may change the other clock edge to clock incoming data.
In summary, the IXIA Explorer GUI will allow the user to alter the clock edge for incoming and outgoing data independently, so that any clock and data delay combinations can be made to work.
The timing diagram shows outgoing data with respect to clock. It is assumed the outgoing data in the RMII Test Board is clocked on the falling edge of the clock as can be selected via the GUI. The 50MHz_PHY clock is shown 180 degrees out of phase because it is assumed that it undergoes a typical delay of 10ns via the transmit and receive LVDS devices as well as the cable.
Figure C-3. Timing Diagram
C-6 Ixia Hardware Guide
DAppendix D: XAUI Connector Specifications
DescriptionThe following cable and accessories for the 10GE XAUI cards are described in this appendix. These include:
• Standard Connector Specifications–the signals carried on the Load Module’s XAUI connector.
• Front Panel Loopback Connector–a connector used to loopback XAUI sig-nals at the external connector.
• Standard Cable Specification–the CAB10GE500S1 (20”) and CAB10GE500S2 (40”) cables.
• SMA Break-Out Box–the BOB10GE500 SMA break-out box.
• XAUI Fujitsu to XENPAK Adapter–an adapter used with Ixia XENPAK load modules to create a XAUI interface.
• XAUI Tyco Interoperability Backplane HM-Zd Adapter–an adapter used to connect to the Tyco Interoperability Backplane.
Standard Connector SpecificationsThe Ixia XAUI Load Module’s front panel connector is the Fujitsu MicroGiGa. This connector can be mounted on the Device Under Test (DUT), eliminating the need for SMA cables. This part is also available directly from Fujitsu as part number FCN-268D008-G/1D-/2D.The connector is shown in Figure D-1.The signal names, functional description and connector pin assignments are as shown in Table D-1.
Ixia Hardware Guide D-1
Standard Connector SpecificationsD
Figure D-1. Fujitsu MicroGiGa Connector
Figure D-2 shows how the pins are physically arranged within the connector. The connector is specifically designed for high-speed differential signals on 100 ohm twisted pairs. Also shown is a cross section of the cable.
Table D-1. XAUI Connector Pin Assignment
Pin No. Signal Name Functional Description
S1 P1_RX_LANE0_P Lane-A, positive receive input
S2 P1_RX_LANE0_N Lane-A, negative receive input
S3 P1_RX_LANE1_P Lane-B, positive receive input
S4 P1_RX_LANE1_N Lane-B, negative receive input
S5 P1_RX_LANE2_P Lane-C, positive receive input
S6 P1_RX_LANE2_N Lane-C, negative receive input
S7 P1_RX_LANE3_P Lane-D, positive receive input
S8 P1_RX_LANE3_N Lane-D, negative receive input
S9 P1_RX_LANE3_P Lane-D, positive transmit output
S10 P1_RX_LANE3_N Lane-D, negative transmit output
S11 P1_RX_LANE2_P Lane-C, positive transmit output
S12 P1_RX_LANE2_N Lane-C, negative transmit output
S13 P1_RX_LANE1_P Lane-B, positive transmit output
S14 P1_RX_LANE1_N Lane-B, negative transmit output
S15 P1_RX_LANE0_P Lane-A, positive transmit output
S16 P1_RX_LANE0_N Lane-A, negative transmit output
G1-G9 GND Shield (Ground)
D-2 Ixia Hardware Guide
Front Panel Loopback Connector
Figure D-2. XAUI Connector Contact Details and Cable Cross Section
Front Panel Loopback ConnectorIn order to verify that the Ixia XAUI Load Module is operational a loopback con-nector may be used to test external loopback on the front panel. The user can remove the connector by pulling back on the blue handle, releasing the connec-tion to the Fujitsu MicroGiGa connector. The loopback connector (Ixia P/N LPG10GE500) is shown in Figure D-3.
Figure D-3. XAUI Front Panel Loopback Connector
Standard Cable SpecificationThe same connector and pin assignments used on the Load Module can also be used on the Device Under Test (DUT). Ixia supplies a 20-inch cross-pinned cable assembly (CAB10GE500S1) that allows a straight connection as shown in Figure D-5. This cable can also be used for loopback testing on an Ixia chassis equipped with two or more XAUI ports. Longer cable assemblies can be made on request, but it is not recommended that the cable length exceed 2 meters, because losses and skew may become unacceptable. Ixia makes a 40” cable available as part number CAB10GE500S2. The 40” cable is shown in Figure D-4.
Ixia Hardware Guide D-3
SMA Break-Out BoxD
Figure D-4. Ixia XAUI Cable (CAB10GE500S2)
Figure D-5. Direct XAUI Interface using Ixia supplied cable
SMA Break-Out Box
If the DUT uses coaxial connectors for the XAUI interface, a special break-out box (BOB10GE500) is required in addition to the XAUI cable, as shown in Figure D-6. The user must provide the sixteen 50-ohm coaxial cables with a male SMA connector on the end that mates to the BOB. The actual break-out box is shown in Figure D-6.
NOTE: The 50cm max. length suggested in the XAUI section of 802.3ae is a rough guideline for keeping the losses on PCB traces under 7.5dB. Well designed cables will usually have much lower losses per meter than PCB traces, so cables can be much longer than 50cm.
Ixia LoadModule
UserDevice
XAUI Port XAUI Port
XAUI 20" Cable
D-4 Ixia Hardware Guide
SMA Break-Out Box
Figure D-6. XAUI SMA Break-Out Box
Figure D-7. XAUI SMA Break-Out Box
When using coaxial cables for the XAUI interface, extreme care should be taken to match the electrical lengths of the two cables in each pair. The pairs can be of different lengths, since the XAUI SerDes should automatically correct for skew between lanes. Skew between the “P” and “N” lines within a pair, however, can introduce bit errors. The XAUI edge-rates can be as short as 60ps. Therefore, the total in-pair skew should be kept below 30ps to avoid bit-errors. Some of this in-pair skew must be budgeted to the Load Module, Ixia XAUI cable, BOB, and the DUT. Allocating 10ps of in-pair skew to the coax cables would require length matching them to within about 0.08” (for RG-174). The propagation velocity of
Ixia LoadModule
XAUI Port
XAUI 20" Cable
XAUI/SMABreak-out box
PNTX Lane-A
PNRX Lane-A
PNTX Lane-B
PNTX Lane-C
PNRX Lane-C
PNTX Lane-D
PNRX Lane-D
PNRX Lane-B
Ixia Hardware Guide D-5
XAUI Fujitsu to XENPAK AdapterD
coax can vary slightly between manufacturers, lots, and as it is bent or stretched. Therefore, it is recommended that coax cables be kept as short as possible.
XAUI Fujitsu to XENPAK AdapterThe electrical interface to XENPAK is XAUI, which uses an industry standard 70-pin connector. Ixia’s XAUI Load Module, however, uses a Fujitsu Micro-GiGa connector to both transmit and receive four XAUI lanes via eight twisted pairs through a 20” cable. Ixia offers an adapter (part number FXN10GE500) which routes the XAUI lanes from the Fujitsu connector to the pins on the XEN-PAK connector.
This enables a XENPAK Load Module to act as a XAUI Load Module. How-ever, the XENPAK Load Module can only run in Ethernet mode and transmit and verify layer 2 or 3 traffic. Further, there is no D-sub connector for MDIO on the front panel of the XENPAK Load Module. Both the MDIO and power are avail-able through pins on the adapter and serve the same function as the D-sub con-nector on the XAUI Load Module.
The adapter is shown in Figure D-8.
Figure D-8. Fujitsu to XENPAK Adapter
Table D-2. XAUI Electrical Interface Performance
Parameter Characteristic
TxOutputs
Impedance 100 ohm balanced differential, AC coupled.
Amplitude 1.2Vpp minimum (with 0 pre-emphasis)
Pre-emphasis Software selectable (0, 10%, 20% or 30%)
Jitter 0.35 UI max. (UI is Unit Interval = 320ps nominal).
RxInputs
Impedance 100 ohm differential, AC coupled.
Amplitude 0.2 to 2.3 Vpp.
Jitter tolerance 0.55 UI.
70-pin connectorMDIO Pins
Fujitsu Connector
D-6 Ixia Hardware Guide
XAUI Tyco Interoperability Backplane HM-Zd Adapter
XAUI Tyco Interoperability Backplane HM-Zd AdapterXAUI interoperability testing has been conducted using a Tyco built simulated backplane. Each XAUI vendor has been required to build a line card to connect to the backplane via the Tyco HM-Zd connector. Tyco had also built an SMA adapter to connect to the backplane, but it is too time-consuming and difficult to connect via SMAs. Ixia has built an HM-Zd adapter (P/N FTY10GE500), which allows direct connection to the backplane via the Fujitsu connector, saving sig-nificant setup time. This is shown in Figure D-9.
Figure D-9. Tyco Interoperability Backplane HM-Zd Adapter
Ixia Hardware Guide D-7
XAUI Tyco Interoperability Backplane HM-Zd AdapterD
D-8 Ixia Hardware Guide
EAppendix E: Available Statistics
This appendix covers the available statistics for the different card types:
• Statistics for 10/100 Cards and Ethernet/USB Cards in Ethernet Mode. These cards include:
• 10/100
• 10/100 MII
• 10/100 Reduced MII
• 100 Base FX MultiMode
• 100 Base FX SingleMode
• Ethernet/USB operating in Ethernet mode
• Copper 10/100/1000 running at 10/100 Mbps
• Statistics for 10/100 TXS Modules. These cards include:
• 10/100 TXS8
• Statistics for 10/100/1000 TXS and 1000 SFPS4 Cards. These cards include:
• 10/100/1000 TXS4
• 1000 SFPS4
• Statistics for Ethernet/USB cards in USB Mode. These cards include:
• Ethernet/USB
• Statistics for Gigabit Modules. These cards include:
• 1000 Base SX MultiMode
• 1000 Base LX MultiMode
• 1000 Base SX SingleMode
• GBIC
• Statistics for OC12c/OC3c Modules. These cards include:
• OC12c/OC3c
• Statistics for OC48c Modules with Bert. These cards include:
Ixia Hardware Guide E-1
Table OrganizationE
• OC48c POS
• OC48 POS VAR
• OC48c BERT
• OC48c BERT Rx
• OC48c POS/BERT
• Statistics for OC192c Modules with Bert. These cards include:
• OC192c with optional BERT and 10 Gigabit Ethernet.
• OC192c VSR. Note that all VSR cards have available all of the VSR statis-tics listed in the VSR section of Table E-6 on page E-8.
• Statistics for 10GE Modules with BERT. These cards include:
• 10 Gigabit Ethernet with optional BERT.
• Statistics for Protocol Server. These statistics are common to all cards which support the Protocol Server.
Table OrganizationEach of the following tables details the statistics available for that set of cards. Available statistics are controlled by three sets of controls:
IxExplorer Statistics Modes
From the Explorer tree, select a port and select Filter, Statistics, Receive Mode from the right-hand panel. Select the tab at the top labelled Statistics. This is shown below for a Gigabit module with the statistics modes highlighted in a solid
E-2 Ixia Hardware Guide
Table Organization
box. The choices here are mutually exclusive. In most cases, when one is selected new statistics are available at the expense of others.
Figure E-1. Statistics Mode Selection
Extra Statistics Checkboxes
Additional statistics are selected through a set of checkboxes located on the same Statistics tab, as highlighted in a dashed line. These statistics are always in addi-tion to those in the Statistics Mode box.
Receive Mode
From the Explorer tree, select a port and select Filter, Statistics, Receive Mode from the right-hand panel. Select the tab at the top labelled Receive Mode. This is shown below for a Gigabit module. Not all of the receive modes necessarily result in additional statistics. For example, in the figure below First Time Stamp
Statistics Mode
Extra Statistics Checkboxes
Ixia Hardware Guide E-3
Table OrganizationE
and ISL Encapsulation do not affect statistics. Otherwise, the checkboxes gener-ally result in additional statistics.
Figure E-2. Receive Mode Selection
Key To Tables
Table E-1 lists the headings that appear in the tables in this appendix and their correspondence to IxExplorer dialogs and selections.Table E-1.Key for Statistics Table
Heading Item IxExplorer Dialog IxExplorer Label
Statistics Mode
UDS 5&6 Statistics User Defined Statistics 5 and 6
QoS Statistics Quality of Service
Normal Statistics Normal
Checksum Errors Statistics IP / TCP / UDP Checksum Verification
Data Integrity Statistics Data Integrity
Extra Statistics Checkboxes
Protocol Server Statistics Protocol Server Stats
ARP STATS Statistics ARP Stats
ICMP STATS Statistics ICMP Stats
BGP STATS Statistics BGP Stats
OSPF STATS Statistics OSPF Stats
ISIS STATS Statistics ISIS Stats
RSVP-TE STATS Statistics RSVP-TE Stats
E-4 Ixia Hardware Guide
Table Organization
TCL Development Statistics Mode
The statistics mode is controlled by the use of the stat mode command. Figure E-1 on page E-3 lists the available choices and their correspondence to IxExplorer choices and the labels used in the tables in this appendix.
Access to Statistics
Most statistics are accessed through the use of stat command. VSR statistics are access through the use of the vsrStat command.
Receive Mode
The receive mode is controlled through the use of the port receiveMode option. The choices available are or’d together. list the bits available to control the receive mode.
LDP STATS Statistics LDP Stats
USB Ext Statistics USB Extended Stats
POS Ext Statistics POS Extended Stats
Temp Sensors Statistics Temperature Sensor Stats
Receive Mode
Rx Capture Receive Mode Capture
Rx Seq Checking Receive Mode Sequence Checking
Rx Data Integrity Receive Mode Data Integrity
Table E-1.Key for Statistics Table
Heading Item IxExplorer Dialog IxExplorer Label
Table E-2.Tcl stat mode Options
Option IxExplorer Choice
statNormal (0) (default) Normal
statQos (1) Quality of Service
statStreamTrigger (2) User Defined Statistics 5 and 6
statModeChecksumErrors (3) IP / TCP / UDP Checksum Verification
statModeDataIntegrity (4) Data Integrity
Table E-3.Tcl port receive Options
Option IxExplorer Choice
portCapture (1) Capture
portPacketGroup (2) Packet Groups
Ixia Hardware Guide E-5
Table OrganizationE
C++ Development Statistics Mode
The statistics mode is controlled by the use of the stat.mode member. Table E-1 on page E-3 lists the available choices and their correspondence to IxExplorer choices and the labels used in the tables in this appendix.
Access to Statistics
Most statistics are accessed through the use of TCLStatistics class. VSR statis-tics are access through the use of the TCLvsrStat class.
Receive Mode
The receive mode is controlled through the use of the port.receiveMode mem-ber. The choices available are or’d together. list the bits available to control the receive mode.
portRxTcpSessions (4) Does not affect statistics.
portRxTcpRoundTrip (8) Does not affect statistics.
portRxDataIntegrity (16) Data Integrity
portRxFirstTimeStamp (32) Does not affect statistics.
portRxSequenceChecking (64) Sequence Checking
portRxModeBert (128) BERT Mode
portRxModeBertChannelized (128) Channelized BERT Mode
Table E-3.Tcl port receive Options
Option IxExplorer Choice
Table E-4.C++ stat Members
Member Value IxExplorer Choice
statNormal (0) (default) Normal
statQos (1) Quality of Service
statStreamTrigger (2) User Defined Statistics 5 and 6
statModeChecksumErrors (3) IP / TCP / UDP Checksum Verification
statModeDataIntegrity (4) Data Integrity
Table E-5.Tcl port receive Options
Member Value IxExplorer Choice
portCapture (1) Capture
portPacketGroup (2) Packet Gropus
portRxTcpSessions (4) Does not affect statistics.
portRxTcpRoundTrip (8) Does not affect statistics.
E-6 Ixia Hardware Guide
Ixia Hardw
are Guide
E-7
Description of Statistics
those statistics.The following three col-
d by general category, as used in the
and C++ API. The base name is used to
e name needed to fetch a particular sta- the first letter of the statistic. For exam-rs.
needed to fetch a particular statistic is st letter of the statistic. For example, for
Description of StatisticsTable E-6 on page E-8 lists all of the available statistics, along with an explanation ofumns are used:
• Counter – the name of the statistics as it appears in IxExplorer. These are organizeremaining tables in this appendix.
• Interpretation – the description of the statistics.
• Internal Baseame – the internal basename used to describe the statistics in the TCLform other names:
• TCL stat command options – the basename is the name of the option.
• TCL stat command get sub-command counterType argument – the counterTyptistic is formed by prepending the letters stat to the basename, while capitalizingple, for basename alignmentErrors, the counterType name is statAlignmentErro
• C++ stat class members – the basename is the name of the member.
• C++ stat command get method counterType argument – the counterType nameformed by prepending the letters stat to the basename, while capitalizing the firbasename alignmentErrors, the counterType name is statAlignmentErrors.
.
portRxDataIntegrity (16) Data Integrity
portRxFirstTimeStamp (32) Does not affect statistics.
portRxSequenceChecking (64) Sequence Checking
portRxModeBert (128) BERT Mode
portRxModeBertChannelized (128) Channelized BERT Mode
Table E-5.Tcl port receive Options
Member Value IxExplorer Choice
Description of Statistics
E-8Ixia H
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Internal Basename
e user- userDefinedStat1userDefinedStat2
met, as captureTrigger
et, as captureFilter
e user-A to OC192
streamTrigger1streamTrigger2
he port has ice. (See
link
POS lineSpeed
note 7 in duplexMode
stat .
transmitState
stat .
captureState
tat .
pauseState
d - this framesSent
Table E-6.Statistics Counters
Counter Interpretation
User Configurable
User Defined Stats 1 and 2 & Rate Counters that increment each time the statistics conditions are met. Thdefined statistics conditions are set up in the Capture Filter window.
Capture Trigger (UDS3) & Rate A counter that increments each time the capture trigger conditions are defined in the Capture Filter window.
Capture Filter (UDS4) & Rate A counter that increments each time the capture filter conditions are mdefined in the Capture Filter window.
User Defined Stats 5 and 6 & Rate Counters that increment each time the statistics conditions are met. Thdefined statistics conditions are set up in the Capture Filter window. (N/modules.)
States
Link State “Up” when a link is established with another device, “Loopback” when tloopback enabled, “Down” when there is no connection to another devnote 2 in Notes)
Line Speed “10”, “100”, or “1000” (denoting Mbps) and OC-12, OC-3 or OC-48 for modules. (See note 6 in Notes)
Duplex Mode “Half” or “Full”. Half duplex only applies to 10/100 Load Modules. (SeeNotes)
Transmit State Not shown in IxExplorer. The current transmit state of the port. See thecommand in the Tcl Development Guide and C++ Development Guide
Capture State Not shown in IxExplorer. The current capture state of the port. See thecommand in the Tcl Development Guide and C++ Development Guide
Pause State Not shown in IxExplorer. The current pause state of the port. See the scommand in the Tcl Development Guide and C++ Development Guide
Common
Frames Sent & Rate A counter that increments only when a frame is successfully transmittecounter does not count collision attempts.
Ixia Hardw
are Guide
E-9
Description of Statistics
V sive of unter an
framesReceived
B bytesSent
B bytesReceived
T
T transmitDuration
Q
Q g is qualityOfService0qualityOfService1...
F
F framerFCSErrors
F framerAbort
F framerMinLength
F framerMaxLength
E
F framerFramesTx
F framerFramesRx
C
I ipPackets
U udpPackets
T
C Internal Basename
alid Frames Received & Rate The valid frame size is from 64 bytes to 1518 bytes inclusive of FCS, exclupreamble and SFD and must be an integer number of octets. This 32 bit coonly counts frames with good FCS. VLAN tagged frames that are greater th1518 but less than 1522 bytes in size will also be counted by this counter.
ytes Sent & Rate A counter that counts the total number of bytes transmitted.
ytes Received & Rate A counter that counts the total number of bytes received.
ransmit Duration
ransmit Duration Reserved for future use
uality of Service
uality of Service 0 - 7 & Rate Counters which increment each time a frame with that particular QoS settinreceived. (N/A to OC192-3)
ramer Stats
ramer CRC Errors CRC errors detected by the POS framer.
ramer Abort POS frames aborted by the Framer.
ramer Min Length & Rate POS frames received with less than the minimum length.
ramer Max Length & Rate POS frames received with more than the maximum length.
xtended Framer Stats
ramer Frames Sent Reserved for future use.
ramer Frames Received Reserved for future use.
hecksum Stats
P Packets Received The number of IP packets received.
DP Packets Received The number of UDP packets received.
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-10Ixia H
ardware G
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tcpPackets
ipChecksumErrors
udpChecksumErrors
tcpChecksumErrors
dataIntegrityFrames
dataIntegrityErrors
sequenceFrames
sequenceErrors
evious egative, or number.
smallSequenceErrors
evious bigSequenceErrors
he previous reverseSequenceErrors
totalSequenceErrors
protocolServerTx
protocolServerRx
txArpReply
Internal Basename
TCP Packets Received The number of TCP packets received.
IP Checksum Errors The number of IP checksum errors detected..
UDP Checksum Errors The number of UDP checksum errors detected.
TCP Checksum Errors The number of TCP checksum errors detected.
Data Integrity
Data Integrity Frames The number of data integrity frames received.
Data Integrity Errors The number of data integrity errors detected.
Sequence Checking
Sequence Frames The number of sequence checking frames received.
Sequence Errors The number of sequence checking errors detected.
Small Sequence Errors The number of times when the current sequence number minus the prsequence number is less than or equal to the error threshold and not nwhen the current sequence number is equal to the previous sequence
Big Sequence Errors The number of times when the current sequence number minus the prsequence number is greater than the error threshold.
Reverse Sequence Errors The number of times when the current sequence number is less than tsequence number.
Total Sequence Errors The sum of the small, bug and reverse sequence errors.
Protocol Server Stats
General
Protocol Server Transmit Packets transmitted by the protocol handler.
Protocol Server Receive Packets received by the protocol handler.
Transmit Arp Reply Number of ARP replies generated.
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-11
Description of Statistics
T txArpRequest
T txPingReply
T txPingRequest
R rxArpReply
R rxArpRequest
R rxPingReply
R rxPingRequest
V protocolServerVlanDroppedFrames
A asynchronousFramesSent
S scheduledFramesSent
P ream portCPUFramesSent
B
B bgpTotalSessions
B bgpTotalSessionsEstablished
I
I isisSessionsConfiguredL1
I isisSessionsConfiguredL2
I isisSessionsUpL1
I isisSessionsUpL2
T
C Internal Basename
ransmit Arp Request Number of ARP requests generated.
ransmit Ping Reply Number of Ping replies generated. (N/A to OC192-3)
ransmit Ping Request Number of Ping requests received. (N/A to OC192-3)
eceive Arp Reply Number of ARP replies received.
eceive Arp Request Number of ARP requests received.
eceive Ping Reply Number of Ping replies received. (N/A to OC192-3)
eceive Ping Request Number of Ping requests generated. (N/A to OC192-3)
LAN Dropped Frames The number of VLAN frames dropped by the Protocol Server.
synchronous Frames Sent The number of frames sent as a result of user request
cheduled Frames Sent The number of frames origination from the stream engine.
ort CPU Frames Sent The number of frames originating from the port’s CPU as opposed to the stengine.
GP
GP Sessions Configured The number of BGP4 sessions that were configured.
GP Sessions Established The number of configured BGP4 sessions that established adjacencies.
SIS
SIS L1 Sessions Configured The total number of level 1 configured sessions.
SIS L2 Sessions Configured The total number of level 2 configured sessions.
SIS L1 Sessions Up The total number of level 1 configured sessions that are fully up.
SIS L2 Sessions Up The total number of level 2 configured sessions that are fully up.
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-12Ixia H
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ospfTotalSessions
ospfFullNeighbors
rsvpIngressLSPsConfigured
rsvpIngressLSPsUp
rsvpEgressLSPsUp
ldpSessionsConfigured
rs ldpSessionsUp
ldpBasicSessionsUp
with a bad fragments
with a good undersize
size. The s: 10/100 de oversize
oversize
fcsErrors
vlanTaggedFramesReceived
bit) symbol symbolErrors
Internal Basename
OSPF
OSPF Total Sessions The number of OSPF sessions that were configured.
OSPF Neighbors in Full State The number of OSPF neighbors that are fully up.
RSVP
RSVP Ingress LSPs Configured The number of ingress LSPs configured.
RSVP Ingress LSPs Up The number of ingress LSPs configured and running
RSVP Egress LSPs Up The number of egress LSPs configured and running
LDP
LDP Sessions Configured The number of LDP sessions configured for targeted peers
LDP Sessions Up The number of LDP sessions configured and running with targeted pee
LDP Basic Sessions Up The number of LDP sessions up for broadcast peers
Ethernet
Fragments & Rate A counter that counts the number of frames less than 64 bytes in size FCS.
Undersize & Rate A counter that counts the number of frames less than 64 bytes in size FCS.
Oversize & Rate A counter that counts the number of frames greater than 1518 bytes infollowing modules count oversize packets with both good and bad FCSTX, 10/100 MII, 10/100 RMII and Ethernet/USB. All other modules inclupackets with a good FCSs only.
CRC Errors & Rate A counter that counts all valid size frames that have CRC errors.
Vlan Tagged Frames & Rate A counter that counts the number of VLAN tagged frames.
Line Errors & Rate A counter that counts the number of 4B/5B (100Mbps) or 8B/10B (Gigaerrors.
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-13
Description of Statistics
F only rties
flowControlFrames
1
A bits en the ent
alignmentErrors
D bits the bit
dribbleErrors
C ) of the collisions
L ble lateCollisions
C d due collisionFrames
ut had excessiveCollisionFrames
G
O with a oversizeAndCrcErrors
L rrors. symbolErrorFrames
B ted to synchErrorFrames
P
T
C Internal Basename
low Control Frames & Rate A counter that counts the number of PAUSE frames received. This counter increments when Flow Control is enabled for that port (using the port propedialog).
0/100
lignment Errors & Rate A counter that counts all valid size frames that are not an even multiple of 8and have an invalid FCS. The frame is truncated to the nearest octet and thFCS is validated. If the FCS is bad, then this frame is counted as an alignmerror.
ribble Errors & Rate A counter that counts all valid size frames that are not an even multiple of 8and have a valid FCS. The frame is truncated to the nearest octet and thenFCS is validated. If the FCS is good, then this frame is counted as a dribbleerror.
ollisions & Rate A counter that counts all occurrences (only one count per frame or fragmentCollision Detect signal from the physical layer controller.
ate Collisions & Rate A counter that counts all collisions that occur after the 512th bit time (preamincluded) or after the 56th byte.
ollision Frames & Rate A counter that counts the number of frames received that were retransmitteto one or more collisions.
Excessive Collision Frames & Rate A counter that counts the number of frames that were attempted to be sent b16 or more consecutive collisions.
igabit
versize and CRC Errors & Rate A counter that counts the number of frames greater than 1518 bytes in sizebad FCS.
ine Error Frames & Rate A counter that counts the number of frames received that contain symbol e
yte Alignment Error & Rate A counter that counts the number of times that a comma character is detecbe out of alignment.
OS
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-14Ixia H
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sectionLossOfSignal
sectionLossOfFrame
sectionBip
ote 3 in lineAis
es) lineRdi
lineRei
lineBip
note 3 in pathAis
Notes) pathRdi
pathRei
pathBip
es) pathLossOfPointer
el byte. te 5 in
pathPlm
second) at sectionBipErroredSecs
r BIP errors sectionBipSeverlyErroredSecs
second) at sectionLossOfSignalSecs
t least one lineBipErroredSecs
Internal Basename
Section LOS “OK” or “ALARM” during loss of signal. (See note 3 in Notes)
Section LOF “OK” or “ALARM” during loss of frame. (See note 3 in Notes)
Section BIP(B1) & Rate The number of section bit interleaved parity errors.
Line AIS “OK” or “ALARM” during a line alarm indication signal condition. (See nNotes)
Line RDI “OK” or “ALARM” during a remote defect indication. (See note 3 in Not
Line REI(FEBE) & Rate A count of the number of remote error indicate conditions.
Line BIP(B2) & Rate The number of line bit interleaved parity errors.
Path AIS “OK” or “ALARM” during a path alarm indication signal condition. (See Notes)
Path RDI “OK” or “ALARM” during a path remote defect indication. (See note 3 in
Path REI(FEBE) & Rate A count of the number of path remote error indicate conditions
Path BIP(B3) & Rate The number of path bit interleaved parity errors.
Path LOP “OK” or “ALARM” during a loss of pointer condition. (See note 3 in Not
Path PLM(C2) Either “OK” or “ALARM” along with the current received path signal lab“ALARM” will occur when a path signal label mismatch occurs. (See noNotes)
Section BIP Errored Seconds A count of the number of seconds during which (at any point during theleast one section layer BIP was detected.
Section BIP Severely Errored Seconds A count of the number of seconds during which K or more Section layewere detected, where K = 2,392 for OC-48 (per ANSI T1.231-1997).
Section LOS Seconds A count of the number of seconds during which (at any point during theleast one section layer LOS defect was present.
Line BIP Errored Seconds A count of the seconds during which (at any point during the second) aLine layer BIP was detected.
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-15
Description of Statistics
L by the lineReiErroredSecs
L st one lineAisAlarmSecs
L e far lineRdiUnavailableSec
P st one pathBipErroredSecs
P st one pathReiErroredSecs
P defect pathAisAlarmSec
P ble. pathAisUnavailableSecs
P ble at pathRdiUnavailableSec
I Notes) inputSignalStrength
P posK1byte
P posK2byte
S
S srpDataFramesReceived
S srpDiscoveryFramesReceived
S srpIpsFramesReceived
S des all srpParityErrors
T
C Internal Basename
ine REI Errored Seconds A count of the seconds during which at least one line BIP error was reportedfar end.
ine AIS Alarmed Seconds A count of the seconds during which (at any point during the second) at leaLine layer AIS defect was present.
ine RDI Unavailable Seconds A count of the seconds during which the line is considered unavailable at thend.
ath BIP Errored Seconds A count of the seconds during which (at any point during the second) at leaPath BIP error was detected.
ath REI Errored Seconds A count of the seconds during which (at any point during the second) at leaSTS Path error was reported by the far end.
ath AIS Alarmed Seconds A count of the seconds during which (at any point during the second) an AISwas present)
ath AIS Unavailable Seconds A count of the seconds during which the STS path was considered unavaila
ath RDI Unavailable Seconds A count of the seconds during which the STS path was considered unavailathe far end.
nput Signal Strength (dB) (OC-192) This stat monitors the receive optical input power. (See note 8 in
OS K1 Byte Monitors the k1 status byte in Sonet Headers.
OS K2 Byte Monitors the k1 status byte in Sonet Headers.
RP
RP Data Frames Received The number of data frames received. IPv4 frames fall in this category.
RP Discovery Frames Received The number of discovery type frames received.
RP IPS Frames Received The number of IPS type frames received.
RP Header Parity Errors The number of SRP frames received with SRP header parity error. This incluframe types.
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-16Ixia H
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ity and only mes,
ived but not
srpUsageFramesReceived
the link srpUsageFramesSent
ld, this srpUsageStatus
eriod. srpUsageTimeouts
interface bertStatus
bertBitsSent
bertBitsReceived
bertBitErrorsSent
bertBitErrorsReceived
he total bertBitErrorRatio
nd. bertErroredBlocks
ock or a bertErroredSeconds
ds. bertErroredSecondRatio
blocks or a bertSeverelyErroredSeconds
e total bertSeverelyErroredSecondsRatio
Internal Basename
SRP Usage Frames Received The umber of usage frames received with good CRC, good header parthose that match the MAC address set for the SRP’s port. Bad CRC fraframes with header errors or those with other MAC addresses are rececounted.
SRP Usage Frames Sent The number of usage frames sent.These are sent periodically to keep alive.
SRP Usage Status If the number of consecutive timeouts exceeds the Keep Alive threshostatus changes to FAIL. Otherwise shows OK.
SRP Usage Timeouts The number of times a usage frame was not received within the time p
BERT
Status For BERT - The status of the connection. “Locked” when the receiving locks onto the data pattern. (See note 1 in Notes)
Bits Sent For BERT - the total number of bits sent.
Bits Received For BERT - the total number of bits received.
Bit Errors Sent For BERT - the total number of bit errors sent.
Bit Errors Received For BERT - the total number of bit errors received.
Bit Error Ratio For BERT - (BER) the ratio of the number of errored bits compared to tnumber of bits transmitted.
Errored Blocks For BERT- (EB) Number of blocks containing at least one errored seco
Errored Seconds For BERT - (ES) Number of seconds containing at least one errored bldefect.
Errored Second Ratio For BERT - (ESR) the ratio of Errored Seconds (ES) to the total secon
Severely Errored Seconds For BERT - (SES) Number of seconds with 30% or more of the erroreddefect.
Severely Errored Second Ratio For BERT - (SESR) the ratio of Severely Errored Seconds (SESs) to thseconds in available time.
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-17
Description of Statistics
E bertErrorFreeSeconds
A bertAvailableSeconds
U able bertUnavailableSeconds
B o the . of 10 A min. . (See
bertBlockErrorState
B bertBackgroundBlockErrors
B l bertBackgroundBlockErrorRatio
E bertElapsedTestTime
N bertNumberMismatchedZeros
M bertismatchedZerosRatio
N bertNumberMismatchedOnes
bertMismatchedOnesRatio
U bertUnframedDetectedLineRate
U
S lable
L onds. bertLastServiceDisruptionTime
T
C Internal Basename
rror Free Seconds For BERT - (EFS) Number of seconds with no errored blocks or defects.
vailable Seconds For BERT - (AS) Number of seconds which have occurred during AvailablePeriods.
navailable Seconds For BERT - (UAS) Number of seconds which have occurred during UnavailPeriods.
lock Error State For BERT - Available Period or Unavailable Period, determined according trunning count and calculation of seconds in various error conditions. A minnon-SESs must pass for the state to change from Unavailable to Available.of 10 SESs must pass for the state to change from Available to Unavailablenote 4 in Notes)
ackground Block Errors For BERT - (BBE) The number of errored blocks not occurring as part of a Severely Errored Second.
ackground Block Error Ratio For BERT - (BBER) the ratio of Background Block Errors (BBEs) to the totanumber of blocks in available time.
lapsed Test Time For BERT - the elapsed test time, expressed in seconds.
umber Mismatched Zeros The number of expected zeroes received as ones.
ismatched Zeros Ratio The ratio of the number of expected zeroes received as ones to all bits.
umber Mismatched Ones The number of expected ones received as zeroes.
Mismatched Ones Ratio The ratio of the number of expected ones received as zeroes to all bits.
nframed Bert Detected Line Rate. For unframed BERT - the detected line rate, in bps.
nframed Bert Output Signal Strength For unframed BERT - the output signal strength, in db.
ervice Disruption A service disruption is the period of time during which the service is unavaiwhile switching rings. The SONET spec calls for this to be less than 50 ms.
ast Service Disruption Time (ms) The length of the last service disruption that occurred, expressed in millisec
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-18Ixia H
ardware G
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s. bertMinServiceDisruptionTime
. bertMaxServiceDisruptionTime
s. bertServiceDisruptionCumulative
dccBytesReceived
dccBytesSent
dccCrcErrorsReceived
dccFramesReceived
dccFramesSent
dccFramingErrorsReceived
dMATemperature
ip. captureTemperature
p. latencyTemperature
chip. backgroundTemperature
p. overlayTemperature
hip. frontEndTemperature
hip. scheduleTemperature
Internal Basename
Min Service Disruption Time (ms) The shortest service disruption that occurred, expressed in millisecond
Max Service Disruption Time (ms) The longest service disruption that occurred, expressed in milliseconds
Cumulative Service Disruption Time (ms)
The total service disruption time encountered, expressed in millisecond
DCC
DCC Bytes Received The number of DCC bytes received.
DCC Bytes Sent The number of DCC bytes sent.
DCC CRC Receive Errors The number of DCC CRC errors received.
DCC Frames Received The number of DCC frames received.
DCC Frames Sent The number of DCC frames sent.
DCC Framing Errors Received The number of DCC framing errors received.
OC192
Temperature
DMA Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the DMA chip.
Capture Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the Capture ch
Latency Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the Latency chi
Background Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the Background
Overlay Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the Overlay chi
Front End Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the Front End C
Scheduler Chip Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature of the Scheduler C
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-19
Description of Statistics
P plmDevice1InternalTemperature
P plmDevice2InternalTemperature
P plmDevice3InternalTemperature
F on the fobPort1FpgaTemperaturefobPort2FpgaTemperature
F on the fobBoardTemperature
F on the fobDevice1InternalTemperature
V annel
R rxChannelProtectionDisabled8
R rxChannelSkewError8
R ace. If st
rxChannelSkewFirst8
R e. If st
rxChannelSkewLast8
R than rxChannelSkewMax8
R rxChannelSwapped8
T
C Internal Basename
lm Internal Chip Temperature 1 (C) (OC-192 - Temperature Sensors Stats) Internal temperature of temperaturemeasuring device #1.
lm Internal Chip Temperature 2 (C) (OC-192 - Temperature Sensors Stats) Internal temperature of temperaturemeasuring device #2.
lm Internal Chip Temperature 3(C) (OC-192 - Temperature Sensors Stats) Internal temperature of temperaturemeasuring device #3.
om Port Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature for one of the sensors Fiber optic module (Fom).
om Board Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature for one of the sensors Fiber optic module (Fom).
om Internal Temperature (C) (OC-192 - Temperature Sensors Stats) Temperature for one of the sensors Fiber optic module (Fom).
SR The statistics in this sub-section relate to all VSR channels. See VSR per Chstatistics below for further per-channel statistics.
x Channel Protection Disabled The status of the channel protection on the receiving interface.
x Channel Skew Error The status of the channel skew error detection on the receiving interface.
X Channel Skew First The channel number of the earliest channel to arrive on the receiving interfmore than one channel arrives at the same time, Channel #1 has the highepriority and so on.
x Channel Skew Last The channel number of the latest channel to arrive on the receiving interfacmore than one channel arrives at the same time, Channel #1 has the highepriority, and so on.
x Channel Skew Max This counter increments every time the channel skew is equal to or greaterthe maximum channel skew.
x Channel Swapped Indicates one or more channel swap errors.
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-20Ixia H
ardware G
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rxCodeWordViolationError8
g interface. rxCrcCorrectedErrorCounter8
rxCrcCorrectionDisabled8
rxCrcError8
iving rxCrcUnCorrectedErrorCounter8
rxHardwareError8
s of rxLossOfSynchronizationCounter8
els were in rxMultiLossOfSynchronizationCounter8
of rxMultiLossOfSynchronizationStatus8
rxOutOfFrameCounter8
rxOutOfFrameStatus8
rxSectionBipErrorCounter8
txHardwareError8
txOutOfFrameCounter8
txOutOfFrameStatus8
een txSectionBipErrorCounter8
Internal Basename
Rx Code Word Violation Error Indicates one or more 8b/10b code word violation errors.
Rx CRC Corrected Errors The number of corrected CRC block errors accumulated on the receivin
Rx CRC Correction Disabled Indicates the status of the CRC correction on the receiving interface.
Rx CRC Error Indicates one or more detected CRC errors.
Rx CRC Uncorrected Errors The number of uncorrected CRC block errors accumulated on the receinterface.
Rx Hardware Error The number of hardware errors detected on the receive side.
Rx Loss Of Synchronization Counter Indicates the number of times that a protection channels was in the lossynchronization state.
Rx Multi-loss Of Synchronization Counter
Indicates the number of times that two or more data or protection channthe Loss of Synchronization state.
Rx Multi-loss Of Synchronization Status Indicates that two or more data or protection channels are in the Loss Synchronization state.
Rx Out of Frame Counter Indicates the number of frame errors for the receiving interface.
Rx Out of Frame Status Indicates one or more out of frame errors for the receiving interface.
Rx Section BIP Error Counter The number of Section BIP errors detected on the receiving interface.
Tx Hardware Error Counter The number of hardware errors detected on the transmit side.
Tx Out Of Frame Counter The number of out of frame errors detected on the transmit side.
Tx Out of Frame Status Indicates one or more out of frame errors for the transmit interface
Tx Section BIP Error Counter The number of Section Bit Interleaved Parity (BIP) errors which have bdetected on the transmit interface.
VSR per Channel The statistics in this sub-section relate to a specific VSR channel.
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-21
Description of Statistics
R ted on ity
rxCodeWordViolationCounter9
R errors rxCrcErrorCounter9
R rxLossOfSynchronization9
R terface rxOutOfFrame9
U
T usbTxNoError
R usbRxNoError
R error. usbRxCRCError
R ffing usbRxBitStuffing
R ved did usbRxToggleMismatch
T usbTxStall
R usbRxStall
T to the usbTxDeviceNotResponding
R nt by usbRxDeviceNotResponding
T usbTxPIDCheckFail
T
C Internal Basename
x Code Word Violation Counter This per-channel statistic indicates the number of codeword violations detecthe receiving channel interface. Codeword violations include running disparerrors, undefined codewords, and any control characters besides K28.5.
x CRC Error Counter This per-channel statistic indicates the number of corrected and uncorrectedon the receive interface.
x Loss Of Synchronization Status This per-channel statistic indicates the loss of synchronization status of thereceiving interface.
x OUt of Frame Status This per-channel statistic indicates the out of frame status of the receiving infor a particular channel.
SB
ransmit NO Error (For USB Extended Stats) Data packets sent with no errors.
eceive NO Error (For USB Extended Stats) Data packets received with no errors.
eceive CRC Error (For USB Extended Stats) The last data packet received contained a CRC
eceive Bit Stuffing (For USB Extended Stats) The last data packet received contained a bit stuviolation.
eceive Data Toggle Mismatch (For USB Extended Stats) The data toggle PID for the last data packet receinot match the expected value.
ransmit Stall (For USB Extended Stats) Transmitted a Stall PID.
eceive Stall (For USB Extended Stats) Received a Stall PID.
ransmit Device Not Responding (For USB Extended Stats) The transmit device did not provide a handshakereceive device.
eceive Device Not Responding (For USB Extended Stats) The receive device did not respond to a token sethe transmit device.
ransmit PID Check Failure (For USB Extended Stats) Check bits in the PID from the endpoint failed onhandshake.
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-22Ixia H
ardware G
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d on data usbRxPIDCheckFail
value. usbTxUnexpectedPID
alue. usbRxUnexpectedPID
size of: usbRxDataOverrun
et size, so usbRxdataUnderrun
n be written usbRxbufferOverrun
m system usbTxBufferUnderrun
is placed in usbTxNotAccessed
is placed in usbRxNotAccessed
pauseAcknowledge
pauseEndFrames
quanta not pauseOverwrite
Internal Basename
Receive PID Check Failure (For USB Extended Stats) Check bits in the PID from the endpoint failePID.
Transmit Unexpected PID (For USB Extended Stats) Transmitted an invalid PID or undefined PID
Receive Unexpected PID (For USB Extended Stats) Received an invalid PID or undefined PID v
Receive Data Overrun (For USB Extended Stats) The amount of data returned exceeded the • maximum data packet allowed, or• remaining amount of memory in the buffer
Receive Data Underrun (For USB Extended Stats) The endpoint sent less than maximum packthe specified buffer is not filled.
Receive Buffer Overrun (For USB Extended Stats) Receiving port receives data faster than it cato system memory.
Transmit Buffer Underrun (For USB Extended Stats) During transmission, cannot retrieve data fromemory and send out fast enough to keep up with the USB data rate.
Transmit Not Accessed (For USB Extended Stats) This code is set by software before the RUT a queue for processing.
Receive Not Accessed (For USB Extended Stats) This code is set by software before the RUT a queue for processing.
10 Gig
Pause Frame
Pause Acknowledge The number of clocks for which transmit has been paused.
Pause End Frames The number of pause frames received with a quanta of 0.
Pause Overwrite The number of pause frames received while transmit was paused with aequal to 0
Temperature
Table E-6.Statistics Counters
Counter Interpretation
Ixia Hardw
are Guide
E-23
Description of Statistics
L 10GigLanTxFpgaTemperature
L 10GigLanRxFpgaTemperature
T
C Internal Basename
an Transmit FPGA Temperature For the 10Gig LAN board, the temperature at the transmit FPGA.
an Receive FPGA Temperature For the 10Gig LAN board, the temperature at the receive FPGA.
able E-6.Statistics Counters
ounter Interpretation
Description of Statistics
E-24Ixia H
ardware G
uide
E
NotesTable E-7.Notes for Statistics Counters
Note Choices displayed for Statistic
1 Locked - All Ones
Locked - Inverted Alternating One/Zero
Locked - Inverted User Defined Pattern
Locked - Inverted 2^31 Linear Feedback Shift Reg
Locked - Inverted 2^11 Linear Feedback Shift Reg
Locked - Inverted 2^15 Linear Feedback Shift Reg
Locked - Inverted 2^20 Linear Feedback Shift Reg
Locked - Inverted 2^23 Linear Feedback Shift Reg
Locked - All Zero
Locked - Alternating One/Zero
Locked - User Defined Pattern
Locked - 2^11 Linear Feedback Shift Reg
Locked - 2^15 Linear Feedback Shift Reg
Locked - 2^20 Linear Feedback Shift Reg
Locked - 2^23 Linear Feedback Shift Reg
Not Locked
2 Demo Mode
Link Up
Link Down
Loopback
WriteMii
Ixia Hardw
are Guide
E-25
Description of Statistics
Restart AutoNegotiate
End RestartAutoNegotiate
AutoNegotiate
WriteMii Failed
No Transceiver
Invalid PHY Address
Read LinkPartner
No LinkPartner
FPGA Download Failed
No GBIC Module
Fifo Reset
Fifo Reset Compete
PPP Off
PPP Up
PPP Down
PPP Init
PPP WaitForOpen
PPP AutoNegotiate
PPP Close
PPP Connect
Loss of Frame
Table E-7.Notes for Statistics Counters
Note Choices displayed for Statistic
Description of Statistics
E-26Ixia H
ardware G
uide
E
Loss of Signal
StateMachine Failure
PPP RestartNegotiation
PPP RestartNegotiation Init
PPP RestartNegotiation WaitForOpen
PPP RestartNegotiation WaitForClose
PPP RestartNegotiation Finish
LP Boot Failed
PPP Disabled - LOF
Ignore Link
Temperature Alarm
PPP Closing
PPP LCP Negotiate
PPP Authenticate
PPP NCP Negotiate
3 OK
Alarm
“-”
Defect
4 Unavailable Period
Available Period
Table E-7.Notes for Statistics Counters
Note Choices displayed for Statistic
Ixia Hardw
are Guide
E-27
Description of Statistics
5 OK
OK (%)
Alarm (%)
“-”
6 OC-3c
OC-12c
OC-48c
OC-192c
10GE WAN
10 Mbps
100 Mbps
1000 Mbps
7 Full
Half
8 Loss of Signal
[-] %d.%d
8 The statistics in this section must be accessed using the vsrStat command in TCL and the TCLvsrStat class in C++.
9 The statistics in this section must be accessed using the vsrStat command in TCL and the TCLvsrStat class in C++. In addition, the desired channel must be set with the getChannel sub-command (TCL) or method (C++).
Table E-7.Notes for Statistics Counters
Note Choices displayed for Statistic
Description of Statistics
E-28Ixia H
ardware G
uide
E
rnet ModeStream Trigger
Pack
etG
roup
RxT
cpR
ound
Trip
RxF
irstT
imeS
tam
p
X X XX X X
XX
X X XX X XX X XX X XX X XX X X
X X XX X XX X XX X XX X X
X X
Table E-8.Statistics for 10/100 Cards and Ethernet/USB Cards in EtheNormal Qos
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxF
irstT
imeS
tam
p
Cap
ture
Cap
ture
Type: User ConfigurableUserDefinedStat1 X X X X XUserDefinedStat2 X X X X XCaptureTrigger X X XCaptureFilter X X XStreamTrigger1 XStreamTrigger2 XType: StatesLink X X X X X XLineSpeed X X X X X XDuplexMode X X X X X XTransmitState X X X X X XCaptureState X X X X X XPauseState X X X X X XType: CommonFramesSent X X X X X XFramesReceived X X X X X XBytesSent X X X X X XBytesReceived X X X X XFcsErrors X X X X X XType: Transmit DurationTransmitDuration X X X X X
Ixia Hardw
are Guide
E-29
Description of Statistics
X X XX X XX X X
XX X X
X X XX X XX X XX X XX X XX X X
ModeStream Trigger
Pack
etG
roup
RxT
cpR
ound
Trip
RxF
irstT
imeS
tam
p
Type: Quality of ServiceQualityOfService0 XType: EthernetFragments X X X X X XUndersize X X X X X XOversize X X X X X XVlanTaggedFramesRx X XFlowControlFrames X X X X X XType: 10/100AlignmentErrors X X X X X XDribbleErrors X X X X XCollisions X X X X X XLateCollisions X X X X X XCollisionFrames X X X X X XExcessiveCollisionFrames X X X X X XType: 10/100 + GigabitSymbolErrors XOversizeAndCrcErrors
Table E-8.Statistics for 10/100 Cards and Ethernet/USB Cards in EthernetNormal Qos
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxF
irstT
imeS
tam
p
Cap
ture
Cap
ture
Description of Statistics
E-30Ixia H
ardware G
uide
E
tream Trigger Mode DataIntegrity
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
X X X X X X X XX X X X X X X XX X XX X X
X X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X X
X X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X X
Table E-9.Statistics for 10/100 TXS ModulesNormal Qos S
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
Type: User ConfigurableUserDefinedStat1 X X X X X X X XUserDefinedStat2 X X X X X X X XCaptureTrigger X X X X XCaptureFilter X X X X XStreamTrigger1 X XStreamTrigger2 X XType: StatesLink X X X X X X X X X XLineSpeed X X X X X X X X X XDuplexMode X X X X X X X X X XTransmitState X X X X X X X X X XCaptureState X X X X X X X X X XPauseState X X X X X X X X X XType: CommonFramesSent X X X X X X X X X XFramesReceived X X X X X X X X X XBytesSent X X X X X X X X X XBytesReceived X X X X X X X XFcsErrors X X X X X X X X X X
Ixia Hardw
are Guide
E-31
Description of Statistics
X
X XX X
XX
X X X X X X XX X X X X X XX X X X X X X
X X XX X X X
XX X X X X X XX X X X X X XX X X X X X X
m Trigger Mode DataIntegrity
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Type: Transmit DurationTransmitDuration XType: Quality of ServiceQualityOfService0 X XType: Data IntegrityDataIntegrityFrames XDataIntegrityErrors XType: Sequence CheckingSequenceFramesSequenceErrorsType: EthernetFragments X X X X X X X X X X XUndersize X X X X X X X X X X XOversize X X X X X X X X X X XVlanTaggedFramesRx X X X X XFlowControlFrames X X X X X X X X X XType: 10/100AlignmentErrors X X XDribbleErrors X X X X X X X X X X XCollisions X X X X X X X X X X XLateCollisions X X X X X X X X X X X
Table E-9.Statistics for 10/100 TXS ModulesNormal Qos Strea
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
Description of Statistics
E-32Ixia H
ardware G
uide
E
X X X X X X X XX X X X X X X X
X X X X X X
tream Trigger Mode DataIntegrity
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
CollisionFrames X X X X X X X X X XExcessiveCollisionFrames X X X X X X X X X XType: 10/100 + GigabitSymbolErrorsOversizeAndCrcErrors X X X X X X X X
Table E-9.Statistics for 10/100 TXS ModulesNormal Qos S
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
Ixia Hardw
are Guide
E-33
Description of Statistics
m Trigger Mode Data Integrity
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
X X X X X X XX X X X X X X
X XX X
X XX X
X X X X X X XX X X X X X XX X X X X X XX X X X X X XX X X X X X XX X X X X X X
X X X X X X XX X X X X X XX X X X X X XX X X X X X XX X X X X X X
Table E-10.Statistics for 10/100/1000 TXS and 1000 SFPS4 CardsNormal Qos Strea
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
Type: User ConfigurableUserDefinedStat1 X X X X X X X X XUserDefinedStat2 X X X X X X X X XCaptureTrigger X X X X X XCaptureFilter X X X X X XStreamTrigger1 X XStreamTrigger2 X XType: StatesLink X X X X X X X X X X XLineSpeed X X X X X X X X X X XDuplexMode X X X X X X X X X X XTransmitState X X X X X X X X X X XCaptureState X X X X X X X X X X XPauseState X X X X X X X X X X XType: CommonFramesSent X X X X X X X X X X XFramesReceived X X X X X X X X X X XBytesSent X X X X X X X X X X XBytesReceived X X X X X X X X XFcsErrors X X X X X X X X X X X
Description of Statistics
E-34Ixia H
ardware G
uide
E
X X X X X X X
XX
XX
X X X X X X X XX X X X X X X XX X X X X X X XXX X X X
X XX X X X X X X XX X X X X X X XX X X X X X X X
tream Trigger Mode Data Integrity
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Type: Transmit DurationTransmitDuration X X X X X X X X XType: Quality of ServiceQualityOfService0 X XType: Data IntegrityDataIntegrityFramesDataIntegrityErrorsType: Sequence CheckingSequenceFramesSequenceErrorsType: EthernetFragments X X X X X X X X X XUndersize X X X X X X X X X XOversize X X X X X X X X X XVlanTaggedFramesRx X X X X XFlowControlFrames X X X X X X X X X XType: 10/100AlignmentErrors X XDribbleErrors X X X X X X X X X XCollisions X X X X X X X X X XLateCollisions X X X X X X X X X X
Table E-10.Statistics for 10/100/1000 TXS and 1000 SFPS4 CardsNormal Qos S
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
Ixia Hardw
are Guide
E-35
Description of Statistics
X X X X X X XX X X X X X X
X X X X X X
m Trigger Mode Data Integrity
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
CollisionFrames X X X X X X X X X X XExcessiveCollisionFrames X X X X X X X X X X XType: 10/100 + GigabitSymbolErrorsOversizeAndCrcErrors X X X X X X X X
Table E-10.Statistics for 10/100/1000 TXS and 1000 SFPS4 CardsNormal Qos Strea
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
Description of Statistics
E-36Ixia H
ardware G
uide
E
sum Mode Data Integrity Additional Modes
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Usb
Exte
nded
Stat
s
X X X X X XX X X X X XX X XX X X
X X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X X
X X X X X XX X X X X XX X X X X XX X X X X XX X X X X X
Table E-11.Statistics for Ethernet/USB cards in USB ModeNormal Qos Stream Trigger Mode Check
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
Type: User ConfigurableUserDefinedStat1 X X X X X X X X X X X X X X X XUserDefinedStat2 X X X X X X X X X X X X X X XCaptureTrigger X X X X X X X X XCaptureFilter X X X X X X X X XStreamTrigger1 XStreamTrigger2 XType: StatesLink X X X X X X X X X X X X X X X X X XLineSpeed X X X X X X X X X X X X X X X X X XDuplexMode X X X X X X X X X X X X X X X X X XTransmitState X X X X X X X X X X X X X X X X X XCaptureState X X X X X X X X X X X X X X X X X XPauseState X X X X X X X X X X X X X X X X X XType: CommonFramesSent X X X X X X X X X X X X X X X X X XFramesReceived X X X X X X X X X X X X X X X X X XBytesSent X X X X X X X X X X X X X X X X X XBytesReceived X X X X X X X X X X X X X X X XFcsErrors X X X X X X X X X X X X X
Ixia Hardw
are Guide
E-37
Description of Statistics
TT X X X X X XTQTIUTIUTTD XD XTS X XS X XTF X X X X X XU X X X X X XO X X X X X X
T Mode Data Integrity Additional
Modes
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Usb
Exte
nded
Stat
s
ype: Transmit DurationransmitDuration X X X X X X X X X X X X X X X Xype: Quality of ServiceualityOfService0 X Xype: Checksum StatspPackets XdpPackets XcpPackets XpChecksumErrors XdpChecksumErrors XcpChecksumErrors Xype: Data IntegrityataIntegrityFrames X X XataIntegrityErrors X X Xype: Sequence CheckingequenceFrames X XequenceErrors X Xype: Ethernetragments X X X X X X X X X X X X Xndersize X X X X X X X X X X X X Xversize X X X X X X X X X X X X X
able E-11.Statistics for Ethernet/USB cards in USB ModeNormal Qos Stream Trigger Mode Checksum
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
Description of Statistics
E-38Ixia H
ardware G
uide
E
X X XX X X
X X X X X XX X X
X X XX X X X X X
XXXXXX
sum Mode Data Integrity Additional Modes
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Usb
Exte
nded
Stat
s
VlanTaggedFramesRx X X X X X XFlowControlFrames X X X X X X XType: 10/100AlignmentErrors X XDribbleErrors X X XCollisions X X XLateCollisions X X XCollisionFrames X X XExcessiveCollisionFrames X X XType: GigabitSymbolErrorFrames X X X X X X X X XSynchErrorFrames X X X XType: 10/100 + GigabitSymbolErrors X X X XOversizeAndCrcErrors X X X X X X X X X X XType: USBUsbTxNoErrorUsbRxNoErrorUsbRxCRCErrorUsbRxBitStuffingUsbRxToggleMismatchUsbTxStall
Table E-11.Statistics for Ethernet/USB cards in USB ModeNormal Qos Stream Trigger Mode Check
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
Ixia Hardw
are Guide
E-39
Description of Statistics
U XU XU XU XU XU XU XU XU XU XU XU XU X
T Mode Data Integrity Additional
Modes
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Usb
Exte
nded
Stat
s
sbRxStallsbTxDeviceNotRespondingsbRxDeviceNotRespondingsbTxPIDCheckFailsbRxPIDCheckFailsbTxUnexpectedPIDsbRxUnexpectedPIDsbRxDataOverrunsbRxdataUnderrunsbRxBufferOverrunsbTxBufferUnderrunsbTxNotAccessedsbRxNotAccessed
able E-11.Statistics for Ethernet/USB cards in USB ModeNormal Qos Stream Trigger Mode Checksum
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
Description of Statistics
E-40Ixia H
ardware G
uide
E
hecksumErrors Mode Data Integrity
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
X X X X X X X XX X X X X X X XX X X XX X X X
X X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X X
X X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X X
Table E-12.Statistics for Gigabit ModulesNormal Qos Stream Trigger ModeC
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Type: User ConfigurableUserDefinedStat1 X X X X X X X X X X X X X XUserDefinedStat2 X X X X X X X X X X X X XCaptureTrigger X X X X X X X XCaptureFilter X X X X X X X XStreamTrigger1 XStreamTrigger2 XType: StatesLink X X X X X X X X X X X X X X X XLineSpeed X X X X X X X X X X X X X X X XDuplexMode X X X X X X X X X X X X X X X XTransmitState X X X X X X X X X X X X X X X XCaptureState X X X X X X X X X X X X X X X XPauseState X X X X X X X X X X X X X X X XType: CommonFramesSent X X X X X X X X X X X X X X X XFramesReceived X X X X X X X X X X X X X X X XBytesSent X X X X X X X X X X X X X X X XBytesReceived X X X X X X X X X X X X X XFcsErrors X X X X X X X X X X X X X X X XType: Transmit Duration
Ixia Hardw
are Guide
E-41
Description of Statistics
T X X X X X X XTQTIUTIUTTD XD XTCS X XS X XTF X X X X X X XU X X X X X X XO X X X X X X XV X X X X
TsumErrors Mode Data Integrity
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
ransmitDuration X X X X X X X X X X X X X X Xype: Quality of ServiceualityOfService0 X Xype: Checksum StatspPackets XdpPackets XcpPackets XpChecksumErrors XdpChecksumErrors XcpChecksumErrors Xype: Data IntegrityataIntegrityFrames X X XataIntegrityErrors X X Xype: Sequence heckingequenceFrames X XequenceErrors X Xype: Ethernetragments X X X X X X X X X X X X X X X X Xndersize X X X X X X X X X X X X X X X X Xversize X X X X X X X X X X X X X X X X XlanTaggedFramesRx X X X X X X X X
able E-12.Statistics for Gigabit ModulesNormal Qos Stream Trigger ModeCheck
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Description of Statistics
E-42Ixia H
ardware G
uide
E
X X X X
X X X X X X X XX X X X
X X X XX X X X X X X X
hecksumErrors Mode Data Integrity
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
FlowControlFrames X X X X X X X X X X XType: 10/100AlignmentErrors X XDribbleErrors X X XCollisions X X XLateCollisions X X XCollisionFrames X X XExcessiveCollisionFrames X X XType: GigabitSymbolErrorFrames X X X X X X X X X X XSynchErrorFrames X X X X X X X XType: 10/100 + GigabitSymbolErrors X X X X X XOversizeAndCrcErrors X X X X X X X X X X X X X X
Table E-12.Statistics for Gigabit ModulesNormal Qos Stream Trigger ModeC
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Ixia Hardw
are Guide
E-43
Description of Statistics
Tm Mode Data Integrity Add’l
Modes
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
PosE
xten
dedS
tats
TU X X X X X XU X X X X X XC XC XSSTL X X X X X XL X X X X X XD X X X X X XT X X X X X XC X X X X X XP X X X X X XTF X X X X X XF X X X X X XB X X X X X XB X X X X X XF X X X X X X
able E-13.Statistics for OC12c/OC3c ModulesNormal Qos Stream Trigger Mode Checksu
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
ype: User ConfigurableserDefinedStat1 X X X X X X X X X X X X X X X XserDefinedStat2 X X X X X X X X X X X X X X XaptureTrigger X X X X XaptureFilter X X X X XtreamTrigger1 X XtreamTrigger2 X Xype: Statesink X X X X X X X X X X X X X X X X X XineSpeed X X X X X X X X X X X X X X X X X XuplexMode X X X X X X X X X X X X X X X X X XransmitState X X X X X X X X X X X X X X X X X XaptureState X X X X X X X X X X X X X X X X X XauseState X X X X X X X X X X X X X X X X X Xype: CommonramesSent X X X X X X X X X X X X X X X X X XramesReceived X X X X X X X X X X X X X X X X X XytesSent X X X X X X X X X X X X X X X X X XytesReceived X X X X X X X X X X X X X X X XcsErrors X X X X X X X X X X X X X X X X X X
Description of Statistics
E-44Ixia H
ardware G
uide
E
X X X X X X X
XXX
XX
X XX X
cksum Mode Data Integrity Add’l Modes
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
PosE
xten
dedS
tats
Type: Transmit DurationTransmitDuration X X X X X X X X X X X X X X XType: Quality of ServiceQualityOfService0 X XType: FramerFramerFCSErrorsFramerAbortFramerMinLengthFramerMaxLengthType: Checksum StatsIpPackets XUdpPackets XTcpPackets XIpChecksumErrors XUdpChecksumErrors XTcpChecksumErrors XType: Data IntegrityDataIntegrityFrames X X XDataIntegrityErrors X X XType: Sequence CheckingSequenceFrames X XSequenceErrors X X
Table E-13.Statistics for OC12c/OC3c ModulesNormal Qos Stream Trigger Mode Che
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Ixia Hardw
are Guide
E-45
Description of Statistics
TF XU XO XV XF XTADCLCETS XS XTS XO XTS X
Tm Mode Data Integrity Add’l
Modes
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
PosE
xten
dedS
tats
ype: Ethernetragments X X X X Xndersize X X X X Xversize X X X X XlanTaggedFramesRx X X X X XlowControlFrames X X X X Xype: 10/100lignmentErrors X XribbleErrors X Xollisions X XateCollisions X XollisionFrames X XxcessiveCollisionFrames X Xype: GigabitymbolErrorFrames X X XynchErrorFrames X X Xype: 10/100 + GigabitymbolErrors X X XversizeAndCrcErrors X X Xype: POSectionLossOfSignal
able E-13.Statistics for OC12c/OC3c ModulesNormal Qos Stream Trigger Mode Checksu
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
Description of Statistics
E-46Ixia H
ardware G
uide
E
XXXXXXXXXXXX
cksum Mode Data Integrity Add’l Modes
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
PosE
xten
dedS
tats
SectionLossOfFrameSectionBipLineAisLineRdiLineReiLineBipPathAisPathRdiPathReiPathBipPathLossOfPointerPathPlmSectionBipErroredSecsSectionBipSeverlyErroredSecsSectionLossOfSignalSecsLineBipErroredSecsLineReiErroredSecsLineAisAlarmSecsLineRdiUnavailableSecsPathBipErroredSecsPathReiErroredSecsPathAisAlarmSecs
Table E-13.Statistics for OC12c/OC3c ModulesNormal Qos Stream Trigger Mode Che
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Ixia Hardw
are Guide
E-47
Description of Statistics
PPIPP
Tm Mode Data Integrity Add’l
Modes
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
PosE
xten
dedS
tats
athAisUnavailableSecsathRdiUnavailableSecs
nputSignalStrengthosK1ByteosK2Byte
able E-13.Statistics for OC12c/OC3c ModulesNormal Qos Stream Trigger Mode Checksu
Errors
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
p
RxS
eque
nceC
heck
ing
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
Description of Statistics
E-48Ixia H
ardware G
uide
E
ModeDataIntegrity Add’l Modes
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
X X X X X XX X X X X X
XX
XX
X X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X X
X X X X X XX X X X X XX X X X X XX X X X X XX X X X X X
Table E-14.Statistics for OC48c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Type: User ConfigurableUserDefinedStat1 X X X X X X X X XUserDefinedStat2 X X X X X X X X XCaptureTrigger X XCaptureFilter X XStreamTrigger1 X X XStreamTrigger2 X X XType: StatesLink X X X X X X X X X X X X XLineSpeed X X X X X X X X X X X X XDuplexMode X X X X X X X X X X X X XTransmitState X X X X X X X X X X X X XCaptureState X X X X X X X X X X X X XPauseState X X X X X X X X X X X X XType: CommonFramesSent X X X X X X X X X X X X XFramesReceived X X X X X X X X X X X X XBytesSent X X X X X X X X X X X X XBytesReceived X X X X X X X X XFcsErrors X X X X X X X X X X X X X
Ixia Hardw
are Guide
E-49
Description of Statistics
TT X X X X XTQTD XD XTS XS XTS XS XS XL XL XL XL XP XP XP X
TModeDataIntegrity Add’l
Modes
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
ype: Transmit DurationransmitDuration X X X X X X X X X X X X X Xype: Quality of ServiceualityOfService0 X X X Xype: Data IntegrityataIntegrityFrames X XataIntegrityErrors X Xype:Sequence CheckingequenceFrames X X XequenceErrors X X Xype: POSectionLossOfSignalectionLossOfFrameectionBipineAisineRdiineReiineBipathAisathRdiathRei
able E-14.Statistics for OC48c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Description of Statistics
E-50Ixia H
ardware G
uide
E
XXX
X X X X X XX X X X X X
X X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X X
X X X X X XX X X X X X
ModeDataIntegrity Add’l Modes
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
PathBipPathLossOfPointerPathPlmSectionBipErroredSecs X X X X X X X X X X X X XSectionBipSeverlyErroredSecs
X X X X X X X X X X X X X
SectionLossOfSignalSecs X X X X X X X X X X X X XLineBipErroredSecs X X X X X X X X X X X X XLineReiErroredSecs X X X X X X X X X X X X XLineAisAlarmSecs X X X X X X X X X X X X XLineRdiUnavailableSecs X X X X X X X X X X X X XPathBipErroredSecs X X X X X X X X X X X X XPathReiErroredSecs X X X X X X X X X X X X XPathAisAlarmSecs X X X X X X X X X X X X XPathAisUnavailableSecs X X X X X X X X X X X X XPathRdiUnavailableSecs X X X X X X X X X X X X XInputSignalStrengthPosK1BytePosK2ByteSrpDataFramesReceived X X X X X X X X X X X X XSrpDiscoveryFramesReceived
X X X X X X X X X X X X X
Table E-14.Statistics for OC48c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Ixia Hardw
are Guide
E-51
Description of Statistics
S X X X X XS X X X X XS X X X X XS X X X X XS X X X X X
TModeDataIntegrity Add’l
Modes
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
rpIpsFramesReceived X X X X X X X X X X X X X XrpParityErrors X X X X X X X X X X X X X XrpUsageFramesReceived X X X X X X X X X X X X X XrpUsageStatus X X X X X X X X X X X X X XrpUsageTimeouts X X X X X X X X X X X X X X
able E-14.Statistics for OC48c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Description of Statistics
E-52Ixia H
ardware G
uide
E
ModeDataIntegrity Add’l Modes
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
Tem
pera
ture
Sens
orsS
tats
X X X X X XX X X X X X
XX
XX
X X X X X XX X X X X XX X X X X XX X X X X XX X X X X XX X X X X X
X X X X X XX X X X X XX X X X X XX X X X X X
Table E-15.Statistics for OC192c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Type: User ConfigurableUserDefinedStat1 X X X X X X X X XUserDefinedStat2 X X X X X X X X XCaptureTrigger X XCaptureFilter X XStreamTrigger1 X X XStreamTrigger2 X X XType: StatesLink X X X X X X X X X X X X XLineSpeed X X X X X X X X X X X X XDuplexMode X X X X X X X X X X X X XTransmitState X X X X X X X X X X X X XCaptureState X X X X X X X X X X X X XPauseState X X X X X X X X X X X X XType: CommonFramesSent X X X X X X X X X X X X XFramesReceived X X X X X X X X X X X X XBytesSent X X X X X X X X X X X X XBytesReceived X X X X X X X X X
Ixia Hardw
are Guide
E-53
Description of Statistics
F X X X X XTT X X X X XTQTD XD XTS XS XTF X X X X XU X X X X XO X X X X XV X X X X XF X X X X XTSO X X X X X
TModeDataIntegrity Add’l
Modes
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
Tem
pera
ture
Sens
orsS
tats
csErrors X X X X X X X X X X X X X Xype: Transmit DurationransmitDuration X X X X X X X X X X X X X Xype: Quality of ServiceualityOfService0 X X X Xype: Data IntegrityataIntegrityFrames X XataIntegrityErrors X Xype:Sequence CheckingequenceFrames X X XequenceErrors X X Xype: Ethernetragments X X X X X X X X X X X X X Xndersize X X X X X X X X X X X X X Xversize X X X X X X X X X X X X X XlanTaggedFramesRx X X X X X X X X X X X X X XlowControlFrames X X X X X X X X X X X X X Xype: 10/100 + GigabitymbolErrorsversizeAndCrcErrors X X X X X X X X X X X X X X
able E-15.Statistics for OC192c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Description of Statistics
E-54Ixia H
ardware G
uide
E
XXXXXXXXXXXXX
ModeDataIntegrity Add’l Modes
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
Tem
pera
ture
Sens
orsS
tats
Type: POSSectionLossOfSignalSectionLossOfFrameSectionBipLineAisLineRdiLineReiLineBipPathAisPathRdiPathReiPathBipPathLossOfPointerPathPlmSectionBipErroredSecsSectionBipSeverlyErroredSecsSectionLossOfSignalSecsLineBipErroredSecsLineReiErroredSecsLineAisAlarmSecs
Table E-15.Statistics for OC192c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Ixia Hardw
are Guide
E-55
Description of Statistics
LPPPPPI X X X X XPPS X X X X XSR
X X X X X
S X X X X XS X X X X XS X X X X XS X X X X XS X X X X XTTD XC X
TModeDataIntegrity Add’l
Modes
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
Tem
pera
ture
Sens
orsS
tats
ineRdiUnavailableSecsathBipErroredSecsathReiErroredSecsathAisAlarmSecsathAisUnavailableSecsathRdiUnavailableSecs
nputSignalStrength X X X X X X X X X X X X X XosK1ByteosK2ByterpDataFramesReceived X X X X X X X X X X X X X XrpDiscoveryFrameseceived
X X X X X X X X X X X X X X
rpIpsFramesReceived X X X X X X X X X X X X X XrpParityErrors X X X X X X X X X X X X X XrpUsageFramesReceived X X X X X X X X X X X X X XrpUsageStatus X X X X X X X X X X X X X XrpUsageTimeouts X X X X X X X X X X X X X Xype: OC192 - emperatureMATemperatureaptureTemperature
able E-15.Statistics for OC192c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Description of Statistics
E-56Ixia H
ardware G
uide
E
XXXXXX
X
X
X
XX
X X X X X XX X X X X XX X X X X X
ModeDataIntegrity Add’l Modes
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
PosE
xten
dedS
tats
Tem
pera
ture
Sens
orsS
tats
LatencyTemperatureBackgroundTemperatureOverlayTemperatureFrontEndTemperatureSchedulerTemperaturePlmDevice1InternalTemperaturePlmDevice2InternalTemperaturePlmDevice3InternalTemperatureFobPort1FpgaTemperatureFobPort2FpgaTemperatureFobBoardTemperatureFobDevice1InternalTemperatureType: 10 Gig - Pause FramePauseAcknowledge X X X X X X X X X X X X XPauseEndFrames X X X X X X X X X X X X XPauseOverwrite X X X X X X X X X X X X X
Table E-15.Statistics for OC192c Modules with BertNormal Qos StreamTrigger
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
Cap
ture
Pack
etG
roup
RxD
ataI
nteg
rity
RxS
eque
nceC
heck
ing
Ixia Hardw
are Guide
E-57
Description of Statistics
Tecks
rorsModeDataIntegrity Add’l
Modes
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edPo
sExt
ende
dSta
ts
Tem
pera
ture
Sens
orsS
tats
TU X X X X X X X X XU X X X X X X X X XC XC XSSTL X X X X X X X X XL X X X X X X X X XD X X X X X X X X XT X X X X X X X X XC X X X X X X X X XP X X X X X X X X XTF X X X X X X X X XF X X X X X X X X XB X X X X X X X X XB X X X X X X X X X
able E-16.Statistics for 10GE Modules with BERTNormal Qos StreamTrigger ModeCh
umEr
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gR
xMod
eBer
tR
xMod
eBer
tCha
nnel
ized
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xTcp
Rou
ndTr
ipR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
y
ype: User ConfigurableserDefinedStat1 X X X X X X X X X X X X X X X X X X XserDefinedStat2 X X X X X X X X X X X X X X X X X XaptureTrigger X X X X XaptureFilter X X X X XtreamTrigger1 X X X X XtreamTrigger2 X X X X Xype: Statesink X X X X X X X X X X X X X X X X X X X X X X X XineSpeed X X X X X X X X X X X X X X X X X X X X X X X XuplexMode X X X X X X X X X X X X X X X X X X X X X X X XransmitState X X X X X X X X X X X X X X X X X X X X X X X XaptureState X X X X X X X X X X X X X X X X X X X X X X X XauseState X X X X X X X X X X X X X X X X X X X X X X X Xype: CommonramesSent X X X X X X X X X X X X X X X X X X X X X X X XramesReceived X X X X X X X X X X X X X X X X X X X X X X X XytesSent X X X X X X X X X X X X X X X X X X X X X X X XytesReceived X X X X X X X X X X X X X X X X X X X
Ixia Hardw
are Guide
E-58
Description of Statistics
F X X X X X X X X XTT X X X X X X X X XTQTIUTIUTTD XD XTS X XS X XTF X X X X X X X X
Tecks
rorsModeDataIntegrity Add’l
Modes
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edPo
sExt
ende
dSta
ts
Tem
pera
ture
Sens
orsS
tats
csErrors X X X X X X X X X X X X X X X X X X X X X X X Xype: Transmit DurationransmitDuration X X X X X X X X X X X X X X X X X X X X X Xype: Quality of ServiceualityOfService0 X X X X Xype: Checksum StatspPackets XdpPackets XcpPackets XpChecksumErrors XdpChecksumErrors XcpChecksumErrors Xype: Data IntegrityataIntegrityFrames X X XataIntegrityErrors X X Xype: Sequence CheckingequenceFrames X X XequenceErrors X X Xype: Ethernetragments X X X X X X X X X X X X X X X X X X X X X
able E-16.Statistics for 10GE Modules with BERTNormal Qos StreamTrigger ModeCh
umEr
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gR
xMod
eBer
tR
xMod
eBer
tCha
nnel
ized
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xTcp
Rou
ndTr
ipR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
y
Description of Statistics
E-59Ixia H
ardware G
uide
E
X X X X X X X XX X X X X X X XX X X X X X X XX X X X X X X X
X XX X
X XX X X X X X X X
XX
deChecksmErrors
ModeDataIntegrity Add’l Modes
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edPo
sExt
ende
dSta
ts
Tem
pera
ture
Sens
orsS
tats
Undersize X X X X X X X X X X X X X X X X X X X X XOversize X X X X X X X X X X X X X X X X X X X X XVlanTaggedFramesRx X X X X X X X X X X X X X X X X X X X X XFlowControlFrames X X X X X X X X X X X X X X X X X X X X XType: 10/100AlignmentErrors X XDribbleErrors X XCollisions X XLateCollisions X XCollisionFrames X XExcessiveCollisionFrames X XType: GigabitSymbolErrorFrames X XSynchErrorFrames X XType: 10/100 + GigabitSymbolErrors X XOversizeAndCrcErrors X X X X X X X X X X X X X X X X X X XType: POSSectionLossOfSignalSectionLossOfFrame
Table E-16.Statistics for 10GE Modules with BERTNormal Qos StreamTrigger Mo
u
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gR
xMod
eBer
tR
xMod
eBer
tCha
nnel
ized
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xTcp
Rou
ndTr
ipR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
re
Ixia Hardw
are Guide
E-60
Description of Statistics
S XL XL XL XL XP XP XP XP XP XP XSSSLLLLPP
Tecks
rorsModeDataIntegrity Add’l
Modes
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edPo
sExt
ende
dSta
ts
Tem
pera
ture
Sens
orsS
tats
ectionBipineAisineRdiineReiineBipathAisathRdiathReiathBipathLossOfPointerathPlmectionBipErroredSecsectionBipSeverlyErroredSecsectionLossOfSignalSecsineBipErroredSecsineReiErroredSecsineAisAlarmSecsineRdiUnavailableSecsathBipErroredSecsathReiErroredSecs
able E-16.Statistics for 10GE Modules with BERTNormal Qos StreamTrigger ModeCh
umEr
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gR
xMod
eBer
tR
xMod
eBer
tCha
nnel
ized
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xTcp
Rou
ndTr
ipR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
y
Ixia Hardw
are Guide
E-61
Description of Statistics
PPPI X X X X X XPPTD XC XL XB XO XF XS XP XP XP XF XFF X
Tecks
rorsModeDataIntegrity Add’l
Modes
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edPo
sExt
ende
dSta
ts
Tem
pera
ture
Sens
orsS
tats
athAisAlarmSecsathAisUnavailableSecsathRdiUnavailableSecs
nputSignalStrength X X X X X X X X X X X X X X X X XosK1ByteosK2Byteype: OC192 - TemperatureMATemperatureaptureTemperatureatencyTemperatureackgroundTemperatureverlayTemperaturerontEndTemperaturechedulerTemperaturelmDevice1InternalTemperaturelmDevice2InternalTemperaturelmDevice3InternalTemperatureobPort1FpgaTemperatureobPort2FpgaTemperatureobBoardTemperature
able E-16.Statistics for 10GE Modules with BERTNormal Qos StreamTrigger ModeCh
umEr
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gR
xMod
eBer
tR
xMod
eBer
tCha
nnel
ized
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xTcp
Rou
ndTr
ipR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
y
Description of Statistics
E-62Ixia H
ardware G
uide
E
X
X X X X X XX X X X X XX X X X X X
deChecksmErrors
ModeDataIntegrity Add’l Modes
Pack
etG
roup
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gC
aptu
rePa
cket
Gro
upR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edPo
sExt
ende
dSta
ts
Tem
pera
ture
Sens
orsS
tats
FobDevice1InternalTemperatureType: 10 Gig - Pause FramePauseAcknowledge X X X X X X X X X X X X X X X X XPauseEndFrames X X X X X X X X X X X X X X X X XPauseOverwrite X X X X X X X X X X X X X X X X X
Table E-16.Statistics for 10GE Modules with BERTNormal Qos StreamTrigger Mo
u
Cap
ture
Pack
etG
roup
RxT
cpR
ound
Trip
RxD
ataI
nteg
rity
RxF
irstT
imeS
tam
pR
xSeq
uenc
eChe
ckin
gR
xMod
eBer
tR
xMod
eBer
tCha
nnel
ized
Cap
ture
Pack
etG
roup
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
rePa
cket
Gro
upR
xTcp
Rou
ndTr
ipR
xDat
aInt
egrit
yR
xFirs
tTim
eSta
mp
RxS
eque
nceC
heck
ing
RxM
odeB
ert
RxM
odeB
ertC
hann
eliz
edC
aptu
re
Ixia Hardw
are Guide
E-63
Description of Statistics
Osp
fSta
ts
Rsv
pSta
ts
LdpS
tats
Table E-17.Statistics for Protocol Server
PosE
xten
dedS
tats
Prot
ocol
Serv
erSt
ats
Arp
Stat
s
Bgp
Stat
s
Icm
pSta
ts
Isis
Stat
s
Type: Protocol Server - GeneralProtocolServerTx XProtocolServerRx XTxArpReply XTxArpRequest XTxPingReply XTxPingRequest XRxArpReply XRxArpRequest XRxPingReply XRxPingRequest XProtocolServerVlanDroppedFrames XScheduledFramesSentAsynchronousFramesSentPortCPUFramesSentType: Protocol Server - BGPBGPTotalSessions XBGPTotalSessionsEstablished XType: Protocol Server - ISISISISSessionsConfiguredL1 XISISSessionsUpL1 XISISSessionsConfiguredL2 XISISSessionsUpL2 X
Description of Statistics
E-64Ixia H
ardware G
uide
E
XX
XXX
XXX
Osp
fSta
ts
Rsv
pSta
ts
LdpS
tats
Type: Protocol Server - OSPFOspfTotalSessionsOSPFFullNeighborsType: Protocol Server - RSVPRSVPIngressLSPsConfiguredRSVPIngressLSPsUpRSVPEgressLSPsUpType: Protocol Server - LDPLdpSessionsConfiguredLdpSessionsUpLdpBasicSessionsUp
Table E-17.Statistics for Protocol Server
PosE
xten
dedS
tats
Prot
ocol
Serv
erSt
ats
Arp
Stat
s
Bgp
Stat
s
Icm
pSta
ts
Isis
Stat
s
Ixia Hardw
are Guide
E-65
Description of Statistics
Description of Statistics
E-66Ixia H
ardware G
uide
E
Index
Numerics10GE BERT 18-110GE LAN 18-110GE Load Modules 18-110GE WAN 18-110Gigabit 18-1
AAntenna A-2, A-3Asynchronous Frames Sent E-11Available Seconds E-17
BBackground Block Error Ratio E-17Background Block Errors E-17Background Chip Temperature E-18BGP Sessions Configured E-11BGP Sessions Established E-11Bit Error Ratio E-16Bit Errors Received E-16Bit Errors Sent E-16Bits Received E-16Bits Sent E-16Block Error State E-17Bytes Received Rate E-9Bytes Sent Rate E-9
CCapture Chip Temperature E-18Capture State E-8Chassis A-2, A-3
Chassis Chaining 2-21Sync-in 2-21Sync-out 2-21
Cumulative Service Disruption Time E-18
DData Integrity Errors E-10Data Integrity Frames E-10DCC Bytes Received E-18DCC Bytes Sent E-18DCC CRC Receive Errors E-18DCC Frames Received E-18DCC Frames Sent E-18DCC Framing Errors Received E-18DMA Chip Temperature E-18
EElapsed Test Time E-17Error Free Seconds E-17Errored Blocks E-16Errored Second Ratio E-16Errored Seconds E-16
FFile-Sharing 2-7Fom Board Temperature E-19Fom Internal Temperature E-19Fom Port Temperature E-19Framer Abort E-9Framer CRC Errors E-9Framer Frames Received E-9Framer Frames Sent E-9
Ixia Hardware Guide Index-1
Index
Framer Max Length & Rate E-9Framer Min Length & Rate E-9Frames Sent Rate E-8Front End Chip Temperature E-18
GGlobal Positioning System A-1GPS 8-4, A-1
HHumidity A-3
IInitial Configuration 2-2Input Signal Strength E-15Introduction 1-1IP Checksum Errors E-10IP Packets Received E-9ISIS L1 Sessions Configured E-11ISIS L1 Sessions Up E-11ISIS L2 Sessions Configured E-11ISIS L2 Sessions Up E-11
LLast Service Disruption Time E-17Latency Chip Temperature E-18LDP Basic Sessions Up E-12LDP Sessions Configured E-12LDP Sessions Up E-12Line AIS E-14Line AIS Alarmed Seconds E-15Line BIP Errored Seconds E-14Line BIP(B2) E-14Line RDI E-14Line RDI Unavailable Seconds E-15Line REI Errored Seconds E-15Line REI(FEBE) E-14
MMaster Chassis Chain 2-21Max Service Disruption Time E-18Min Service Disruption Time E-18Mismatched Ones Ratio E-17Mismatched Zeros Ratio E-17
NNumber Mismatched Ones E-17
Number Mismatched Zeros E-17
OOptional Down Converter A-2OSPF Neighbors in Full State E-12OSPF Total Sessions E-12Overlay Chip Temperature E-18Oversize E-12
PPath AIS E-14Path AIS Alarmed Seconds E-15Path AIS Unavailable Seconds E-15Path BIP Errored Seconds E-15Path BIP(B3) E-14Path LOP E-14Path PLM(C2) E-14Path RDI E-14Path RDI Unavailable Seconds E-15Path REI E-14Path REI Errored Seconds E-15Pause Acknowledge E-22Pause End Frames E-22Pause Overwrite E-22Pause State E-8Plm Internal Chip Temperature E-19Plm Internal Chip Temperature 1 E-19Plm Internal Chip Temperature 2 E-19Port CPU Frames Sent E-11POS K1 Byte E-15POS K2 Byte E-15Powering Up 2-21Protocol Server Receive E-10Protocol Server Transmit E-10
QQuality of Service E-9
RReceive Arp Reply E-11Receive Arp Request E-11Receive Bit Stuffing E-21Receive Buffer Overrun E-22Receive CRC Error E-21Receive Data Overrun E-22Receive Data Toggle Mismatch E-21
Index-2 Ixia Hardware Guide
Index
Receive Data Underrun E-22Receive Device Not Responding E-21Receive NO Error E-21Receive Not Accessed E-22Receive PID Check Failure E-22Receive Ping Reply E-11Receive Ping Request E-11Receive Stall E-21Receive Unexpected PID E-22RG-59 A-2RSVP Egress LSPs Up E-12RSVP Ingress LSPs Configured E-12RSVP Ingress LSPs Up E-12Rx Code Word Violation Counter E-21Rx CRC Error Counter E-21Rx Loss Of Synchronization Status E-21Rx OUt of Frame Status E-21
SSatellite Acquisition A-4Scheduled Frames Sent E-11Scheduler Chip Temperature E-18Section BIP Errored Seconds E-14Section BIP Severely Errored Seconds E-14Section BIP(B1) E-14Section LOF E-14Section LOS E-14Section LOS Seconds E-14Severely Errored Second Ratio E-16Severely Errored Seconds E-16Status E-16Sync-in 2-21Sync-out 2-21
TTCP Checksum Errors E-10TCP Packets Received E-10TCXO A-1Temperature A-3Temperature Compensated Crystal Oscillator A-1Time and Frequency Module A-1, B-1, C-1, D-1Transmit Arp Reply E-10Transmit Arp Request E-11Transmit Buffer Underrun E-22Transmit Device Not Responding E-21Transmit Duration E-9
Transmit NO Error E-21Transmit Not Accessed E-22Transmit PID Check Failure E-21Transmit Ping Reply E-11Transmit Ping Request E-11Transmit Stall E-21Transmit State E-8Transmit Unexpected PID E-22
UUDP Checksum Errors E-10UDP Packets Received E-9Unavailable Seconds E-17Unframed Bert Detected Line Rate E-17Unframed Bert Output Signal Strength E-17Unpacking 2-1
VValid Frames Received Rate E-9virtual chassis chain 8-2VLAN Dropped Frames E-11
WWarnings 2-2
YY connector 2-4
Ixia Hardware Guide Index-3
Index
Index-4 Ixia Hardware Guide
Recommended