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Introduction to
Field Programmable Gate
Arrays
(FPGAs)
MicroLab, NTUA 1
What is a Field Programmable Gate Array ?
.. a quick answer for the impatient
An FPGA is an integrated circuit
Mostly digital electronics
An FPGA is programmable in the in the field (=outside the factory),
hence the name “ field programmable”
Design is specified by schematics or with a
hardware description language
Tools compute a programming file for the FPGA
(gateware or firmware)
The FPGA is configured with the design
Your electronic circuit is ready to use
With an FPGA you can build electronic circuits …
… without using a bread board or soldering iron
… without plugging together NIM modules
… without having a chip produced at a factory
MicroLab, NTUA 2
Outline
Quick look at digital electronics
Shor t history of programmable logic devices
FPGAs and their features
Programming techniques
Design flow
MicroLab, NTUA 3
Acknowledgement
Parts of this lecture are based on material by of several
books on FPGAs and running/completed projects.
MicroLab, NTUA 4
World of Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD FPGA
Digital electronics
MicroLab, NTUA 6
The building blocks: logic gatesTruth table C equivalent
AND gate
OR gate
Exclusive OR gate XOR gate
q = a && b;
q = a || b;
q = a != b;A
BQ
…
MicroLab, NTUA 7
Combinatorial logic (asynchronous)
Outputs are determined by Inputs, only
Example: Full adder with carry-in, carry-out
Combinatorial logic may
be implemented using
Look-Up Tables (LUTs)
LUT = small memory
A B Cin S Cout
0 0 0 0 0
1 0 0 1 0
0 1 0 1 0
1 1 0 0 1
0 0 1 1 0
1 0 1 0 1
0 1 1 0 1
1 1 1 1 1MicroLab, NTUA 8
(Synchronous) sequential logic
Outputs are determined
by Inputs and their History
(Sequence)The logic has an internal state
clock
data Output
Inverted output
reset
D Flip-flop:samples the data at the rising (or falling) edge of the clock
The output will be equal tothe last sampled input until the
next rising (or falling) clock edge
D Flip-flop (D=data, delay)
2-bit binary counter
set
MicroLab, NTUA 9
Synchronous sequential logic
+ =
Using Look-Up-Tables and Flip-Flopsany kind of digital electronics may be implemented
Of course there are some detailsto be learnt about electronics design …
MicroLab, NTUA 10
Programmable
digital electronics
MicroLab, NTUA 11
Long long ti me ago ...
τranslstαs
ΙC (Geneιal)
SRλλ &ORAM
ASICs
SPLDs
CPLDs
I I I I I I I I 11 I I(
ι I ι I I ι I ι I
(
(ι I 1 ι Ι Ι
(
l (
(I ι I ι I
(
MicroLab, NTUA 12
Simple Programmable Logic Devices (sPLDs)a) Programmable Read Only Memory (PROMs)
Late 60’s
Unprogrammed PROM (Fixed AND Array, Programmable OR Array)MicroLab, NTUA 13
Programmable AND array
Unprogrammed PLA (Programmable AND and OR Arrays)
1975Most flexible but slower
Simple Programmable Logic Devices (sPLDs)b) Programmable Logic Arrays (PLAs)
MicroLab, NTUA 14
Unprogrammed PAL (Programmable AND Array, Fixed OR Array)
Simple Programmable Logic Devices (sPLDs)c) Programmable Array Logic (PAL)
MicroLab, NTUA 15
Complex PLDs (CPLDs)
and flip-flops
Coarse grained100’s of blocks, restrictive structure
(EE)PROM basedMicroLab, NTUA 16
τranslstαs
ΙC (Geneιal)
SRλλ &ORAM
ASICs
SPLDs
CPLDs
J:PGA."
FPGAs ...
I I I I I I I I 11 I I(
ι I ι I I ι I ι I
(
(ι I 1 ι Ι Ι
(
l (
(I ι I ι I
(
(
I ιΙ I I
MicroLab, NTUA 17
FPGAs
Programmable Input / Output pinsFine-grained: 100.000’s of blocks today: up to 4 million logic blocks
(extremely flexible)
MicroLab, NTUA 18
LUT-based Fabrics
MicroLab, NTUA 19
Typical LUT-based Logic Cell
Xilinx: logic cell, Altera: logic element
LUT may implement any function of the inputs
Flip-Flop registers the LUT output
May use only the LUT or only the Flip-flop
LUT may alternatively be configured a shift register
Additional elements (not shown): fast carry logicMicroLab, NTUA 20
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
οοοοοοοοοοοοοο
οοοο
ο0 0 0 0 0 0 0
Clock Trees
Clock
treeFlip-flops
οο
0 0 0 0 0 0 0
Specίal clock
pin and pad
Clock signal fromL - - - - - - - oυtside wor1d
Clock trees guarantee that the clock arriνes at the same time at all flip-flopsMicroLab, NTUA 21
Clock Managers
Daughter clocks
may have multiple
or fractionof the frequency
MicroLab, NTUA 22
Embedded RAM blocksColumns of
embedded RAM
blooks
Arrays of
programmable - - - - - . .
loglc blocks
Today: Up to -100 Mbit of RAMMicroLab, NTUA 23
Embedded Multipliers & DSPs
[)][)][)][)]
11
[)]
I[J11j
r - RAM
blocks- Mult.ιplιers
, ...,....,' [ Loglc blocks
_,...- ............r--...
r1 '\
-/ - - [ \
\
MicroLab, NTUA 24
Digital Signal Processor (DSP)
DSP block (Xilinx 7-series) Up to several 1000 per chip
MicroLab, NTUA 25
Soft and Hard Processor Cores
Soft core
Design implemented with
the programmable
resources (logic cells) in
the chip
Hard core
Processor core that is
available in addit ion to the
programmable resources
E.g.: Power PC, ARM
MicroLab, NTUA 26
General-Purpose Input/ Output (GPIO)
Today: Up to 1200 user I/O pins Input and / or output
Voltages from (1.0), 1.2 .. 3.3 VMany IO standards
Single-ended: LVTTL, LVCMOS, … Differential pairs: LVDS, …MicroLab, NTUA 27
High-Speed Serial Interconnect
Using differential pairs
Standard I/ O pins limited to
about 1 Gbit/ s
Latest serial transceivers:
typically 10 Gb/ s, 13.1 Gb/ s,
up to 32.75 Gb/ s
up to 56 Gb/ s with
Pulse Amplitude Modulation(PAM)
FPGAs with multi-Tbit/ s IO
bandwidth
(SERDES)
MicroLab, NTUA 28
Components in a modern FPGA
Ο ' ι ι •[ Q • ι ι ' Οι
ο Logίc block
ΟSRAM block
ο Multiplier
Ο DSP block
D DD
ι ιD
-
ι ι ι
-- 1- 1- r-
ι ι ι
D PLL
D Clock Manager
1/0 Bank
D SERDES
block
- --DD
DD
- - - 1- 1- 1--ι ι ι
- Ι -- f -- Ι -
1- - 1- 1- 1-
DD
DD
ι _ι ι
Ο ι ι ι ιΕ:l)ι ι ι ι Ο
MicroLab, NTUA 29
Programming techniques
MicroLab, NTUA 30
Fusible Links (not used in FPGAs)
Unprogrammed link
Programmed lίnk-----. .... -/ ι ι \ '
MicroLab, NTUA 31
Antifuse Technology
L!Jnprogrammed link
Programmed link
Amorphous sιlioon column
++====; ;;;;::ι.._---, •
Polysilioon νia
+Meta l - •Oxιde • f==.===;;;=;;;=l----
,- Metal
• Substrate •
(a) Before programming (b) After ρrogramming
MicroLab, NTUA 32
EPROM TechnologyErasable Programmable Read Only Memory
Intel, 1971
MicroLab, NTUA 33
EEPROM and FLASH TechnologyElectrically Erasable Programmable Read Only Memory
EEPROM: erasable word by word FLASH: erasable by block or by device
MicroLab, NTUA 34
SRAM-Based Devices
Multi-transistor SRAM cell
MicroLab, NTUA 35
Programming a 3-bit wide LUT
2:1
----
/U
jX
Hard-wϊred Osand 1s(Antifuse technology)
ISRAMoells
(S ; · b a • & d looh, ogy )
2:1
-- -
/U
jXο
1
ο1
ο1
1
1
Υ
C - '
b - - - - - '
C - - '
b - - - - - '
a - - - - - - - - - '
Υ
MicroLab, NTUA 36
Summary of Technologies
Rad-tolerant(e.g. Alice)
Used in mostFPGAs
Rad-tolerant secure
MicroLab, NTUA 37
Design Considerations (SRAM Config.)
MicroLab, NTUA 38
Configuration at power-up
FPGA
( SRAM based )
FlashPROM
Serial bit-stream (may be encrypted)
stores
single or
multiple
designs
Typical FPGA configuration time: millisecondsMicroLab, NTUA 39
Programming via JTAGJoint Test Action Group
FPGA
( SRAM based )
JTAG is a serial bus that can be used to- Program Flash PROMs
- Program FPGAs- Read / write the status of all FPGA I/ Os
( = Boundary scan )
FlashPROM
JTAGconnector
...MicroLab, NTUA 40
Remote programming
...
JTAG bus
FPGA
( SRAM based )
FlashPROM FPGA PCI, VME
The JTAG bus may be driven by an FPGA
which contains an interface to a host PC
via PCI or VME
gateware can then be updated remotelyMicroLab, NTUA 41
Major Manufacturers Xilinx
First company to produce FPGAs in 1985
About 45-50% market share, today
SRAM based CMOS devices
Intel FPGA (formerly Altera)
About 40-45% market share
SRAM based CMOS devices
Microsemi (Actel)
Anti-fuse FPGAs
Flash based FPGAs
Mixed Signal
Lattice Semiconductor
SRAM based with integrated Flash PROM
low power
(Formerly )
MicroLab, NTUA 42
Trends
MicroLab, NTUA 43
Ever-decreasing feature size
130 nmXilinx Virtex-2
28 nm Xilinx Virtex-7 / Altera Stratix V
16 nm Xilinx UltraScale
14 nm Altera Stratix 10
Slowing down
5.5 million logic cells
4 million logic cells
Higher capacity
Higher speed
Lower power
consumption
MicroLab, NTUA 44
Trends Speed of logic increasing
Look-up-tables with more inputs (5 or 6)
Speed of serial links increasing (mult iple Gb/ s)
More and more hard macro cores on the FPGA
PCI Express
Gen2: 5 Gb/ s per lane
Gen3: 8 Gb/ s per lane
up to 8 lanes / FPGA
Gen4: 16 Gb/ s per lane
10 Gb/ s, 40 Gb/ s, 100 Gb/ s Ethernet
Sophist icated soft macros CPUs
Gb/s MACs
Memory interfaces (DDR2 / 3 / 4)
Processor-centric architectures – see next slides
MicroLab, NTUA 45
System-On-a-Chip (SoC) FPGAs
Xlinix Zynq
Altera Stratix 10
CPU(s) + Peripherals + FPGA in one packageMicroLab, NTUA 46
FPGAs in Server Processors and the Cloud
New in 2016: Intel Xeon Server Processor with FPGA insocket
Intel acquired
Altera in 2015
FPGAs in the cloud
Amazon Elastic Cloud F1 instances
8 CPUs / 1 Xlinix UltraScale FPGA
64 CPUs / 8 Xlinix UltraScale FPGA
MicroLab, NTUA 47
FPGA – ASIC comparison
FPGA
Rapid development cycle(minutes / hours)
May be reprogrammed in thefield (gateware upgrade)
New features
Bug fixes
Low development cost
You can get started with a
development board (< $100)
and free software
• ASIC
Higher performance
Analog designs possible
Better radiation hardness
Long development cycle (weeks / months)
Design cannot be changed once it is produced
Extremely high development cost ASICs are produced at a
semiconductor fabrication facility(“ fab” ) according to your design
Lower cost per device comparedto FPGA, when large quantit iesare needed
MicroLab, NTUA 48
FPGA development
MicroLab, NTUA 49
Design entry
Graphical overview
Can draw entire design
Use pre-defined blocks
Can generate blocks using loops
Can synthesize algorithms
Independent of design tool
May use tools used in SW
development (SVN, git …)
entity DelayLine is
generic (
n_halfcycles : integer := 2);
port (
x : in std_logic_vector;
x_delayed : out std_logic_vector;
clk : in std_logic);
end entity DelayLine;
Schematics Hardware description languageVHDL, Verilog
Mostly a personal choice depending on previous experienceMicroLab, NTUA 50
Schematics
MicroLab, NTUA 51
Hardware Description Language
Looks similar to a programming language
BUT be aware of the difference
Programming Language => translated into machine
instructions that are executed by a CPU
HDL => translated into gateware (logic gates & flip-flops)
Common HDLs
VHDL
Verilog
AHDL ( Altera specific )
Newer trends
C-like languages (handle-C, System C)
Labview
MicroLab, NTUA 52
Example: VHDL Looks like a
programming
language
All statements
executed in
parallel, except
inside
processes
MicroLab, NTUA 53
Schematics & HDL combined
Graphlcal State Dlagram
\\\\
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,,,,ιιι
,JTof)-leνel ,, block-leνel
schematic,,
,,
'
\\\
\\\\
'\ \\
\\
Graphlcal Flowchart
Textual HDL
IMιcn cιισnAcsη (s • • Ο)
thθny" ta & bl Ι t ;
e l s e y . c & l (d . "
,,,,,
Blod<..fevel schematlc
MicroLab, NTUA 54
Design flow
Synthesis
ImplementationMap
Place & Route
Timing
SimulationProgramming file
Behavioral
Simulation
constraints Schematics
Pins Timing Area
…
Core GeneratorVHDL / Verilog
Counters FIFOs…
Static Timing
Analysis
Intellectual Property cores
Processors Interfaces Controllers
…
State Machines
Register Transfer Level (RTL) model
MicroLab, NTUA 55
Floorplan (ΧΙinx Virtex 2)
MicroLab, NTUA 56
Manual Floor planning
For large designs, manual
floor planning may be necessary
Routing congesti on
Xilinx Virtex 7 (Vivado)MicroLab, NTUA 57
Embedded Logic Analyzers
MicroLab, NTUA 58
Recommended