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Hardware Design with VHDL FSMs ECE 443
ECE UNM 1 (11/19/08)
FSMs
Mealy vs. Moore:
FSMs can be described using state diagrams or algorithmic state machines (ASMs)
next state
state_nextd q
state
clk
Mealy
inputs
output
Mooreoutputlogic
logic
Mealy
outputs
Moore
outputs
reg.logic
state_reg
state_name
moore< = valexpr
mealy <= val
expr
mealy <= val
to other state to other state
Hardware Design with VHDL FSMs ECE 443
ECE UNM 2 (11/19/08)
State Transition Graph and ASMs
State diagrams contain nodes (states) and transition arcs.
The arcs are associated with a logical expression of the input signals -- when
true, the arc is taken.
Moore outputs depend only on the state and are placed inside the circles.
Mealy outputs depend on the state and inputs, and are listed on the arcs.
Only the asserted outputs are listed.
ASMs
Each state box has only one exit and is usually followed by a decision box.
moore <= val
state_name
boolean cond.T F
mealy <= valconditionaloutput box
decision box
state box
Hardware Design with VHDL FSMs ECE 443
ECE UNM 3 (11/19/08)
State Transition Graph and ASMs
Example:
This FSM has three states, two input signals a and b, a Moore output y1 and a Mealy
output y0.
y1 is asserted when in states s0 and s1. y0 is asserted when in s0 and a.b is true.
y1 <= 1
s0
TT
y0 <= 1
s0y1 <= 1
s1
y1 <= 1
a
a
a
a.b
s2
a.by0 <= 1
a=1F
b=1
s2
a=1
F
y1 <= 1
T F
s1
Hardware Design with VHDL FSMs ECE 443
ECE UNM 4 (11/19/08)
State Transition Graph and ASMs
library ieee;
use ieee.std_logic_1164.all;
entity fsm_ex is
port(
clk, reset: in std_logic;
a, b: in std_logic;
y0, y1: out std_logic;
);
end fsm_ex
architecture mult_seg_arch of fsm_ex is
type ex_state_type is (s0, s1, s2);
signal state_reg, state_next: ex_state_type;
begin
process(clk, reset)
begin
if (reset = ’1’) then
state_reg <= s0;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 5 (11/19/08)
State Transition Graph and ASMs
elsif (clk’event and clk = ’1’) then
state_reg <= state_next;
end if;
end process;
process(state_reg, a, b)
begin
case state_reg is
when s0 =>
if (a = ’1’) then
if (b = ’1’) then
state_next <= s2;
else
state_next <= s1;
end if;
else
state_next <= s0;
end if;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 6 (11/19/08)
State Transition Graph and ASMs
when s1 =>
if (a = ’1’) then
state_next <= s0;
else
state_next <= s1;
end if;
when s2 =>
stat_next <= s0;
end case;
end process;
-- Moore output logic
process (state_reg)
begin
case state_reg is
when s0 | s2 =>
y1 <= ’0’;
when s1 =>
y1 <= ’1’;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 7 (11/19/08)
State Transition Graph and ASMs
end case;
end process;
-- Mealy output logic
process (state_reg, a, b)
begin
case state_reg is
when s0 =>
if (a = ’1’ and b = ’1’) then
y0 <= ’1’;
else
y0 <= ’0’;
end if;
when s1 | s2 =>
y0 <= ’0’;
end case;
end process;
end mult_seg_arch;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 8 (11/19/08)
FSMD
An FSMD (finite state machine with data path) combines an FSM and regular
sequential logic.
The FSM is referred to as the control path -- it examines the external commands and
status and generates control signals to control the operation of the data path.
FSMD are used to describe RTL (register transfer level) logic.
Here, operations manipulate data and control transfer among a set of registers.
Note that the result, 9 - 3 + 1 = 7 is not stored until the rising edge of clk.
Also, b_reg changes after a clk-to-q delay.
d q
d q
clk
+1-a_next
a_reg
b_reg
clk
a_reg
9
3
57b_reg
Hardware Design with VHDL FSMs ECE 443
ECE UNM 9 (11/19/08)
FSMD
The ASM chart for an RTL circuit:
RTL operations are treated as output signals and are placed inside the boxes.
The current state, given by state_reg, selects the MUX
Here, r1 is destination register. First it is initialized to 8, and then is added to the con-
tents of r2, and then shifted left by two bits.
The r1 <- r1 is the default operation (no change) and is typically left out.
s0 s1 s2 s3
r1 <- 8 r1 <- r1+r2 r1 <- r1<< 2 r1 <- r1
d q
d q
0123
8+
<<2
state_reg
clk
r2_reg
r1_regr1_next
Hardware Design with VHDL FSMs ECE 443
ECE UNM 10 (11/19/08)
FSMD
As another example:
Here, the RTL operation on r2 is specified in a conditional output box.
All operations, e.g., r2 + a and r2 + b are performed in parallel and the proper value
is routed to the input of r2_reg based on the condition and state_reg.
r1 <- r1 - 1
s0
a > b
r2 <- r2 + ar2 <- r2 + b
d q0-1
d q0
+
+
state_reg
01
clk
>ab
F T r2_reg
r1_reg
r1_next
r2_next
Hardware Design with VHDL FSMs ECE 443
ECE UNM 11 (11/19/08)
FSMD
Note that the destination register is updated when the FSMD exits the current state,
e.g., r_next <= r_reg - 1; r_reg <= r_next on the next rising edge of clk.
Beware the delayed store:
On the left, the r register is decremented in the state box and ALSO used in the deci-
sion box.
Since r is NOT updated until exit from the state box, the old content of r is used
in the decision box!
The right side shows how to use the new value -- here the output of the combinational
logic is used (r_next) in the decision box.
s1
r <- r - 1
r = 0F
T
s1
r_next := r - 1
r_next = 0F
T
r <- r_next
’:=’ indicatesimmediateassignment
Hardware Design with VHDL FSMs ECE 443
ECE UNM 12 (11/19/08)
FSMD
General structure of an FSMD:
Although the FSMD consists of two types of sequential circuits, both are controlled
by the same clock.
d qdataregs
routingnetwork
Data path
functionalunits
routingnetworkdata
input
dataoutput
outputlogic
Control path
d qstateregs
next-statelogic
control signalsinternal status
external status
command
FSM
Hardware Design with VHDL FSMs ECE 443
ECE UNM 13 (11/19/08)
RTL Version of Debouncing Circuit
The FSM is used to initiate a timer so that an exact ’wait’ interval can be imple-
mented.
zero
sw = 1
q <- 1..1
wait1
sw = 1
F
T
q_next:= q-1
T
F
q <- q_next
q_next = 0T
F
db_tick <- 1
one
sw = 0
q <- 1..1
wait0
sw = 0
F
T
q_next:= q-1
T
F
q <- q_next
q_next = 0
T
F
db_level <- 1
Hardware Design with VHDL FSMs ECE 443
ECE UNM 14 (11/19/08)
RTL Version of Debouncing Circuit
The signal db_level is the debounced output.
The db_tick signal is a one-clock-cycle enable pulse asserted at the zero-to-one
transition, i.e., during the last clock cycle while in state wait1.
The zero and one states mean that the sw input has been stabilized for ’0’ and ’1’,
respectively.
The wait0 and wait1 states filter out short glitches.
The datapath consists of one register q which is 21 bits wide.
In the zero state, when the sw signal becomes ’1’, the FSMD moves to the wait1 state
and initializes q to all ’1’s.
While in wait1, q is decremented by one on each clock cycle as long as sw
remains ’1’.
Once q reaches ’0’, the FSM moves to the one state.
With a 50 MHz clock, the delay is 20 ns * 221 = 40 ms
Hardware Design with VHDL FSMs ECE 443
ECE UNM 15 (11/19/08)
Code of Debouncing Circuit
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debounce is
port(
clk, reset: in std_logic;
sw: in std_logic;
db_level, db_tick: out std_logic;
);
end debounce;
architecture exp_fsmd_arch of debounce is
constant N: integer:= 21;
type state_type is (zero, wait0, one, wait1);
signal state_reg, state_next: state_type;
signal q_reg, q_next: unsigned(N-1 downto 0);
signal q_load, q_dec, q_zero: std_logic;
begin
Hardware Design with VHDL FSMs ECE 443
ECE UNM 16 (11/19/08)
Code of Debouncing Circuit
process(clk, reset)
begin
if (reset = ’1’) then
state_reg <= zero;
q_reg <= (others => ’0’);
elsif (clk’event and clk = ’1’) then
state_reg <= state_next;
q_reg <= q_next;
end if;
end process;
-- FSMD data path (counter) next-state logic
q_next <= (others => ’1’) when q_load = ’1’ else
q_reg - 1 when q_dec = ’1’ else
q_reg;
q_zero <= ’1’ when q_next = 0 else ’0’;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 17 (11/19/08)
Code of Debouncing Circuit
process(state_reg, sw, q_zero)
begin
q_load <= ’0’;
q_dec <= ’0’;
db_tick <= ’0’;
state_next <= state_reg;
case state_reg is
when zero =>
db_level <= ’0’;
if (sw = ’1’) then
state_next <= wait1;
q_load <= ’1’;
end if;
when wait1 =>
db_level <= ’0’;
if (sw = ’1’) then
q_dec <= ’1’;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 18 (11/19/08)
Code of Debouncing Circuit
if (q_zero = ’1’) then
state_next <= one;
db_tick <= ’1’;
end if;
else
state_next <= zero;
end if;
when one =>
db_level <= ’1’;
if ( sw = ’0’ ) then
state_next <= wait0;
q_load <= ’1’;
end if;
when wait0 =>
db_level <= ’1’;
if (sw = ’0’) then
q_dec <= ’1’;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 19 (11/19/08)
Code of Debouncing Circuit
if (q_zero = ’1’) then
state_next <= zero;
end if;
else
state_next <= one;
end if;
end case;
end process;
end exp_fsmd_arch;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 20 (11/19/08)
RTL Schematic of Debouncing Circuit
21 FFs ofdown cnter
zero detect unit
Next state logic
feedback
q_dec andq_load logic
q_next logic
Hardware Design with VHDL FSMs ECE 443
ECE UNM 21 (11/19/08)
Fibonacci Number Circuit
The Fibonacci numbers constitute a sequence defined as:
This can be implemented in an iterative fashion, from 0 to i.
Requires two temp registers to store the 2 most recently calculated values, fib(i-1)
and fib(i-2) and one index register to track the # of iterations.
fib i( ) =01fib i 1–( ) fib i 2–( )+
if i =0if i =1if i >1
Hardware Design with VHDL FSMs ECE 443
ECE UNM 22 (11/19/08)
Fibonacci Number Circuit
ready <= ’1’
idle
start = 1
t0 <- 0t1 <- 1n <- i
F
T
op
n = 0
n = 1t1 <- 0
T F
t1 <- t1+t0t0 <- t1n <- n-1done_tick <- 1
done
T
t0 and t1 are the temp regs.
F
n is the index reg.
i, start are input signalsready, done_tick are output signals
Initial state witht0 = 0 represents fib(0)t1 = 1 represents fib(1)
First iteration of op:t0 = 1t1 = 1
Second iteration of op:t0 = 1t1 = 2
Third iteration of op:t0 = 2t1 = 3
Fourth iteration of op:t0 = 3t1 = 5
The f output signal is t1
Hardware Design with VHDL FSMs ECE 443
ECE UNM 23 (11/19/08)
Fibonacci Number Circuit
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fib is
port(
clk, reset: in std_logic;
start: in std_logic;
i: in std_logic_vector(4 downto 0);
ready, done_tick: out std_logic;
f: out std_logic_vector(19 downto 0)
);
end fib;
architecture arch of fib is
type state_type is (idle, op, done);
signal state_reg, state_next: state_type;
signal t0_reg, t0_next: unsigned(19 downto 0);
signal t1_reg, t1_next: unsigned(19 downto 0);
Hardware Design with VHDL FSMs ECE 443
ECE UNM 24 (11/19/08)
Fibonacci Number Circuit
signal n_reg, n_next: unsigned(4 downto 0);
begin
process(clk, reset)
begin
if (reset = ’1’) then
state_reg <= idle;
t0_reg <= (others => ’0’);
t1_reg <= (others => ’0’);
n_reg <= (others => ’0’);
elsif (clk’event and clk = ’1’) then
state_reg <= state_next;
t0_reg <= t0_next;
t1_reg <= t1_next;
n_reg <= n_next;
end if;
end process;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 25 (11/19/08)
Fibonacci Number Circuit
process(state_reg, n_reg, t0_reg, t1_reg,
start, i, n_next)
begin
ready <= ’0’;
state_next <= state_reg;
t0_next <= t0_reg;
t1_next <= t1_reg;
n_next <= n_reg;
case state_reg is
when idle =>
ready <= ’1’;
if (start = ’1’) then
t0_next <= (others => ’0’);
t1_next <= (0=>’1’, others => ’0’);
n_next <= unsigned(i);
state_next <= op;
end if;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 26 (11/19/08)
Fibonacci Number Circuit
when op =>
if (n_reg = 0) then
t1_next <= (others => ’0’);
state_next <= done;
elsif (n_reg = 1) then
state_next <= done;
else
t1_next <= t1_reg + t0_reg;
t0_next <= t1_reg;
n_next <= n_reg - 1;
end if;
when done =>
done_tick <= ’1’;
state_next <= idle;
end case;
end process;
f <= std_logic_vector(t1_reg);
end arch;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 27 (11/19/08)
RTL Schematic of Fibonacci Number Circuit
t1 next logic
t0 next logic
t0 regs
n next logic
n regs
t1 regs
t0+t1
n = n -1
Hardware Design with VHDL FSMs ECE 443
ECE UNM 28 (11/19/08)
Division Circuit
Long division:
The pseudo-code to implement this:
• Double the dividend width by appending 0’s in front and align the divisor to the lef-
most bit of the extended dividend.
• If the relevant dividend bits are greater than or equal to the divisor, subtract the divi-
sor from the divident and add a ’1’ to the quotient bits.
• Append one additional dividend bit to the previous result and shift the divisor to the
right one position
• Repeat steps 2 & 3 until all dividend bits are used.
001000110
000011010000
00010000
00110010
00100010
0001
dividend
quotient
remainder
divisor
Hardware Design with VHDL FSMs ECE 443
ECE UNM 29 (11/19/08)
Division Circuit
Data path:
Each iteration, rh and rl are shifted left one position, which corresponds to shifting
the divisor to the right in pseudo-code.
Compare rh and d and perform subtraction if rh is >= d.
When rh and rl are shifted left, the rightmost bit of rl is used to store q_bit.
d
compare & subtract
shift left 1 bit
q_bitrh_tmp
rh_tmp
rh rl
divisor stored here
extended dividendstored here
Hardware Design with VHDL FSMs ECE 443
ECE UNM 30 (11/19/08)
Division Circuit
Finally, after the last iteration, the result of the last subtraction is stored in rh, which
becomes the remainder, while the quotient is latched into rl.
The ASMD consists of four states, idle, op, last and done.
The compare and subtract and shift left operations are carried out in the op state.
Since the remainder is not shifted in the last iteration, a separate state, last, is created
to accommodate this.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div is
generic(
W: integer:= 8;
CBIT: integer:= 4
);
Hardware Design with VHDL FSMs ECE 443
ECE UNM 31 (11/19/08)
Division Circuit
port(
clk, reset: in std_logic;
start: in std_logic;
dvsr, dvnd: in std_logic_vector(W-1 downto 0);
ready, done_tick: out std_logic;
quo, rmd: out std_logic_vector(W-1 downto 0)
);
end div;
architecture arch of div is
type state_type is (idle, op, last, done);
signal state_reg, state_next: state_type;
signal rh_reg, rh_next: unsigned(W-1 downto 0);
signal rl_reg, rl_next:
std_logic_vector(W-1 downto 0);
signal rh_tmp: unsigned(W-1 downto 0);
signal d_reg, d_next: unsigned(W-1 downto 0);
signal n_reg, n_next: unsigned(CBIT-1 downto 0);
Hardware Design with VHDL FSMs ECE 443
ECE UNM 32 (11/19/08)
Division Circuit
signal q_bit: std_logic;
begin
process(clk, reset)
begin
if (reset = ’1’) then
state_reg <= idle;
rh_reg <= (others => ’0’);
rl_reg <= (others => ’0’);
d_reg <= (others => ’0’);
n_reg <= (others => ’0’);
elsif (clk’event and clk = ’1’) then
state_reg <= state_next;
rh_reg <= rh_next;
rl_reg <= rl_next;
d_reg <= d_next;
n_reg <= n_next;
end if; end process;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 33 (11/19/08)
Division Circuit
process(state_reg, n_reg, rh_reg, rl_reg, d_reg,
start, dvsr, dvnd, q_bit, rh_tmp, n_next)
begin
ready <= ’0’;
done_tick <= ’0’;
state_next <= state_reg;
rh_next <= rh_reg;
rl_next <= rl_reg;
d_next <= d_reg;
n_next <= n_reg;
case state_reg is
when idle =>
ready <= ’1’;
if (start = ’1’) then
rh_next <= (others => ’0’);
rl_next <= dvnd;
d_next <= unsigned(dvsr);
Hardware Design with VHDL FSMs ECE 443
ECE UNM 34 (11/19/08)
Division Circuit
-- iteration counter initialized to the value 9
n_next <= to_unsigned(W+1, CBIT);
state_next <= op;
end if;
when op =>
-- shift rh and rl left
rl_next <= rl_reg(W-2 downto 0) & q_bit;
rh_next <= rh_tmp(W-2 downto 0) &
rl_reg(W-1);
n_next <= n_reg - 1;
if (n_next = 1) then
state_next <= last;
end if;
-- don’t shift rh_next on last iteration
when last =>
rl_next <= rl_reg(W-2 downto 0) & q_bit;
rh_next <= rh_tmp;
state_next <= done;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 35 (11/19/08)
Division Circuit
when done =>
state_next <= idle;
done_tick <= ’1’;
end case;
end process;
process (rh_reg, d_reg)
begin
if (rh_reg >= d_reg) then
rh_tmp <= rh_reg - d_reg;
q_bit <= ’1’;
else
rh_tmp <= rh_reg;
q_bit <= ’0’;
end if;
end process;
quo <= rl_reg;
rmd <= std_logic_vector(rh_reg); end arch;
Hardware Design with VHDL FSMs ECE 443
ECE UNM 36 (11/19/08)
RTL of Division Circuit
cnter nnext logic
cnter nFFs
cnter nsubtractor
divisor
divisor and rh_regsubtractor &comparator
rh_reg
rl_reg
next state logic
rl next logic
rh next logic
rh tmp logic
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