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Qi Wang
VP and Chief of Staff to the CEO
Cadence
Sept 26, 2017
FD-SOI Foundry Enablement –From Concept to Mass Production
© 2017 Cadence Design Systems, Inc. All rights reserved.2
Emerging Technology Trends
CONNECTED CAR INTERNET OF THINGSAR / VR
DEEP LEARNING
CLOUD /
DATACENTER
© 2017 Cadence Design Systems, Inc. All rights reserved.3
INTERNET OF
THINGS*****
$11B
$34B
2015 2020
AR / VR**
$2B
$22B
2015 2020
$24B
$37B
2015 2020
CONNECTED
CAR*
Emerging Technology Trends
The opportunities are massive* IBS Global Service Industry Report, Nov 2016
** MarketAndMarkets, AR/VR Market Forecast 2016
*** Gartner Semiconductor Forecast Q3’16
**** BofAMerrill Lynch Global Research estimates October 2016
***** Gartner Forecast – IoT Endpoints, Nov 2016
$.6M
$10B
2015 2020
DEEP
LEARNING****
$65B
$80B
2015 2020
CLOUD /
DATACENTER***
© 2017 Cadence Design Systems, Inc. All rights reserved.4
Cadence System Design Enablement
SYSTEM INTEGRATION
PACKAGE AND BOARD
CHIP (Core EDA)
IP
System Analysis * Hardware-Software Verification * Software Applications
PCB Design * Package Design * PCB and Package Analysis
Design and Implementation * IP/SoC Verification * Software Drivers
CLOUD / HPC AUTOMOTIVE MOBILE AERO AND DEFENSE MEDICAL AND MORE…
© 2017 Cadence Design Systems, Inc. All rights reserved.5
Cadence Implementation LeadershipTechnology innovation: fast, smart, and optimized
Quantus™
Tempus™
Voltus™
Genus™
Modus DFT
Innovus™
Massively parallel for speed and capacity
Best PPA and intelligent flows
Rapid convergence and ECO
Fully integrated mixed signal
Implementation FabricCommon Engines, UI, and Flows
Pegasus™
PLACE and ROUTEFRONT END ELECTRICAL SIGNOFF
LogicalConformal®
ElectricalTiming, Power
PPA EnginesOptimization
PhysicalDRC, LVS, DFM
• Best-in-class core tools
• Common foundation
engines
• Differentiated productivity
DESIGN RULE CHECK
© 2017 Cadence Design Systems, Inc. All rights reserved.6
CHARACTERIZATIONLiberate™
Variety™
Cadence Custom IC and PCB Design LeadershipEnabling smart product design from start to finish
PACKAGEAllegro®
Virtuoso
CHIPVirtuoso®
Spectre®
ANALYSISSigrity™ Market leadership for
over 25 years
In excess of 70 different
ecosystem partners
Differentiated and
comprehensive
support for IoT,
automotive, and
aero/defense designs
System Design Enablement via an Extensive Ecosystem
BOARDAllegro
PSpice®
OrCAD®
Mixed signal
Analog/RF
Photonics support
Rigid-flex board enablement
Advanced node (28nm to 5nm)
Advanced packaging
© 2017 Cadence Design Systems, Inc. All rights reserved.7
Cadence Verification SuiteTechnology innovation leadership: fast, smart, and optimized
VIPVERIFICATION IP
Perspec™
SW-DRIVEN TEST
vManager™
METRICS
Indago™
DEBUGUniform multi-engine verificationVerification Fabric
Palladium® Z1EMULATION
Xcelium™
SIMULATION
JasperGold®
FORMAL and STATIC
Protium™ S1FPGA PROTOTYPE
Total throughput
Metric-driven signoff
Application optimized
Cloud-centric architecture
• Fast: Best-in-class engines
• Smart: Flow-driven engine
integrations
• Optimized:
Comprehensive solutions
© 2017 Cadence Design Systems, Inc. All rights reserved.8
EDA Requirements for Developing Foundry Technology NodeFor customer confidence in fast ramp and efficient usage – 22FDX
Working Silicon
Proof-Points (tapeouts)
Mixed-Signal Support, System Design Support
Reference Flows
Specific Tool Features Enabled (SOI)
PDK and Tech Files
© 2017 Cadence Design Systems, Inc. All rights reserved.9
2015
Digital and Signoff Tools 22FDX Enabled
2016
V0.5 22FDX TapeoutSupported
EAD in 22FDX
2017
Phase III of 22FDX Reference Flow
Digital Reference Flow for 28FDS Voltus 28FDS Certification
Cadence Design Solutions for FD-SOIStrong collaboration history – tool enablement and design flows
© 2017 Cadence Design Systems, Inc. All rights reserved.10
Samsung-Cadence Collaboration on 28FDS
Cadence DFM Signoff Solutions Achieve Qualification for Samsung 28nm FD-SOI/14nm/10nm Process Technologies
Samsung Expands FD-SOI Process Technology Leadership and its Design Ecosystem Readiness
© 2017 Cadence Design Systems, Inc. All rights reserved.11
Enabling FD-SOI Process
Genus Design
ExplorationReleased in December 2016
Innovus Body-Bias
Interpolation September 2017
Tempus Body-Bias
Interpolation September 2017
Voltus Body-Bias
Interpolation Upcoming
This slide contains forward-looking statements about Cadence business or products. Actual results may differ materially from the information presented here.
© 2017 Cadence Design Systems, Inc. All rights reserved.12
MathWorks
• Beamforming
• Digital Pre-Distortion
• Calibration
Finite
Element
Mesh
Virtuoso
E/M
FieldS-Parameter
5G / 802.11ax Design Enablement for FD-SOIIndustry-leading RF solution in PCB, SiP, and SoC
Allegro
Sigrity
Virtuoso
Virtuoso Layout SuiteCadence SiP LayoutAllegro PCB RF Layout Analog Design Environment
Spectre RF
S-Parameter
Allegro
Sigrity
SoC Design
© 2017 Cadence Design Systems, Inc. All rights reserved.13
Cadence Tensilica Processor IP For automotive applications
Front-collision warning
Automatic high beam
Traffic sign
detection/
recognition
Lane-departure warning
Digital radio receiver: HD Radio,
DAB, DAB+, DRM, T-DMB
Multi-channel audio decode and
advanced post-processing
Multi-microphone voice command and noise reduction
Embedded Signal Processing
ADAS Vision Processing
Digital Radio and Voice Command
Acoustic noise cancellation
Advanced Driver Assistance Systems
Built-in LTE modem and
Wi-Fi access point
Peer-to-peer smart car
networking for intelligent
vehicle highway control
GPS
Telematics Connectivity / Radar
Emergency services
Battery management
Regenerative power
management
Engine control
Cabin environmental control
Tensilica® HiFi DSPs Tensilica Fusion DSPs
Tensilica Vision DSPs Tensilica ConnX DSPs
Radar/Lidar
ISO 26262 Ready / ISO 9001 Certified
© 2017 Cadence Design Systems, Inc. All rights reserved.14
SOI Advanced-Node EDA Enablement – 28FDS
Samsung 28FDS Cadence Digital Reference Flow presented at CDNLive Silicon
Valley 2017: “Fast Ramp to Reap 28FDSOI Benefits ”
Design Capabilities 28FDS
Logic Simulation (Incisive)
Dig
ital I
mple
menta
tion a
nd S
ignoff
(RT
L to G
DS
)
Synthesis (Genus)
Power Analysis (Joules)
Test (Modus)
Place and Route (Innovus)
Timing Analysis (Tempus)
Extraction (Quantus)
EM/IR Analysis (Voltus)
Physical Verification (PVS)
Litho Physical Analysis (DFM/LPA)
Litho Electrical Analysis (DFM/LEA)
Chemical Mechanical Polishing (DFM/CMP)
Custo
m a
nd A
nalo
g
Desig
n
Schematic Editing (Virtuoso VSE)
Analog Design Environment (Virtuoso ADE)
Layout System (Virtuoso VLS)
Circuit Simulation (Spectre APS/XLS)
Electrically Aware Design (EAD)
EM/IR Analysis (Voltus-Fi)
Certified
Enabled
© 2017 Cadence Design Systems, Inc. All rights reserved.15
SOI Advanced-Node EDA Enablement – 22FDX
Design Capabilities 22FDX
Logic Simulation (Incisive)
Dig
ital I
mple
menta
tion a
nd S
ignoff
(RT
L to G
DS
)
Synthesis (Genus)
Power Analysis (Joules)
Test (Modus)
Place and Route (Innovus)
Timing Analysis (Tempus)
Extraction (Quantus)
EM/IR Analysis (Voltus)
Physical Verification (PVS)
Litho Physical Analysis (DFM/LPA)
Litho Electrical Analysis (DFM/LEA)
Chemical Mechanical Polishing (DFM/CMP)
Custo
m a
nd A
nalo
g
Desig
n
Schematic Editing (Virtuoso VSE)
Analog Design Environment (Virtuoso ADE)
Layout System (Virtuoso VLS)
Circuit Simulation (Spectre APS/XLS)
Electrically Aware Design (EAD)
EM/IR Analysis (Voltus-Fi)
Certified
Enabled
© 2017 Cadence Design Systems, Inc. All rights reserved.16
Cadence EDA Solutions Ready for FD-SOIEnables designers to take optimal advantage of FD-SOI technology
Working Silicon
Proof-Points (tapeouts)
Mixed-Signal Support, System Design Support
Reference Flows
Specific Tool Features Enabled (SOI)
PDK and Tech Files
Signoff-proven, Vision/DDR4, working boards running system and application software demos
High-performing industry-standard IP used in tapeout
Mixed-Signal Open Access (MSOA) PDK; packaging, signal integrity analysis for system-level
Custom analog, digital, PPA / TTM
Back-biasing, forward-biasing in
placement, routing, timing, IR drop
Custom analog design, digital design, physical verification decks, library characterization
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
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