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EE105 Fall 2007 Lecture 18, Slide 1 Prof. Liu, UC Berkeley
Lecture 18
OUTLINE• Basic MOSFET amplifier• MOSFET biasing• MOSFET current sources• Common-source amplifier
Reading: Chapter 7.1-7.2
ANNOUNCEMENTS• HW#10 will be posted tonight
EE105 Fall 2007 Lecture 18, Slide 2 Prof. Liu, UC Berkeley
• For large small-signal gain, the MOSFET should be operated in the saturation region. Vout should not fall below Vin by more than VTH.
Basic MOSFET Amplifier
EE105 Fall 2007 Lecture 18, Slide 3 Prof. Liu, UC Berkeley
MOSFET BiasingThe voltage at node X is determined by VDD, R1, and R2:Also,
Soxn
THDD
THGS
RLW
CV
VRR
VRVVVVV
1 where
2
1
21
21
211
DDX VRR
RV
21
2
SDGSX RIVV
2
2
1THGSoxnD VV
L
WCI
EE105 Fall 2007 Lecture 18, Slide 4 Prof. Liu, UC Berkeley
Self-Biased MOSFET Stage• Note that there is no voltage dropped across RG
M1 is operating in the saturation region.
DDDSGSDD VIRVRI
EE105 Fall 2007 Lecture 18, Slide 5 Prof. Liu, UC Berkeley
MOSFETs as Current Sources• A MOSFET behaves as a current source when it is operating in
the saturation region.• An NMOSFET draws current from a point to ground (“sinks
current”), whereas a PMOSFET draws current from VDD to a point (“sources current”).
EE105 Fall 2007 Lecture 18, Slide 6 Prof. Liu, UC Berkeley
Common-Source Stage: = 0
Dout
in
DDoxnDmv
RR
R
RIL
WCRgA
2
Amplifier circuit Small-signal analysis circuitfor determining voltage gain, Av
Small-signal analysis circuit fordetermining output resistance, Rout
EE105 Fall 2007 Lecture 18, Slide 7 Prof. Liu, UC Berkeley
Common-Source Stage: 0• Channel-length modulation results in reduced small-signal
voltage gain and amplifier output resistance.
ODout
in
ODmv
rRR
R
rRgA
||
||
Small-signal analysis circuitfor determining voltage gain, Av
Small-signal analysis circuit fordetermining output resistance, Rout
EE105 Fall 2007 Lecture 18, Slide 8 Prof. Liu, UC Berkeley
CS Gain Variation with L• An ideal current source has infinite small-signal resistance.The largest Av is achieved with a current source as the load.
• Since is inversely proportional to L, Av increases with L.
D
oxn
D
Doxn
omv I
WLC
I
ILW
CrgA
2
2
EE105 Fall 2007 Lecture 18, Slide 9 Prof. Liu, UC Berkeley
CS Stage with Current-Source Load
21
211
||
||
OOout
OOmv
rrR
rrgA
• Recall that a PMOSFET can be used as a current source from VDD.Use a PMOSFET as a load of an NMOSFET CS amplifier.
EE105 Fall 2007 Lecture 18, Slide 10 Prof. Liu, UC Berkeley
PMOS CS Stage with NMOS Load • An NMOSFET can be used as the load for a PMOSFET CS amplifier.
21
212
||
)||(
OOout
OOmv
rrR
rrgA
EE105 Fall 2007 Lecture 18, Slide 11 Prof. Liu, UC Berkeley
CS Stage with Diode-Connected Load
Av is lower, but it is less dependent on process parameters (n and Cox and drain current (ID).
Amplifier circuit Small-signal analysis circuitincluding MOSFET output resistances
2
1
21 /
/1
:0 If
LW
LW
ggA
mmv
122
122
1
||||1
||||1
OOm
out
OOm
mv
rrg
R
rrg
gA
:0
EE105 Fall 2007 Lecture 18, Slide 12 Prof. Liu, UC Berkeley
CS Stage with Diode-Connected PMOS Load
211
211
2
||||1
||||1
oom
out
oom
mv
rrg
R
rrg
gA
:0
EE105 Fall 2007 Lecture 18, Slide 13 Prof. Liu, UC Berkeley
CS Stage with Degeneration
Sm
Dv
Rg
RA
1 :0 If
Amplifier circuit Small-signal analysis circuitfor determining voltage gain, Av
EE105 Fall 2007 Lecture 18, Slide 14 Prof. Liu, UC Berkeley
Example• A diode-connected device degenerates a CS stage.
21
11
mm
Dv
gg
RA
EE105 Fall 2007 Lecture 18, Slide 15 Prof. Liu, UC Berkeley
Rout of CS Stage with Degeneration• Degeneration boosts the output impedance:
Small-signal analysis circuit fordetermining output resistance, Rout
SOmOSSmOX
X
XSXSXmXO
RrgrRRgri
v
vRiRigir
1
SXRiv 1
Current flowing down through ro is
SXmX
SXmXmX
Rigi
Rigivgi
1
EE105 Fall 2007 Lecture 18, Slide 16 Prof. Liu, UC Berkeley
Output Impedance Examples
211
11
mmOout ggrR 1211 OOOmout rrrgR
EE105 Fall 2007 Lecture 18, Slide 17 Prof. Liu, UC Berkeley
CS Stage with Gate Resistance• For low signal frequencies, the gate conducts no current. Gate resistance does not affect the gain or I/O impedances.
EE105 Fall 2007 Lecture 18, Slide 18 Prof. Liu, UC Berkeley
CS Core with Biasing
Sm
D
Gv
Rg
R
RRR
RRA
1||
||
21
21Dm
Gv Rg
RRR
RRA
21
21
||
||
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