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ECE2030 Introduction to Computer Engineering
Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech
2
Basic Shifting• Shift directions
– Left (multiply by 2)– Right (divide by 2)
• Take floor value if the result is not an integer• Floor value of XX (or X) is the greatest
integer number less than or equal to X, X, E.g. 5/2 = 2 -3/2 = -2
• Shift types– Logical (or unsigned) – Arithmetic (or signed)
3
Logical Shift
• Shift Left– MSB: Shifted out– LSB: Shifted in with a “0”– Examples:
• (11001011 << 1) = 10010110• (11001011 << 3) = 01011000
• Shift right– MSB: Shifted in with a “0”– LSB: Shifted out– Examples: (Some ISA use triple “>” for logical
right shift)• (11001011 >>> 1) = 01100101• (11001011 >>> 3) = 00011001
4
Arithmetic Shift
• Shift left– MSB: Shifted out, however, be aware of
overflow/underflow – LSB: Shifted in with a “0”– Examples:
• (1100 << 1) = 1000• (1100 << 3) = 0000 (Incorrect!) Underflow
• Shift right– MSB: Retain “sign bit” – LSB: Shifted out – Examples:
• (1100 >> 1) = 1110 (Retain sign bit)• (1100 >> 3) = 1111 (-4/8 = -1 ) Floor value of -0.5
5
Examples of Arithmetic Shift 1111 1011 Arithmetic shift right by 1
1111 1101
1111 1011 Arithmetic shift left by 1
1111 0110
1011 1111 (= -65) Arithmetic shift left by 1 (i.e. x2)
0111 1110 (= +126 -130) Underflow !
0100 0010 (= +66) Arithmetic shift left by 1 (i.e. x2)
1000 0100 (= -124 +132) Overflow !
Overflow/Underflow
6
4-bit Logical Shifter
S1 S0 D3 D2 D1 D0
0 X A3 A2 A1 A0
1 0 0 A3 A2 A1
1 1 A2 A1 A0 0
A3 A2 A1 A0
D3 D2 D1 D0
S/NS
S0
S1
L/R
101010
001201111
101301212
201313
ASSAS D
ASS ASS AS D
ASSASSAS D
ASSASD
7
4-bit Logical Shifter using 4-to-1 Mux
4-to-1 Mux
00 01 10 11s1
s0
S1 S0 D3 D2 D1 D0
0 X A3 A2 A1 A0
1 0 0 A3 A2 A1
1 1 A2 A1 A0 0
D3
A2A3
4-to-1 Mux
00 01 10 11s1
s0
D2
A1
4-to-1 Mux
00 01 10 11s1
s0
D1
A0
4-to-1 Mux
00 01 10 11s1
s0
D0S1
S0
Right Shift
Left Shift
8
4-bit Arithmetic Shifter w/ 4-to-1 Mux
4-to-1 Mux
00 01 10 11s1
s0
S1 S0 D3 D2 D1 D0
0 X A3 A2 A1 A0
1 0 A3A3 A3 A2 A1
1 1 A2 A1 A0 0
D3
A2A3
4-to-1 Mux
00 01 10 11s1
s0
D2
A1
4-to-1 Mux
00 01 10 11s1
s0
D1
A0
4-to-1 Mux
00 01 10 11s1
s0
D0S1
S0
Right Shift
Left Shift
9
4-bit Arithmetic Shifter w/ 4-to-1 Mux
4-to-1 Mux
00 01 10 11s1
s0
S1 S0 D3 D2 D1 D0
0 X A3 A2 A1 A0
1 0 A3A3 A3 A2 A1
1 1 A2 A1 A0 0
D3
A2A3
4-to-1 Mux
00 01 10 11s1
s0
D2
A1
4-to-1 Mux
00 01 10 11s1
s0
D1
A0
4-to-1 Mux
00 01 10 11s1
s0
D0S1
S0
Right Shift
Left ShiftOverflow/Overflow/UnderflowUnderflow
10
4-bit Arithmetic Shifter w/ 4-to-1 Mux
4-to-1 Mux
00 01 10 11s1
s0
S1 S0 D3 D2 D1 D0
0 X A3 A2 A1 A0
1 0 A3A3 A3 A2 A1
1 1 A2 A1 A0 0
D3
A2A3
4-to-1 Mux
00 01 10 11s1
s0
D2
A1
4-to-1 Mux
00 01 10 11s1
s0
D1
A0
4-to-1 Mux
00 01 10 11s1
s0
D0S1
S0
Right Shift
Left ShiftOverflow/Overflow/UnderflowUnderflow
OverflowUnderflow Detection
11
RotatorS1 S0 D3 D2 D1 D0
0 0 A3 A2 A1 A0
0 1 A0 A3 A2 A1
1 0 A1 A0 A3 A2
1 1 A2 A1 A0 A3
4-to-1 Mux
00 01 10 11s1
s0
D3
A2A3
4-to-1 Mux
00 01 10 11s1
s0
D2
A1
4-to-1 Mux
00 01 10 11s1
s0
D1
A0
4-to-1 Mux
00 01 10 11s1
s0
D0S1
S0
12
Barrel Shifter
S2 S1 S0 D3 D2 D1 D0
0 0 0 A3 A2 A1 A0
0 0 1 A3 A3 A2 A1
0 1 0 A3 A3 A3 A2
0 1 1 A3 A3 A3 A3
1 0 0 A3 A2 A1 A0
1 0 1 A2 A1 A0 0
1 1 0 A1 A0 0 0
1 1 1 A0 0 0 0
Shift multiple bitsmultiple bits at a time
Left Shift
Right Shift
13
Barrel Shifter Design w/ Mux (D3)S2 S1 S0 D
3D2
D1
D0
0 0 0 A3 A2 A1 A0
0 0 1 A3 A3 A2 A1
0 1 0 A3 A3 A3 A2
0 1 1 A3 A3 A3 A3
1 0 0 A3 A2 A1 A0
1 0 1 A2 A1 A0 0
1 1 0 A1 A0 0 0
1 1 1 A0 0 0 0
4-to-1 Mux
00 01 10 11s1
s0
00 01 10 11s1s04-to-1 Mux
2-to
-1 M
ux
2-to
-1 M
ux1
0 D3
A3
A3 A2 A1 A0
S0
S1
S2
Replicate and change wiring of the two 4-to-1 Muxes for D2, D1 and D0
14
Barrel Shifter Design Alternative (16-bit)
23 Shifter
22 Shifter
21 Shifter
20 Shifter
Left/Right
S3
S2
S1
S0
16
16
16
16
(S3 S2 S1 S0) specifies the “shift amount” in binary(S3 S2 S1 S0) specifies the “shift amount” in binary
16Output NumberOutput Number
Input NumberInput Number
15
Barrel Shifter Design w/ nMOSFET
D3
D2
D1
D0
A3
S=0(No Shift)
S=1 S=2 S=3
A2
A1
A0
S=3
S=2
S=1
16
A3A3A3
Barrel Shifter Design w/ nMOSFET
D3
D2
D1
D0
A3
S=0(No Shift)
S=1 S=2S=2 S=3
A2
A1
A0
S=3
S=2S=2
S=1
A3
A2
17
Barrel Shifter Design w/ nMOSFET
D3
D2
D1
D0
A3
S=0(No Shift)
S=1S=1 S=2 S=3
A2
A1
A0
S=3
S=2
S=1S=1
= A3
= A3
= A2
= A1
18
Unsigned Binary Multiply
101 (5)X 111 (7)---------- 101 101 101----------100011 (35)
19
Unsigned Integer Multiplier (2-bit)
s
00100111
1011
0001
01
01
ba baba ba
ba ba
ba ba
b b x
a a
2-bit by 2-bit
carrycarry out
p0
a0b0
H.A.
p1
c
s
a1b0a0b1
H.A.c
s
p2p3
a1b1
20
Unsigned Integer Multiplier (3-bit)
ba ba ba
ba ba ba
ba ba ba
b b b x
a a a
202122
101112
000102
012
012
3-bit by 3-bit
p0
a0b0
s
F.A.
p1
a1b0a0b1
0co
s
ci
c
F.A.
p2
s
a2b0a1b1
co
s
ci
c
F.A.
s
co
s
ci
a0b2
00
c
F.A.
p3
a2b1
co
s
ci
c
F.A.co
s
ci
a1b2
0
s
s
s
c
p4
c
F.A.co
s
ci
a2b2
p5
21
4-bit Unsigned Integer Multiplier
a0 b0
P0
a1 b0
a0 b1
++0
P1
a2 b0
a1 b1
++
a0 b2
++0
P2
a3 b0
a2 b1
++
a1 b2
++
a0 b3
++0
P3
a3 b1
++
a2 b2
++
a1 b3
++
0
P4
a3 b2
++
a2 b3
++
P5
a3 b3
++
P6P7
a0 b0
++CinCout
Sum
A B
Full AdderFull Adder
a0b0
22
Propagation Delay
a0 b0
P0
a1 b0
a0 b1
++0
P1
a2 b0
a1 b1
++
a0 b2
++0
P2
a3 b0
a2 b1
++
a1 b2
++
a0 b3
++0
P3
a3 b1
++
a2 b2
++
a1 b3
++
0
P4
a3 b2
++
a2 b3
++
P5
a3 b3
++
P6P7
1122
33
33
44
44
55
55
66
667788
4x4Delay = 8 adders
8x8Delay = 20 adders
23
a3 b3
++
P7 P6
Carry-Save Multiplier
a0 b0
P0
a1 b0
a0 b1
++0
P1
a2 b0
a1 b1
++
a0 b2
++
0
P2
a3 b0
a2 b1
++
a1 b2
++
a0 b3
++
0
P3
a3 b2
++
a2 b3
++
P5
a3 b1
++
a2 b2
a1 b3
++
++0
P4
24
Propagation Delay of Carry-Save Multiplier
a0 b0
P0
a3 b1
++
a2 b2
a1 b3
++
a3 b2
++
a2 b3
++
P5
a3 b3
++
P7
a1 b0
a0 b1
++0
P1
11
22
33 33
5566
4x4Delay = 6 adders
8x8Delay = 14 adders
a2 b0
a1 b1
++
a0 b2
++
0
P2
11
22
a3 b0
a2 b1
++
a1 b2
++
a0 b3
++
0
P3
11
22
33
++440
P6 P4
25
Signed Binary Multiply
When the Multiplicand is negativeWhen the Multiplicand is negative
11101 (-3) 01001 (+9) -------------------- 11111101 00 11101 -------------------- 11100101
Maintain the sign bits of the partial product
26
Signed Binary Multiply
When the Multiplier is negativeWhen the Multiplier is negative
01001 (+9) 11101 (-3) -------------------- 01001 01001 -------------------- 0101101 01001 -------------------- 01110101 10111 -------------------- 111100101 (-27)
At the last step, 2’s complement the multiplicand before adding
27
Signed Binary Multiply
When both the Multiplicand and Multiplier are negativeWhen both the Multiplicand and Multiplier are negative
10111 (-9) 11101 (-3) -------------------- 1110111 10111 -------------------- 11010011 10111 -------------------- 110001011 01001 -------------------- 000011011(+27)
At the last step, 2’s complement the multiplicand before adding
Maintain the sign bits of the partial product
28
More Examples (1)
1111 1010 (-6) 0000 0101 (+5) -------------------- 111111 1010 111110 10 -------------------- 1110 0010 (-30)
Assume 8-bit numbers
29
More Examples (2)
0011 (+3) 1110 (-2) -------------------- 0 0110 00 11 -------------------- 01 0010 110 1 -------------------- 1010 (-6)
Assume 4-bit numbers
30
More Examples (3)
1111 1100 (-4) 1110 0000 (-32) -------------------- 11 1111 1000 0000 11 1111 00 -------------------- 111 1110 1000 0000 000 0010 0 -------------------- 000 0000 1000 0000 (+128)
Assume 8-bit numbers
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