ECE2030 Introduction to Computer Engineering Lecture 9: Combinational Logic, Mixed Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering

ECE2030 Introduction to Computer Engineering

Lecture 9: Combinational Logic, Mixed Logic

Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee

School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering

Georgia TechGeorgia Tech

2

Logic Design• Logic circuits

– Combinational

– Sequential

Combinationalcircuits

Ninputs

Moutputs


inputs outputs

StorageElement

delaydelay

3

Combinational Logic

• Outputs, “at any time”, are determined by the input combination

• When input changed, output changed immediately– Note that real circuits are imperfect and have “propagation

delay”

• A combinational circuit – Performs logic operations that can be specified by a set of

Boolean expressions– Can be built hierarchically


Ninputs

Moutputs

4

Design Hierarchy Example

9-inputOdd Function

X0X1X2X3X4X5X6X7X8

Z

A0A1A2

3-inputOdd Function

ZA0A1A2

3-inputOdd Function

X3X4X5

A0A1A2

3-inputOdd Function

X6X7X8

B0

B0

A0A1A2

3-inputOdd Function

X0X1X2

B0

9-input Odd Function

How to design a 3-input Odd Function?

Function Specification:To detect odd numberof “1” inputs, i.e. Z=1 when there is an odd number of “1” present in the inputs

5

Derive Truth Table for Desired Functionality

A B C F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

00 01 11 10

0 0 1 0 1

1 1 0 1 0

ABC

CBA

C)(BA

)CBA(C)(BA

BC)CBA()CBCB(A

ABCCBACBACBAF

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Design Hierarchy Example

9-inputOdd Function

X0X1X2X3X4X5X6X7X8

Z

A0A1A2

3-inputOdd Function

ZA0A1A2

3-inputOdd Function

X3X4X5

A0A1A2

3-inputOdd Function

X6X7X8

B0

B0

A0A1A2

3-inputOdd Function

X0X1X2

B0

9-input Odd Function

3-input Odd function:B0=A0A1A2

A0

A1A2

B0

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Combinational Logic Design Example

DA BC D)C,B,F(A,

B

C

D

A

F

8

Mixed Logic• Enable component reuse

• Allow a digital logic circuit designer to implement a combinational logic with– Only NAND gates– Only NOR gates– Only NAND and NOR gates

9

DeMorgan’s Law

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Mixed Logic (1)• Implement all ORs in the Boolean

function• Implement all ANDs in the Boolean

function• Forget all the inversion at this

moment

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Example: Mixed Logic (1)

DA BC D)C,B,F(A,

B

C

D

A

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Mixed Logic (2)• Draw “Vertical Bars” in the circuits

where all complements in the Boolean equation occur

• Draw a bubble on each Vertical Bar

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DA BC D)C,B,F(A,

B

C

D

A

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Mixed Logic (3)• Convert each gate to the desired gate

– If only NAND gate is available, insert a bubble in front of the AND gate

– If only OR gate is available, insert a bubble in front of the OR gate

• Using DeMorgan’s Law in the process– OR NAND: by adding 2 bubbles on the

inputs side of OR– AND NOR: by adding 2 bubbles on the

inputs side of the AND

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DA BC D)C,B,F(A,

B

C

D

A

Assume this design uses Assume this design uses NANDNAND gatesgates only only

==

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Mixed Logic (4)• Balance the bubbles on each wire, i.e.

even out the number of bubbles on every wire

• If there is odd number of bubbles on a wire, add an inverter (i.e. a bubble)

• And remove those “vertical bars with bubbles” which are used to help only, not in the circuits

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DA BC D)C,B,F(A,

B

C

D

A


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How about Inverters?• Inverters can be implemented by either a

NAND or a NOR gate– Wiring the inputs together

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Example: Mixed Logic (Final)

DA BC D)C,B,F(A,

B

C

D

A


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DA BC D)C,B,F(A,

B

C

D

A


6 NAND gates are used6 NAND gates are used

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Mixed Logic• How about build the prior circuits with

only NOR gates?

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DA BC D)C,B,F(A,

B

C

D

A

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DA BC D)C,B,F(A,

B

C

D

A

Add vertical bar forAdd vertical bar foreach inversioneach inversion

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DA BC D)C,B,F(A,

B

C

D

A

Assume this design uses Assume this design uses NOR gatesNOR gates only only

==Convert each gate Convert each gate to a NORto a NOR

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DA BC D)C,B,F(A,

B

C

D

A


Balance number ofBalance number ofBubbles on each wire Bubbles on each wire

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DA BC D)C,B,F(A,


Balance number ofBalance number ofbubbles on each wire bubbles on each wire and substitute all gates and substitute all gates to NOR to NOR

B

C

D

A

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DA BC D)C,B,F(A,


B

C

D

A

7 NOR gates are used7 NOR gates are used

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Mixed Logic Example II (1)

))DC (B AC BAF

C

D

A

B

Implement the logic circuits by ignoring all inversionsImplement the logic circuits by ignoring all inversions

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))DC (B AC BAF

C

D

A

B

Add vertical bar/bubble for each inversionAdd vertical bar/bubble for each inversion

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))DC (B AC BAF

C

D

A

B


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))DC (B AC BAF

C

D

A

B

Balance the bubbles for each wire w/ invertersBalance the bubbles for each wire w/ inverters

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))DC (B AC BAF

C

D

A

B

Remove the vertical bars/bubblesRemove the vertical bars/bubbles

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))DC (B AC BAF

C

D

A

B

Replace all the gates to Replace all the gates to NAND gatesNAND gates

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))DC (B AC BAF

C

D

A

B

Final mixed logic uses 11 NAND gates Final mixed logic uses 11 NAND gates (one of them is a triple-input NAND gate)(one of them is a triple-input NAND gate)

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Mixed Logic Example III (1)

DB AC AF B

D

A

C

Implement the logic circuits by ignoring all inversionsImplement the logic circuits by ignoring all inversions

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DB AC AF B

D

A

C

Add vertical bar/bubble for each inversionAdd vertical bar/bubble for each inversion

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DB AC AF B

D

A

C


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DB AC AF B

D

A

C

Balance the bubbles for each wire w/ invertersBalance the bubbles for each wire w/ inverters

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DB AC AF B

D

A

C

Remove the vertical bars/bubblesRemove the vertical bars/bubbles

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DB AC AF B

D

A

C

Replace all the gates to Replace all the gates to NOR gatesNOR gates

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DB AC AF B

D

A

C

Final mixed logic uses 9 NOR gates Final mixed logic uses 9 NOR gates

Documents

ECE2030 Introduction to Computer Engineering Lecture 9: Combinational Logic, Mixed Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering