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Digital Integrated Circuits – EECS 312
http://robertdick.org/eecs312/
Teacher: Robert DickOffice: 2417-E EECSEmail: dickrp@umich.eduPhone: 734–763–3329Cellphone: 847–530–1824
GSI: Shengshou LuOffice: 2725 BBBEmail: luss@umich.edu
HW engineers SW engineers
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200 220 240 260 280 300
Cu
rre
nt
(mA
)
Time (seconds)
Typical Current Draw 1 sec Heartbeat
30 beats per sample
Sampling andRadio Transmission
9 - 15 mA
Heartbeat1 - 2 mA
Radio Receive for
Mesh Maintenance
2 - 6 mA
Low Power Sleep0.030 - 0.050 mA
Year of announcement
1950 1960 1970 1980 1990 2000 2010
Pow
er d
ensi
ty (
Wat
ts/c
m2 )
0
2
4
6
8
10
12
14
Bipolar
CMOS
VacuumIBM 360
IBM 370 IBM 3033
IBM ES9000
Fujitsu VP2000
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
CDC Cyber 205IBM 4381
IBM 3081Fujitsu M380
IBM RY5
IBM GP
IBM RY6
Apache
Pulsar
Merced
IBM RY7
IBM RY4
Pentium II(DSIP)
T-Rex
Squadrons
Pentium 4
Mckinley
Prescott
Jayhawk(dual)
IBM Z9
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Review
What are the historical motivations that have driven changes indigital device implementation technologies?
What is the difference between a combinational and sequentialnetwork?
What substrates (device types) have been used for computation?
What are the primary advantages of integrated circuits over thesecompeting technologies?
2 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Lecture plan
1. Recent history of digital integrated circuits
2. Digital device requirements
3. Introduction to Cadence tools
4. Homework
3 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Remember the ENIAC?
1946.
18,000 vacuum tubes.
30 tons.
100 kHz.
Unreliable.
What impact would ICs have on it?
4 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
IC ENIAC
30 tons → 40 mm2.
100 kHz → 20 MHz.
Unreliable.
5 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
First microprocessor
Intel 4004.
1971.
2,300 transistors.
12 mm2.
740 kHz.
12-bit addresses, 8-bitinstructions, 4-bit data words.
6 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Trend for one company
More than ten generations.
Datapath: 4 bits → 64 bits.
Frequency: 740 KHz →3 GHz.
In-order, cache-less →Architectural features forcommon-case performance.
Uni-processor →Chip-multiprocessor (CMP).
A few thousand transistors →Billions of transistors.
7 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Moore’s law
1965.
The number of transistors in an IC doubles every 18–24 months.
8 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Actual trend
9 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Feature size trends
10 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Logic density trends
11 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Frequency trends
Technology scaling ↓ delay by 30% and ↑ frequency by 43%.
Frequency ∝ 1/Delay.
12 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Power trends
13 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Power density trends
Year of announcement
1950 1960 1970 1980 1990 2000 2010
Pow
er d
ensi
ty (
Wat
ts/c
m2 )
0
2
4
6
8
10
12
14
Bipolar
CMOS
VacuumIBM 360
IBM 370 IBM 3033
IBM ES9000
Fujitsu VP2000
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
CDC Cyber 205IBM 4381
IBM 3081Fujitsu M380
IBM RY5
IBM GP
IBM RY6
Apache
Pulsar
Merced
IBM RY7
IBM RY4
Pentium II(DSIP)
T-Rex
Squadrons
Pentium 4
Mckinley
Prescott
Jayhawk(dual)
IBM Z9
14 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Power supply trends
15 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Productivity trends
16 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Impact of power consumption and temperature
Early ICs used bipolar transistors (BJT).
Easier to manufacture reliably, faster.
In the 1970s, integration densities rose.
Each bipolar device consumes a lot of power.
Eventually power became the limiting factor in moving from BJTto MOS devices.
Currently CMOS dominates.
Complementary MOS logic.
Likely to dominate for the next decade.
17 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Power consumption trends
Initial optimization at transistor level.
Further research-driven gains at this level difficult.
Research moved to higher levels, e.g., RTL.
Trade area for performance and performance for power.
Clock frequency gains linear.
Voltage scaling VDD2 – important.
18 Robert Dick Digital Integrated Circuits
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C · VDD2 · f · A
† PSHORT =b
12(VDD − 2 · VT )3 · f · A · t
PLEAK = VDD · (ISUB + IGATE + IJUNCTION + IGIDL)
C : total switched capacitance VDD : high voltage
f : switching frequency A : switching activity
b : MOS transistor gain VT : threshold voltage
t : rise/fall time of inputs
† PSHORT usually ≤ 10% of PSWITCH
Smaller as VDD → VT
A < 0.5 for combinational nodes, 1 for clocked nodes.
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Wiring power consumption
In the past, transistor power � wiring power.
Process scaling ⇒ ratio changing.
20 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Other (related) design trends
Smaller transistors.
Bigger chips (die).
Lower power consumption.
Higher clock frequencies.
More complex designs.
Lower voltage.
21 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Other (related) design trends
Smaller transistors.
Bigger chips (die).
Lower power consumption.
Higher clock frequencies.
More complex designs.
Lower voltage.
More cores.
Some of these trends are slowing.
22 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Current status
Feature size: 22 nm.
Integration: 700,000,000 transistors.
Frequency: 2-4 GHz.
Power: 100 W.
Only two of these characteristics have changes in the past few years.
23 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Current status
Feature size: 22 nm.
Integration: 700,000,000 transistors.
Frequency: 2-4 GHz.
Power: 100 W.
Only two of these characteristics have changes in the past few years.
23 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Multi-core processors
Intel Core 2 Duo
24 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Summary of recent IC history
Process scaling improves device count, speed.
Power density increases, eventually limiting further improvements.
Current move to multi-core.
Also considering new device technologies, but no clear winnersnow.
25 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Lecture plan
1. Recent history of digital integrated circuits
2. Digital device requirements
3. Introduction to Cadence tools
4. Homework
26 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Levels of abstraction
Hardware–software system.
Processor.
Functional unit.
Logic stage: flip-flop or combinational logic network.
Gate.
Transistor or wire.
Physical material or doping regions.
Derive and explain.
27 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
What properties must a “digital” device have?
What allows us to treat a device as digital, and still have thesystem work?
Does this imply certain properties for the transfer function?
28 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Transfer function
Vout
Vin
29 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Transfer function
Vout
Vin
29 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Transfer function
Vout
Vin
29 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Transfer function
Vout
Vin
29 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Completeness
Technology should support implementation of arbitrary Booleanfunctions.
Consider {AND2, OR2} and {NAND2}.
Derive and explain.
30 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS
Metal Oxide Semiconductor
Positive and negative carriers
Complimentary MOS
PMOS gates are like normally closed switches that are good attransmitting only true (high) signals
NMOS gates are like normally open switches that are good attransmitting only false (low) signals
31 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS
Metal Oxide Semiconductor
Positive and negative carriers
Complimentary MOS
PMOS gates are like normally closed switches that are good attransmitting only true (high) signals
NMOS gates are like normally open switches that are good attransmitting only false (low) signals
31 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS
Metal Oxide Semiconductor
Positive and negative carriers
Complimentary MOS
PMOS gates are like normally closed switches that are good attransmitting only true (high) signals
NMOS gates are like normally open switches that are good attransmitting only false (low) signals
31 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
NMOSFET
gate
silicon bulk (P)
drain (N)source (N)
dielectric
gate
silicon bulk (P)
drain (N)source (N) channel
dielectric
32 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
NMOSFET
gate
silicon bulk (P)
drain (N)source (N)
dielectric
gate
silicon bulk (P)
drain (N)source (N) channel
dielectric
32 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS
NMOS turns on when the gate is high
PMOS just like NMOS, with N and P regions swapped
PMOS turns on when the gate is low
NMOS good at conducting low (0s)
PMOS good at conducting high (1s)
Use NMOS and PMOS transistors together to build circuits
Complementary metal oxide semiconductor (CMOS)
33 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS NAND gate
VSS
VDD
A B
Z
VSS
VDD
A B
Z
PMOS
NMOS
VSS
VDD
A B
Z
VSS
VDD
A B
Z
pull−up network
pull−down network
34 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS NAND gate
VSS
VDD
A B
Z
VSS
VDD
A B
Z
PMOS
NMOS
VSS
VDD
A B
Z
VSS
VDD
A B
Z
pull−up network
pull−down network
34 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS NAND gate
VSS
VDD
A B
Z
VSS
VDD
A B
Z
PMOS
NMOS
VSS
VDD
A B
Z
VSS
VDD
A B
Z
pull−up network
pull−down network
34 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
CMOS NAND gate
VSS
VDD
A B
Z
VSS
VDD
A B
Z
PMOS
NMOS
VSS
VDD
A B
Z
VSS
VDD
A B
Z
pull−up network
pull−down network
34 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
What is this?
35 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
What is this? How would we lay it out?
VDD
VSS
A B
36 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Non-Credit quiz on material covered so far
1 History of integrated circuits.1 What happens as a result of process scaling?2 What have the motivations for major changes in device technology
been?3 What is a digital system?4 What is a general-purpose computer?5 What is an embedded system?6 What is an integrated circuit?7 What is an ASIC?8 What is an instruction processor?9 What is an FPGA?
2 What gate properties support use in digital systems?1 What properties should Vout–Vin curve have?2 Describe completeness.
37 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Upcoming topics
Enough overview: time to start building!
Diodes
Transistor static behavior
Transistor dynamic behavior
38 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Lecture plan
1. Recent history of digital integrated circuits
2. Digital device requirements
3. Introduction to Cadence tools
4. Homework
39 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Lab one challenges
Learning to use the tools (Friday).
Understanding the circuits used in the lab (Tuesday).
A note on the CAD tools market.
Derive and explain.
40 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
NMOS inverter schematic
41 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
NMOS inverter simulation results
42 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Upcoming topics
6 September: Discussion in room 1620 BBB will focus on Lab 1.
10 September: MOSFETs.
43 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Lecture plan
1. Recent history of digital integrated circuits
2. Digital device requirements
3. Introduction to Cadence tools
4. Homework
44 Robert Dick Digital Integrated Circuits
Recent history of digital integrated circuitsDigital device requirements
Introduction to Cadence toolsHomework
Homework assignment and announcement
5 September: Email topics of interest.
10 September: Read Sections 3.1, 3.2, and 3.3.1 in J. Rabaey,
A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: ADesign Perspective.Prentice-Hall, second edition, 2003.
17 September: Laboratory assignment one.
45 Robert Dick Digital Integrated Circuits
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