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Continuous-time delta-sigma modulator
using vector filter in feedback path to reduce
effect of clock jitter and excess loop delay
Yuki Kimura Akira Yasuda Michitaka Yoshino
Engineering research course University of Hosei
Tokyo Japan
Table of Contents
Ⅰ. Research Introduction
Ⅱ. The difference of CTDSM and DTDSM
Ⅲ. Advantages and disadvantages of the CTDSM
Ⅳ. Proposed method
Ⅴ. Simulation result (MATLAB/Simulink)
Ⅵ. Conclusion
Ⅰ. Research Introduction
The one of the candidates “High-Precision and High-Speed ADC”
Continuous-time delta-sigma modulator (CTDSM)
Conversion speed[Hz]
Res
olu
tion
[bit
s]
ΔΣ ADC
SAR ADC
Flash ADC
Pipeline ADC
●Conversion speed
1[MHz]~100[MHz]
●Resolution
12~20[bits]
Ⅱ. The difference of CTDSM and DTDSM
Differences in circuit-architecture of Integrator
OTA
CT-Integrator DT-Integrator
R-C Integrator Gm-C Integrator SC Integrator
CT-Integrator operation is “switch-less”
Ⅲ. Advantages and disadvantages of the CTDSM
●Advantages1
Speedup of DSM by CT-Integrator
Output of CT-Integrator changes gently
●Advantages2
Ⅲ. Advantages and disadvantages of the CTDSM
Relax Characteristic of Anti-aliasing-filter
Input
DAC
Loop-filterOutputComparator F・F
Circuit
Folding-noise is shaped by Loop-filter
Folding-noise
Ideal sample point
High
Low
Error sample point
High
Low
Ideal sample point
Output current of DAC (CTDSM)
Output current of DAC (DTDSM)
Ⅲ. Advantages and disadvantages of the CTDSM
●Disadvantages1
“Electron charge to integrator” is changed
clock edge is changed
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
gain
[dB
]
Normalized frequency[Hz]
Output of DAC (Conventional CTDSM)Clock-jitter Noise
Ⅲ. Advantages and disadvantages of the CTDSM
From a different point of view
Add to Clock-jitter noise
Phase-modulation caused
Random clock jitter down-converts
quantization noise to signal band
Input
DAC
Loop-filterOutputComparator F・F
Circuit
Ⅲ. Advantages and disadvantages of the CTDSM
●Disadvantages2
Time-constant
Slew rate limit
Phase lag
CTDSM becomes unstable SNR deteriorates
Propagation Delay
Ⅳ. Proposed method
Input
DAC
Loop-filterOutputComparator F・F
Circuit
VectorFilter×
Vector Filter is used in feedback path
Vector Filter can realize the characteristic of
a low-pass and a high-pass filter
DSM-VF(The DSM using Vector filter in Feedback path)
Ⅳ. Proposed method
VectorFilter× z
1Input
XOutput
Y
0.5
0.5
・ ・
・
One clock delay exists between the input of Vector Filter
Vector operation
Ⅳ. Proposed method
Design of DSM-VF (CT-model)
Step1 DSM-VF is designed by DT-model
Input
DAC1
0.5
0.5
DAC2 z1
DAC3
DAC4
z1
Output
z1
z1
ba c
d
Vector Filter
The poles of system are located at the origin in this design.
Ⅳ. Proposed method
Step2 Conversion from DT-model to CT-model
Using “Bilinear-transform”
InputS
1
DAC1
DAC5 0.5
0.5
DAC2 z1
DAC3
S
1
DAC4
z1
Output
a
e
c h
bd f
g
i
“Bilinear-transform” is a method used for converting
the DT-model into the CT-model.
10-4
10-3
10-2
10-1
100
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
gain
[dB
]
Normalized frequency[Hz]
Continuous-time-modelDiscrete-time-model
Ⅳ. Proposed method
Noise-shaping-characteristic is same
Parameters Result(DT) Result(CT)
Input Level -6[dBFS] -6[dBFS]
Sampling
Frequency
(Normalized)
1[Hz] 1[Hz]
OSR 128 128
SNR 85.2[dB] 84.8[dB]
ENOB 13.9[bits] 13.8[bits]
DT model and the CT model exhibit
equivalent noise shaping and SNR characteristics
InputS
1
DAC1
DAC5 0.5
0.5
DAC2 z1
DAC3
S
1
DAC4
z1
Output
a
e
c h
bd f
g
i
Output spectrum of Vector Filter
Ⅳ. Proposed method
Toward DAC1 and DAC5 Toward DAC2
10-4
10-3
10-2
10-1
100
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
gain
[dB
]
Normalized frequency[Hz]
From Vector Filter YL
Output spectrum of path toward DAC1 and DAC5
Ⅳ. Proposed method
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
gain
[dB
]
Normalized frequency[Hz]
From Vector Filter YL
Low-pass signal reduces influence of clock-jitter
Down-converted quantization-noise is suppressed
Ⅳ. Proposed method
Output spectrum of path toward DAC2
10-4
10-3
10-2
10-1
100
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0ga
in[d
B]
Normalized frequency[Hz]
From Vector Filter YH
Ⅳ. Proposed method
Ⅳ. Proposed method
InputS
1
DAC1
DAC5 0.5
0.5
DAC2 z1
DAC3
S
1
DAC4
z1
Output
a
e
c h
bd f
g
i
High pass signal improves influence of excess loop delay
High pass signal can realize phase compensation
Ⅴ. Simulation result (MATLAB/Simulink)
10-4
10-3
10-2
10-1
100
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
gain
[dB
]
Normalized frequency[Hz]
ConventionalDSM-VF
Parameters Conventional Proposed
(CT model)
Clock Jitter 0.1[%] 0.1[%] Input level -6[dBFs] -6[dBFs] Sampling
Frequency (Normalized)
1[Hz] 1[Hz]
OSR 128 128 plot 2^15 2^15
Signal Noise Ratio 61.7[dB] 84.2[dB] ENOB 10.0[bit] 13.7[bit]
Vector-filter can suppress influence of clock-jitter
SNR is improved by 22.5dB
Ⅴ. Simulation result (MATLAB/Simulink)
SNR deterioration of DSM-VF is approximately 10 dB
less than that for the system with low pass filter
Ⅵ. Conclusion
Input
DAC
Loop-filterOutputComparator F・F
Circuit
VectorFilter×
DSM-VF(The DSM using Vector filter in Feedback path)
SNR is improved by 22.5dB
SNR is improved by 10dB
Thank you for your attention
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