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Configurable System-on-Chip: Xilinx EDK. Enno Lübbers Computer Engineering Group University of Paderborn enno.luebbers@uni-paderborn.de. EPROM. Field-Programmable Gate Arrays (FPGAs). Fine-grained reconfigurable hardware - PowerPoint PPT Presentation
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Configurable System-on-Chip: Xilinx EDK
Enno LübbersComputer Engineering GroupUniversity of Paderborn
enno.luebbers@uni-paderborn.de
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Field-Programmable Gate Arrays (FPGAs)
Fine-grained reconfigurable hardware Gate-Array: regular structure of “logic cells”, connected
through an interconnection network Configuration stored in SRAM, must be loaded on startup
EP
RO
M
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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FPGA toolflow
HDL (VHDL /Verilog)
HDL (VHDL /Verilog)
SynthesizeSynthesize
NetlistNetlist
MapMap
PlacePlace
RouteRoute
BitstreamBitstream
Hardware design is traditionally done by modeling the system in a hardware description language
An FPGA “compiler” (synthesis tool) generates a netlist,
which is then mapped to the FPGA technology,
the inferred components are placed on the chip,
and the connecting signals are routed through the interconnection network.
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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HDL Synthesis
RegisterRegister
aabb
outputoutput
clkclk
resetreset
clearclear
DD QQ
process(clk, reset)
begin
if reset = ‚1‘ thenoutput <= ‚0‘;
elsif rising_edge(clk) thenoutput <= a XOR b;
end if;
end process;
HDL (VHDL /Verilog)
HDL (VHDL /Verilog)
SynthesizeSynthesize
NetlistNetlist
MapMap
PlacePlace
RouteRoute
BitstreamBitstream
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Technology Mapping
HDL (VHDL /Verilog)
HDL (VHDL /Verilog)
SynthesizeSynthesize
NetlistNetlist
MapMap
PlacePlace
RouteRoute
BitstreamBitstream
RegisterRegister
aabb
outputoutput
clkclk
resetreset
clearclear
DD QQ
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Place & Route
HDL (VHDL /Verilog)
HDL (VHDL /Verilog)
SynthesizeSynthesize
NetlistNetlist
MapMap
PlacePlace
RouteRoute
BitstreamBitstream
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Xilinx ISE
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Traditional Embedded System
Power SupplyCLKCLK
CLKcustomIF-logic
SDRAM SDRAMSRAM SRAMSRAM
Memory Controller
UARTLC
DisplayController
InterruptController Timer
AudioCodec
CPU(uP / DSP) Co-
Proc.
GP I/O
AddressDecode
Unit
EthernetMAC
Images by H.Walder
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Traditional Embedded System
FPGACLKCLK
CLKcustomIF-logic
SDRAM SDRAMSRAM SRAMSRAM
Memory Controller
UART
DisplayController
Timer
Power Supply
LC
AudioCodec
CPU(uP / DSP) Co-
Proc.
GP I/O
AddressDecode
Unit
EthernetMAC
InterruptController
Images by H.Walder
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Configurable System on Chip (CSoC)
Power Supply
SDRAM SDRAMSRAM SRAMSRAM
LC
AudioCodec EPROM
Images by H.Walder
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Advantages
Fewer physical components
Shorter development cycles
Field-programmable (updates, new features...)
Possibly higher performance through on-chip integration Signals on a chip can typically be clocked higher than signals across
board traces Optimization between modules possible
Partial reconfigurability Exchange peripherals while the rest of the system keeps running
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Embedded CPUs
PowerPC 405 (hard core) 32 bit embedded PowerPC RISC architecture Up to 450 MHz 2x 16 kB instruction and data caches Memory management unit (MMU) Hardware multiply and divide Coprocessor interface (APU) Embedded in Virtex-II Pro and Virtex-4 PLB and OCM bus interfaces
MicroBlaze (soft core) 32 bit RISC architecture 2-64 kB instruction and data caches Barrel Shifter Hardware multiply and divide OPB and LMB bus interfaces
Others NIOS (Altera), ARM, PicoBlaze (Xilinx), ...
Images by Xilinx
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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CoreConnect Bus Architecture
Flexible bus architecture for embedded Systems and SoCs Developed by IBM Used by Xilinx EDK
Processor Local Bus (PLB) On-Chip Peripheral Bus (OPB) Device Control Register Bus
(DCR)
Alternatives: AMBA (Altera) Wishbone (OpenCores) Proprietary bus architectures
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Bus Configurations
Images by H.Walder
LMB: Local Memory Bus (for on-chip memory)OPB: On-Chip Peripheral Bus
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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CSoC Design Flow (Hardware)
HDL (VHDL /Verilog)
HDL (VHDL /Verilog)
SynthesizeSynthesize
NetlistNetlist
MapMap
PlacePlace
RouteRoute
BitstreamBitstream
Platform description is translated/assembled into netlist, which in turn is either
mapped, placed and routed onto FPGA, or
Platform Description
Platform Description
Netlist Generation
Netlist Generation
NetlistNetlist
BitstreamBitstream
Xilinx ISE(VHDL Edit, Map, Place & Route)
Xilinx ISE(VHDL Edit, Map, Place & Route)
XST(Map, Place & Route)
XST(Map, Place & Route)
VHDL
VHDL
imported into ISE and used in a larger FPGA design
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
16 FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
Platform Description
Platform Description
Netlist Generation
Netlist Generation
NetlistNetlist
BitstreamBitstream
Xilinx ISE(VHDL Edit, Map, Place & Route)
Xilinx ISE(VHDL Edit, Map, Place & Route)
XST(Map, Place & Route)
XST(Map, Place & Route)
VHDL
VHDL
CSoC Design Flow (Hardware)
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CSoC Design Flow (Software)
Platform Description
Platform Description
Netlist Generation
Netlist Generation
NetlistNetlist
BitstreamBitstream
XST or ISE(Map, Place & Route)
XST or ISE(Map, Place & Route)
Compile & Link
Compile & Link
Update BitstreamUpdate
Bitstream
Bitstream with
executable Code
Bitstream with
executable Code
Program
*.elf
*.aLibrary
GenerationLibrary
Generation*.h *.h *.c
User sources
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
18 FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
CSoC Design Flow (Software)
Platform Description
Platform Description
Netlist Generation
Netlist Generation
NetlistNetlist
BitstreamBitstream
XST or ISE(Map, Place & Route)
XST or ISE(Map, Place & Route)
Compile & Link
Compile & Link
Update BitstreamUpdate
Bitstream
Bitstream with
executable Code
Bitstream with
executable Code
Program
*.elf
*.aLibrary
GenerationLibrary
Generation*.h *.h *.c
User sources
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Demonstration
Simple System: LED Counter Bus Configuration:
MicroBlaze CPU Instruction- and data memories
attached to local memory buses General Purpose I/O (GPIO)
attached to data-side OPB
Target: Xilinx Spartan-III (XC3S200) 200’000 gates (4’320 logic cells) 480 CLBs (24 x 20) 216 Kbits Block RAM 173 User I/O pins 12 18x18 bit multipliers
MicroBlaze CPU Core
DOPB
DLMBILMB
GP I/O
BRAM
Image by H.Walder
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Demonstration
Spartan III FPGA
50 MHz clock(back side)
7-segment display
E14
G13F13N16
N15
P16P15
R16
Reset button
CLK
RST LED0
LED7
Image by H.Walder
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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Questions?
More information on Xilinx FPGAs and design tools http://www.xilinx.com http://www.xilinx.com/edk
Student projects / Thesises (DA/SA/BA/MA) Enno Lübbers
P1.7.08.4enno.luebbers@upb.de
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
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