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Figure 11 Graph of an analog quantity (temperature versus time).
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
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Figure 12 Sampled-value representation (quantization) of the analog quantity in Figure 11. Each value represented by a dot can be
digitized byrepresenting it as a digital code that consists of a series of 1s and 0s.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
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Figure 13 A basic audio public address system.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
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Figure 14 Basic block diagram of a CD player. Only one channel is shown.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 15 Logic level ranges of voltage for a digital circuit.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 16 Ideal pulses.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 17 Nonideal pulse characteristics.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 18 Examples of digital waveforms.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 19
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 110 Example of a clock waveform synchronized with a waveform representation of a sequence of bits.
Thomas L. FloydDigital Fundamentals, 9e
Copyright
2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
All rights reserved.
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Figure 111 Example of a timing diagram.
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 112 Illustration of serial and parallel transfer of binary data. Only the data lines are shown.
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 113
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 114
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 115 The basic logic operations and symbols.
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 116 The NOT operation.
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 117 The AND operation.
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 118 The OR operation.
Thomas L. FloydDigital Fundamentals, 9e
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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458
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Figure 119 The comparison function.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 120 The addition function.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 121 An encoder used to encode a calculator keystroke into a binary code for storage or for calculation.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 122 A decoder used to convert a special binary code into a 7-segment decimal readout.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 123 Illustration of a basic multiplexing/demultiplexing application.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 124 Example of the operation of a 4-bit serial shift register. Each block represents one storage cell or flip-flop.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 125 Example of the operation of a 4-bit parallel shift register.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
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Figure 126 Illustration of basic counter operation.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 127 Cutaway view of one type of fixed-function IC package showing the chip mounted inside, with connections to input and
output pins.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 128 Examples of through-hole and surface-mounted devices. The DIP is larger than the SOIC with the same number of leads.
This particularDIP is approximately 0.785 in. long, and the SOIC is approximately 0.385 in. long.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 129 Examples of SMT package configurations.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 130 Pin numbering for two standard types of IC packages. Top views are shown.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 131 Programmable logic.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 132 Block diagrams of simple programmable logic devices (SPLDs).
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 133 Typical SPLD package.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 134 General block diagram of a CPLD.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 135 Typical CPLD packages.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
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Figure 136 Basic structure of an FPGA.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 137 A typical ball-grid array package configuration.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 138 Basic configuration for programming a PLD or FPGA.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 139 Basic programmable logic design flow block diagram.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 140 A typical dual-channel oscilloscope. Used with permission from Tektronix, Inc.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 141 Comparison of analog and digital oscilloscopes.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 142 Block diagram of an analog oscilloscope.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 143 Block diagram of a digital oscilloscope.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Fig re 1 44 A t i l d l h l ill N b b l i di t th l f h di i i th ti l ( lt )
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Figure 144 A typical dual-channel oscilloscope. Numbers below screen indicate the values for each division on the vertical (voltage)
and horizontal(time) scales and can be varied using the vertical and horizontal controls on the scope.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 145 Comparison of an untriggered and a triggered waveform on an oscilloscope.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 146 Displays of the same waveform having a dc component.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 147 An oscilloscope voltage probe. Used with permission from Tektronix, Inc.
Thomas L. FloydDigital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 148 Probe compensation conditions.
Thomas L. FloydDigital Fundamentals, 9e
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Figure 149
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
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Figure 150 Typical logic analyzer. Used with permission from Tektronix, Inc.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Fi 1 51 Si lifi d bl k di f l i l
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Figure 151 Simplified block diagram of a logic analyzer.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Fi 1 52 T l i l di l d
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Figure 152 Two logic analyzer display modes.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Fi 1 53 A t i l lti h l l i l b U d ith i i f T kt i I
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Figure 153 A typical multichannel logic analyzer probe. Used with permission from Tektronix, Inc.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Fi 1 54 T i l i l t U d ith i i f T kt i I
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Figure 154 Typical signal generators. Used with permission from Tektronix, Inc.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 155 Illustration of how a logic pulser and a logic probe can be used to apply a pulse to a given point and check for resulting
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g g p g p pp y p g p g
pulse activity atanother part of the circuit.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 1 56 Typical dc power supplies Courtesy of B+K Precision
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Figure 156 Typical dc power supplies. Courtesy of B+K Precision.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 1 57 Typical DMMs Courtesy of B+K Precision
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Figure 157 Typical DMMs. Courtesy of B+K Precision.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 158 Simplified basic block diagram for a tablet-counting and bottling control system
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Figure 158 Simplified basic block diagram for a tablet-counting and bottling control system.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 159
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Figure 159
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 160
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Figure 1 60
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 161
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Figure 1 61
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 162
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Figure 1 62
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 163
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g
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright 2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458All rights reserved.
Figure 164
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g
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