Binary Adder DesignSpring 2003 1 Binary Adders. Binary Adder DesignSpring 2003 2 n-bit Addition...

Binary Adder Design Spring 2003 1

Binary Adders

Binary Adder Design Spring 2003 2

n-bit Addition

– Ripple Carry Adder

– Conditional Sum Adder

– (Carry Lookahead Adder)

Binary Adder Design Spring 2003 3

Ripple Carry Adder

incnbnans ]0:1[]0:1[]0:[

Binary Adder Design Spring 2003 4

Ripple Carry Adder

in

in

in

cbanbna

cbnbana

cnbnans

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

11

11

Binary Adder Design Spring 2003 5

Ripple Carry Adder

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

11

11

11

scnbna

cbanbna

cbnbana

cnbnans

in

in

in

Binary Adder Design Spring 2003 6

Ripple Carry Adder

]0[2]1[]1:1[]1:1[

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

1

11

11

11

scnbna

scnbna

cbanbna

cbnbana

cnbnans

in

in

in

Binary Adder Design Spring 2003 7

Ripple Carry Adder

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[]1:1[]1:1[

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

1

1

11

11

11

sscnbna

scnbna

scnbna

cbanbna

cbnbana

cnbnans

in

in

in

Binary Adder Design Spring 2003 8

Ripple Carry Adder

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[]1:1[]1:1[

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

12

1

1

11

11

11

sscnbna

sscnbna

scnbna

scnbna

cbanbna

cbnbana

cnbnans

in

in

in

Binary Adder Design Spring 2003 9

Ripple Carry Adder

]0:1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[]1:1[]1:1[

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

2

12

1

1

11

11

11

scnbna

sscnbna

sscnbna

scnbna

scnbna

cbanbna

cbnbana

cnbnans

in

in

in

Binary Adder Design Spring 2003 10

Ripple Carry Adder

]0:1[2][]:1[]:1[

]0:1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[]1:1[]1:1[

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

2

12

1

1

11

11

11

kskcknbkna

scnbna

sscnbna

sscnbna

scnbna

scnbna

cbanbna

cbnbana

cnbnans

k

in

in

in

Binary Adder Design Spring 2003 11

Ripple Carry Adder

])0:1[],[(

]0:1[2][]:1[]:1[

]0:1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[2]2[]2:1[]2:1[

]0[2]1[]1:1[]1:1[

])0[],1[(2]1:1[2]1:1[

]0[]0[2]1:1[2]1:1[

]0[2]1:1[]0[2]1:1[

]0:1[]0:1[]0:[

2

12

1

1

11

11

11

nsnc

kskcknbkna

scnbna

sscnbna

sscnbna

scnbna

scnbna

cbanbna

cbnbana

cnbnans

k

in

in

in

Binary Adder Design Spring 2003 12

Ripple Carry Adder

)192(128)32()(

)448(480)32()(

RCA

FARCA

RCA

FARCA

DDnnD

CCnnC

Binary Adder Design Spring 2003 13

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

incnbnans ]0:1[]0:1[]0:[

Binary Adder Design Spring 2003 14

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

innn

in

cnbnnbnanna

cnbnans

]0:12/[2]2/:1[]0:12/[2]2/:1[

]0:1[]0:1[]0:[2/2/

Binary Adder Design Spring 2003 15

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

inn

innn

in

cnbnannbnna

cnbnnbnanna

cnbnans

]0:12/[]0:12/[2]2/:1[]2/:1[

]0:12/[2]2/:1[]0:12/[2]2/:1[

]0:1[]0:1[]0:[

2/

2/2/

Binary Adder Design Spring 2003 16

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

])0:12/[],2/[(2]2/:1[]2/:1[

]0:12/[]0:12/[2]2/:1[]2/:1[

]0:12/[2]2/:1[]0:12/[2]2/:1[

]0:1[]0:1[]0:[

2/

2/

2/2/

nsncnnbnna

cnbnannbnna

cnbnnbnanna

cnbnans

nin

nin

nnin

Binary Adder Design Spring 2003 17

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

]0:12/[2]2/[2]2/:1[]2/:1[

])0:12/[],2/[(2]2/:1[]2/:1[

]0:12/[]0:12/[2]2/:1[]2/:1[

]0:12/[2]2/:1[]0:12/[2]2/:1[

]0:1[]0:1[]0:[

2/2/

2/

2/

2/2/

nsncnnbnna

nsncnnbnna

cnbnannbnna

cnbnnbnanna

cnbnans

nn

nin

nin

nnin

Binary Adder Design Spring 2003 18

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

]0:12/[2]2/[]2/:1[]2/:1[

]0:12/[2]2/[2]2/:1[]2/:1[

])0:12/[],2/[(2]2/:1[]2/:1[

]0:12/[]0:12/[2]2/:1[]2/:1[

]0:12/[2]2/:1[]0:12/[2]2/:1[

]0:1[]0:1[]0:[

2/

2/2/

2/

2/

2/2/

nsncnnbnna

nsncnnbnna

nsncnnbnna

cnbnannbnna

cnbnnbnanna

cnbnans

n

nn

nin

nin

nnin

Binary Adder Design Spring 2003 19

Conditional Sum Adder

Main principle: pre-computing upper sums for the cases: c[k]=1 and c[k]=0

Assume n is power of 2:

1]2/[

0]2/[

1]2/:1[]2/:1[

]2/:1[]2/:1[2]0:12/[

]0:12/[2]2/[]2/:1[]2/:1[

]0:12/[2]2/[2]2/:1[]2/:1[

])0:12/[],2/[(2]2/:1[]2/:1[

]0:12/[]0:12/[2]2/:1[]2/:1[

]0:12/[2]2/:1[]0:12/[2]2/:1[

]0:1[]0:1[]0:[

2/

2/

2/2/

2/

2/

2/2/

nc

nc

if

if

nnbnna

nnbnnans

nsncnnbnna

nsncnnbnna

nsncnnbnna

cnbnannbnna

cnbnnbnanna

cnbnans

n

n

nn

nin

nin

nnin

Binary Adder Design Spring 2003 20

Conditional Sum Adder

Binary Adder Design Spring 2003 21

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

Binary Adder Design Spring 2003 22

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

MUXCSACSA DnDnD )2/()(

Binary Adder Design Spring 2003 23

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

MUXFA

MUXCSACSADnD

DnDnD

)(log

)2/()(

2

Binary Adder Design Spring 2003 24

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

)16(14)32(

)(log)2/()(

2

CSA

MUXFA

MUXCSACSA

D

DnDDnDnD

Binary Adder Design Spring 2003 25

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

MUXCSACSA CnnCnC )12/()2/(3)(

Binary Adder Design Spring 2003 26

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

)1(3

)12/()2/(3)()(log2

CSAn

MUXCSACSA

C

CnnCnC

Binary Adder Design Spring 2003 27

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

FAn

CSAn

MUXCSACSA

C

C

CnnCnC

)(log

)(log

2

2

3

)1(3

)12/()2/(3)(

Binary Adder Design Spring 2003 28

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

FAn

FAn

CSAn

MUXCSACSA

C

C

C

CnnCnC

)3(log)(log

)(log

)(log

22

2

2

2

3

)1(3

)12/()2/(3)(

Binary Adder Design Spring 2003 29

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

FA

FAn

FAn

CSAn

MUXCSACSA

Cn

C

C

C

CnnCnC

57.1

)3(log)(log

)(log

)(log

22

2

2

2

3

)1(3

)12/()2/(3)(

Binary Adder Design Spring 2003 30

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

FA

FAn

FAn

CSAn

MUXCSACSA

Cn

C

C

C

CnnCnC

57.1

)3(log)(log

)(log

)(log

22

2

2

2

3

)1(3

)12/()2/(3)(

4398)32(1449)16(474)8(153)4(48)2(14)1(

CSA

CSA

CSA

CSA

CSA

CSA

CCCCCC

Binary Adder Design Spring 2003 31

Conditional Sum Adder

full adder implements adder for n=1: CSA(1) = FA !!!!

FA

FAn

FAn

CSAn

MUXCSACSA

Cn

C

C

C

CnnCnC

57.1

)3(log)(log

)(log

)(log

22

2

2

2

3

)1(3

)12/()2/(3)( n CSA RCA

1 14 142 48 284 153 568 474 11216 1449 22432 4398 448

Binary Adder Design Spring 2003 32

Carry Lookahead Adder

Main principle: combine carry computations of substrings

Carry into bit position i: c[i] is computed from bits: a[i-1:0],b[i-1:0], cin

• condition:

0

1

2]0:1[]0:1[

12]0:1[]0:1[

2]0:1[]0:1[][

in

ini

i

iin

c

c

if

if

ibia

ibia

cibiaic

Binary Adder Design Spring 2003 33

Carry Lookahead Adder

Main principle: combine carry computations of substrings

Carry into bit position i: c[i] is computed from bits: a[i-1:0],b[i-1:0], cin

• condition:

Definition propagate signals:

Definition generate signals:

1, 1]:[]:[1),( ijij ijbijabap

1, 10]:[]:[1),( ijij ijbijabag

10, 10]0:[]0:[1),,(),,( j

ininjinj cjbjacbagcbaG

0

1

2]0:1[]0:1[

12]0:1[]0:1[

2]0:1[]0:1[][

in

ini

i

iin

c

c

if

if

ibia

ibia

cibiaic

Binary Adder Design Spring 2003 34

Carry Lookahead Adder

Definition propagate signals:

Definition generate signals:

for i>0:

for i=0:

relation to carries:

Computation of the signals , :

for i>0:

for i=0: 2]0[]0[),,(

][][),(

][][),(

0,0

,

,

inin

ii

ii

cbacbag

ibiabag

ibiabap

),(, bap ii ),(, bag ii

1, 1]:[]:[1),( ijij ijbijabap

1, 10]:[]:[1),( ijij ijbijabag

10, 10]0:[]0:[1),,( j

ininj cjbjacbag

),,(),,(][ 10,1 iniini cbaGcbagic

Binary Adder Design Spring 2003 35

Carry Lookahead Adder

Combination of carry and propagate signals:

ijjkik ppp ,1,,

Binary Adder Design Spring 2003 36

)( ,1,1,,

,1,,

ijjkjkik

ijjkik

gpgg

ppp

Carry Lookahead Adder

Combination of carry and propagate signals:

Binary Adder Design Spring 2003 37

ijjkjk

ijjkjkik

ijjkik

gNANDpNANDg

gpgg

ppp

,1,1,

,1,1,,

,1,,

)(

Carry Lookahead Adder

Combination of carry and propagate signals:

Binary Adder Design Spring 2003 38

Carry Lookahead Adder

Combination of carry and propagate signals:

Given two such pairs of generate and propagate signals and

we define the operation :

ijjkjk

ijjkjkik

ijjkik

gNANDpNANDg

gpgg

ppp

,1,1,

,1,1,,

,1,,

)(

),( 1,1, jkjk pg ),( ,, ijij pg

ijjkijjkjk

ijijjkjkikik

ppgNANDpNANDg

pgpgpg

,1,,1,1,

,,1,1,,,

,

),(),(),(

Binary Adder Design Spring 2003 39

Carry Lookahead Adder

Carry computation based on computation of generate and propagate signals:

),(

),(),(),(),(

,,

,,1,11,1,,,,

jjjj

k

ij

iiiikkkkkkkkikik

pg

pgpgpgpg

Binary Adder Design Spring 2003 40

Carry Lookahead Adder

Carry computation based on computation of generate and propagate signals:

),(

),(),(),(),(

,,

,,1,11,1,,,,

jjjj

k

ij

iiiikkkkkkkkikik

pg

pgpgpgpg

),(

),(),(),(

),(),(

,,0

0,00,01,11,1,,

0,0,0,

jjjj

k

j

kkkkkkkk

kkkk

pg

pgpgpg

pgpG

Binary Adder Design Spring 2003 41

Carry Lookahead Adder

incnbnans ]0:1[]0:1[]0:[

Binary Adder Design Spring 2003 42

Carry Lookahead Adder

injj

in

cjbjnbjajna

cnbnans

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

Binary Adder Design Spring 2003 43

Carry Lookahead Adder

inj

injj

in

cjbjajnbjna

cjbjnbjajna

cnbnans

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

Binary Adder Design Spring 2003 44

Carry Lookahead Adder

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jin

jin

jjin

Binary Adder Design Spring 2003 45

Carry Lookahead Adder

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

1

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jj

jin

jin

jjin

Binary Adder Design Spring 2003 46

Carry Lookahead Adder

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

,,1

1

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 47

Carry Lookahead Adder

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

,1

,1

,,1

1

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 48

Carry Lookahead Adder

])0:1[],[(22]1:1[]1:1[

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

,1

,

,1

,1

,,1

1

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjj

jjj

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 49

Carry Lookahead Adder

]0:1[2][22]1:1[]1:1[

])0:1[],[(22]1:1[]1:1[

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

,1

,

,1

,

,1

,1

,,1

1

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjjj

jjj

jjj

jjj

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 50

Carry Lookahead Adder

]0:1[222]1:1[]1:1[

]0:1[2][22]1:1[]1:1[

])0:1[],[(22]1:1[]1:1[

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

1,0,1

,

,1

,

,1

,

,1

,1

,,1

1

jsGpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jj

jjj

jjj

jjjj

jjj

jjj

jjj

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 51

Carry Lookahead Adder

]0:1[22]1:1[]1:1[

]0:1[222]1:1[]1:1[

]0:1[2][22]1:1[]1:1[

])0:1[],[(22]1:1[]1:1[

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

1,0,1

,

1,0,1

,

,1

,

,1

,

,1

,1

,,1

1

jsGpgjnbjna

jsGpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjjj

jjj

jj

jjj

jjj

jjjj

jjj

jjj

jjj

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 52

Carry Lookahead Adder

]0:1[22]1:1[]1:1[

]0:1[22]1:1[]1:1[

]0:1[222]1:1[]1:1[

]0:1[2][22]1:1[]1:1[

])0:1[],[(22]1:1[]1:1[

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

1,0,1

,0

1,0,1

,

1,0,1

,

,1

,

,1

,

,1

,1

,,1

1

jsGpGjnbjna

jsGpgjnbjna

jsGpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjjj

jj

jjjj

jjj

jj

jjj

jjj

jjjj

jjj

jjj

jjj

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

Binary Adder Design Spring 2003 53

Carry Lookahead Adder

]0:1[22]1:1[]1:1[

]0:1[22]1:1[]1:1[

]0:1[222]1:1[]1:1[

]0:1[2][22]1:1[]1:1[

])0:1[],[(22]1:1[]1:1[

])0:1[],[(222]1:1[]1:1[

])0:1[],[(2),(2]1:1[]1:1[

])0:1[],[(2])[][(2]1:1[]1:1[

])0:1[],[(2]:1[]:1[

]0:1[]0:1[2]:1[]:1[

]0:1[2]:1[]0:1[2]:1[

]0:1[]0:1[]0:[

1,0,1

,0

1,0,1

,

1,0,1

,

,1

,

,1

,

,1

,1

,,1

1

jsGpGjnbjna

jsGpgjnbjna

jsGpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcpgjnbjna

jsjcjbjajnbjna

jsjcjnbjna

cjbjajnbjna

cjbjnbjajna

cnbnans

jjjj

jj

jjjj

jjj

jj

jjj

jjj

jjjj

jjj

jjj

jjj

jjj

jjj

j

jjjjj

j

jj

jin

jin

jjin

1,0,][ jjj Gpjs

Binary Adder Design Spring 2003 54

Carry Lookahead Adder

• Structure

• Implementation using Parallel Prefix Computation

Binary Adder Design Spring 2003 55

Parallel Prefix Computation

For associative operation o, we define

Parallel Prefix Operation:

n-bit INPUT:

n-bit OUTPUT:

Compute the operation o on all prefixes of X[n:1]

11 XXXY iii

]1:[nX

]1:[nY

Binary Adder Design Spring 2003 56

Carry Lookahead Adder

Parallel Prefix Computation:

n=1: n=2^k:

1212212

21212

21212211

122

''''

'

XXXXX

YXY

YXXXXXXXY

XXX

iii

iii

iiiiii

iii

11 XY

Binary Adder Design Spring 2003 57

Carry Lookahead Adder

Parallel Prefix Computation:

0)1()1()2/()(

PP

PPPPC

CnnCnC

Binary Adder Design Spring 2003 58

Carry Lookahead Adder

Parallel Prefix Computation:

0)1(2)2/()(

0)1()1()2/()(

PP

PPPP

PP

PPPP

DDnDnD

CCnnCnC

Binary Adder Design Spring 2003 59

Carry Lookahead Adder

Parallel Prefix Computation:

)(log2)(0)1(

2)2/()(0)1(

)1()2/()(

2 nDnDD

DnDnDC

CnnCnC

PP

PP

PPPP

PP

PPPP

Binary Adder Design Spring 2003 60

Carry Lookahead Adder

Parallel Prefix Computation:

)(log2)(0)1(

2)2/()(0)1(

)1()2/()(

2 nDnDD

DnDnDC

CnnCnC

PP

PP

PPPP

PP

PPPP

n cost delay

1 0 02 7 4(2)4 28 8(4)8 77 12(8)16 182 16(12)32 399 20(16)

Binary Adder Design Spring 2003 61

Carry Lookahead Adder

ORANDPPCLA CCnCnnCnC )1(2)()(

Binary Adder Design Spring 2003 62

Carry Lookahead Adder

ORANDPPCLA

ORANDPPCLADDDnDnD

CCnCnnCnC

2)()(

)1(2)()(

Binary Adder Design Spring 2003 63

Carry Lookahead Adder

26)32(2)()(

)1(2)()(

CLA

ORANDPPCLA

ORANDPPCLA

DDDDnDnD

CCnCnnCnC

Binary Adder Design Spring 2003 64

Carry Lookahead Adder

• cost:n CSA RCA CLA

1 14 14 142 48 28 314 153 56 728 474 112 16116 1449 224 34632 4398 448 723

Binary Adder Design Spring 2003 65

Carry Lookahead Adder

• delay:n CSA RCA CLA

1 4 4 6(4)2 6 8 10(6)4 8 16 14(10)8 10 32 18(14)16 12 64 22(18)32 14 128 26(22)

Binary Adder Design Spring 2003 66

Carry Lookahead Adder

• Example for n=8 – design

– computation of 183+43

Binary Adder Design Spring 2003 67

Carry Lookahead Adder

Binary Adder Design Spring 2003 68

Carry Lookahead Adder

Binary Adder Design Spring 2003 69

Carry Lookahead Adder

Binary Adder Design Spring 2003 70

Carry Lookahead Adder

Binary Adder Design Spring 2003 71

Carry Lookahead Adder

Binary Adder Design Spring 2003 72

Carry Lookahead Adder

Binary Adder Design Spring 2003 73

Carry Lookahead Adder

Binary Adder Design Spring 2003 74

Carry Lookahead Adder

Binary Adder Design Spring 2003 75

Carry Lookahead Adder

Binary Adder Design Spring 2003 76

Carry Lookahead Adder

Binary Adder Design Spring 2003 77

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

]]0:1[[)1(]0:1[[]]0:1[[ nbnans op

Binary Adder Design Spring 2003 78

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[]]0:1[[)1(]0:1[[]]0:1[[

opifnbna

opifnbnanbnans op

Binary Adder Design Spring 2003 79

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

00]0]0:1[[]0:1[[

11]1]0:1[[]0:1[[

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[]]0:1[[)1(]0:1[[]]0:1[[

opifnbna

opifnbna

opifnbna

opifnbnanbnans op

Binary Adder Design Spring 2003 80

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[

00]0]0:1[[]0:1[[

11]1]0:1[[]0:1[[

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[]]0:1[[)1(]0:1[[]]0:1[[

opifopopnbna

opifopopnbna

opifnbna

opifnbna

opifnbna

opifnbnanbnans op

Binary Adder Design Spring 2003 81

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

opopnbnaopifopopnbna

opifopopnbna

opifnbna

opifnbna

opifnbna

opifnbnanbnans op

]]0:1[[]0:1[[0]]0:1[[]0:1[[

1]]0:1[[]0:1[[

00]0]0:1[[]0:1[[

11]1]0:1[[]0:1[[

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[]]0:1[[)1(]0:1[[]]0:1[[

Binary Adder Design Spring 2003 82

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

• assumption: add/sub result is representable with n bits

opopnbnaopifopopnbna

opifopopnbna

opifnbna

opifnbna

opifnbna

opifnbnanbnans op

]]0:1[[]0:1[[0]]0:1[[]0:1[[

1]]0:1[[]0:1[[

00]0]0:1[[]0:1[[

11]1]0:1[[]0:1[[

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[]]0:1[[)1(]0:1[[]]0:1[[

Binary Adder Design Spring 2003 83

Addition/Substraction

• Addition and Subtration for n-bit two’s complement inputs– bit op signals the case of subtraction (op=1):

• assumption: add/sub result is representable with n bits

• Detection of the case that the result can not be represented with n bits(overflow)

opopnbnaopifopopnbna

opifopopnbna

opifnbna

opifnbna

opifnbna

opifnbnanbnans op

]]0:1[[]0:1[[0]]0:1[[]0:1[[

1]]0:1[[]0:1[[

00]0]0:1[[]0:1[[

11]1]0:1[[]0:1[[

0]]0:1[[]0:1[[

1]]0:1[[]0:1[[]]0:1[[)1(]0:1[[]]0:1[[

Binary Adder Design Spring 2003 84

Overflow

• Overflow: result too large for finite computer word– e.g., adding two n-bit numbers does not yield an n-bit number

0111+ 0001 note that overflow term is somewhat

misleading, 1000 it does not mean a carry “overflowed”

• Detecting Overflow– No overflow when adding a positive and a negative number– No overflow when signs are the same for subtraction– Overflow occurs when the value affects the sign:

• overflow when adding two positives yields a negative • or, adding two negatives gives a positive• or, subtract a negative from a positive and get a negative• or, subtract a positive from a negative and get a positive

– Consider the operations A + B, and A – B• Can overflow occur if B is 0 ?• Can overflow occur if A is 0 ?

Binary Adder Design Spring 2003 85

Effects of Overflow

• An exception (interrupt) occurs– Control jumps to predefined address for exception

– Interrupted address is saved for possible resumption

• Details based on software system / language– example: flight control vs. homework assignment

• correct sign has to be computed even for overflows– branches should also work correctly after overflows

– neg signal:

0]]0:1[[)1(]]0:1[[ nbnaneg sub

Binary Adder Design Spring 2003 86

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[ nT

Binary Adder Design Spring 2003 87

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

innnn

in cnbnabacba ]0:2[]0:2[)(2][][ 111

nT

Binary Adder Design Spring 2003 88

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

])0:2[],1[()(2

]0:2[]0:2[)(2][][

111

111

nsncba

cnbnabacba

nnn

innnn

in

nT

Binary Adder Design Spring 2003 89

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

]0:2[])1[2]1[(2

])0:2[],1[()(2

]0:2[]0:2[)(2][][

111

111

111

nsncncba

nsncba

cnbnabacba

nnn

nnn

innnn

in

nT

Binary Adder Design Spring 2003 90

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

]0:2[])1[2])1[],[((2

]0:2[])1[2]1[(2

])0:2[],1[()(2

]0:2[]0:2[)(2][][

111

111

111

1

nsncnsnc

nsncncba

nsncba

cnbnabacba

nnn

nnn

ninnn

nin

nT

Binary Adder Design Spring 2003 91

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

]]0:1[[])1[][(2

]0:2[])1[2])1[],[((2

]0:2[])1[2]1[(2

])0:2[],1[()(2

]0:2[]0:2[)(2][][

111

111

111

1

nsncnc

nsncnsnc

nsncncba

nsncba

cnbnabacba

n

nnn

nnn

ninnn

nin

nT

Binary Adder Design Spring 2003 92

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

]]0:1[[])1[][(2

]0:2[])1[2])1[],[((2

]0:2[])1[2]1[(2

])0:2[],1[()(2

]0:2[]0:2[)(2][][

111

111

111

1

nsncnc

nsncnsnc

nsncncba

nsncba

cnbnabacba

n

nnn

nnn

ninnn

nin

]1[][]]0:1[[])1[][(2 ncncTnsncnc nn

nT

Binary Adder Design Spring 2003 93

Overflow & Sign

• Overflow detection:

incnbnaovf ]]0:1[[]]0:1[[

]]0:1[[])1[][(2

]0:2[])1[2])1[],[((2

]0:2[])1[2]1[(2

])0:2[],1[()(2

]0:2[]0:2[)(2][][

111

111

111

1

nsncnc

nsncnsnc

nsncncba

nsncba

cnbnabacba

n

nnn

nnn

ninnn

nin

]1[][]]0:1[[])1[][(2 ncncTnsncnc nn

]1[][ ncncovf

nT

Binary Adder Design Spring 2003 94

Overflow & Sign

• Sign condition:

0]]0:1['[]]0:1[[ incnbnaneg

Binary Adder Design Spring 2003 95

Overflow & Sign

• Sign condition:

consider sign extended sum:

0]]0:1['[]]0:1[[ incnbnaneg

]0:1[])0:1[],1[(])0:1[],1[( nscnbnbnana in

Binary Adder Design Spring 2003 96

Overflow & Sign

• Sign condition:

consider sign extended sum:

sign computation:

0]]0:1['[]]0:1[[ incnbnaneg

]0:1[])0:1[],1[(])0:1[],1[( nscnbnbnana in

][nsneg

Binary Adder Design Spring 2003 97

Overflow & Sign

• Sign condition:

consider sign extended sum:

sign computation:

0]]0:1['[]]0:1[[ incnbnaneg

]0:1[])0:1[],1[(])0:1[],1[( nscnbnbnana in

][]1[]1[][

ncnbnansneg

Binary Adder Design Spring 2003 98

Overflow & Sign

• Sign condition:

consider sign extended sum:

sign computation:

0]]0:1['[]]0:1[[ incnbnaneg

]0:1[])0:1[],1[(])0:1[],1[( nscnbnbnana in

][),(][]1[]1[

][

1,1 ncbapncnbna

nsneg

nn

Binary Adder Design Spring 2003 99

Overflow & Sign

• Sign condition:

consider sign extended sum:

sign computation:

0]]0:1['[]]0:1[[ incnbnaneg

]0:1[])0:1[],1[(])0:1[],1[( nscnbnbnana in

),,(),(

][),(][]1[]1[

][

1,01,1

1,1

innnn

nn

cbaGbap

ncbapncnbna

nsneg

Binary Adder Design Spring 2003 100

Design of an Add/Subtract Unit

Binary Adder Design Spring 2003 101

Design of an Add/Subtract Unit

])1[][( ncncovf

Binary Adder Design Spring 2003 102

Design of an Add/Subtract Unit

])1[]1[]1[][(])1[][(

npncnpncncncovf

Binary Adder Design Spring 2003 103

Design of an Add/Subtract Unit

])1[]1[][(])1[]1[]1[][(

])1[][(

nsnpncnpncnpnc

ncncovf

Binary Adder Design Spring 2003 104

Design of an Add/Subtract Unit

])1[]1[][(])1[]1[][(

])1[]1[]1[][(])1[][(

nsnpncnsnpnc

npncnpncncncovf

Binary Adder Design Spring 2003 105

Design of an Add/Subtract Unit

])1[(])1[]1[][(])1[]1[][(

])1[]1[]1[][(])1[][(

nsnegnsnpncnsnpnc

npncnpncncncovf