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A Pipelined Datapath. Resisters are used to save data between stages. 1/14. Corrected Datapath. The Write Register in the IF/ID register is from the wrong instruction. The Write Register is passed through the pipeline and forwarded to the Register File (RF) from the MEM/WB register. 2/14. - PowerPoint PPT Presentation
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Computer Architecture - A Pipelined Datapath
A Pipelined DatapathResisters are used to save data between stages.
Instructionmemory
Address
4
32
0
Add Addresult
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Writeregister
Writedata
Readdata
1
ALUresult
Mux
ALUZero
ID/EX
Datamemory
Address
1/14
Computer Architecture - A Pipelined Datapath
Corrected DatapathThe Write Register in the IF/ID register is from the
wrong instruction.The Write Register is passed through the pipeline
and forwarded to the Register File (RF) from the MEM/WB register.
Instructionmemory
Address
4
32
0
Add Addresult
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0
Address
Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Writeregister
Writedata
Readdata
Datamemory
1
ALUresult
Mux
ALUZero
ID/EX
2/14
Computer Architecture - A Pipelined Datapath
Instructions in the Pipeline (Clock 2)
Instructionmemory
Address
4
32
0
Add Addresult
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Writeregister
Writedata
Readdata
1
ALUresult
Mux
ALUZero
ID/EX
Instruction decode
lw $10, 20($1)
Instruction fetch
sub $11, $2, $3
Instructionmemory
Address
4
32
0
Add Addresult
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Writeregister
Writedata
Readdata
1
ALUresult
Mux
ALUZero
ID/EX
Instruction fetch
lw $10, 20($1)
Address
Datamemory
Address
Datamemory
Clock 1
Clock 2
sub $11,$2,$3 lw $10,20($1)
3/14
Computer Architecture - A Pipelined Datapath
Instructions in the Pipeline (Clock 4)sub $11,$2,$3 lw $10,20($1)
Instructionmemory
Address
4
0
Add Addresult
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
3216Sign
extend
Writeregister
Writedata
Memory
lw $10, 20($1)
Readdata
1
ALUresult
Mux
ALUZero
ID/EX
Execution
sub $11, $2, $3
Instructionmemory
Address
4
0
Add Addresult
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
Mux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Writeregister
Writedata
Readdata
1
ALUresult
Mux
ALUZero
ID/EX
Execution
lw $10, 20($1)
Instruction decode
sub $11, $2, $3
3216Sign
extend
Address
Datamemory
Datamemory
Address
Clock 3
Clock 4
4/14
Computer Architecture - A Pipelined Datapath
Instructions in the Pipeline (Clock 5) sub $11,$2,$3 lw $10,20($1)
Instructionmemory
Address
4
32
0
Add Addresult
1
ALUresult
Zero
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEMID/EX MEM/WB
Write backMux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Mux
ALUReaddata
Writeregister
Writedata
lw $10, 20($1)
Instructionmemory
Address
4
32
0
Add Addresult
1
ALUresult
Zero
Shiftleft 2
Inst
ruct
ion
IF/ID EX/MEMID/EX MEM/WB
Write backMux
0
1
Add
PC
0Writedata
Mux
1Registers
Readdata 1
Readdata 2
Readregister 1
Readregister 2
16Sign
extend
Mux
ALUReaddata
Writeregister
Writedata
sub $11, $2, $3
Memory
sub $11, $2, $3
Address
Datamemory
Address
Datamemory
Clock 6
Clock 5
5/14
Computer Architecture - A Pipelined Datapath
Pipelined ControlProblem: Control lines are defined in the IF stage.Example: In the WB stage MemtoReg and
RegWrite are opcode dependent.Solution: Pass the control lines through the
pipeline.
Control
EX
M
WB
M
WB
WB
IF/ID ID/EX EX/MEM MEM/WB
Instruction
6/14
Computer Architecture - A Pipelined Datapath
Pipeline Datapath with Control
PC
Instructionmemory
Inst
ruct
ion
Add
Instruction[20– 16]
Mem
toR
eg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction[15– 0]
0
0
Mux
0
1
Add Addresult
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Mux
1
ALUresult
Zero
Writedata
Readdata
Mux
1
ALUcontrol
Shiftleft 2
Reg
Writ
e
MemRead
Control
ALU
Instruction[15– 11]
6
EX
M
WB
M
WB
WBIF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
Mux
0
1
Me
mW
rite
AddressData
memory
Address
Computer Architecture - A Pipelined Datapath
Data DependenciesBackward lines cause data hazards:
IM Reg
IM Reg
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6
Time (in clock cycles)
sub $2, $1, $3
Programexecutionorder(in instructions)
and $12, $2, $5
IM Reg DM Reg
IM DM Reg
IM DM Reg
CC 7 CC 8 CC 9
10 10 10 10 10/– 20 – 20 – 20 – 20 – 20
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
Value of register $2:
DM Reg
Reg
Reg
Reg
DM
sub $2,$1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2
sw $15,100($2)
8/14
Computer Architecture - A Pipelined Datapath
2 Easy SolutionsThe RF is written into in the 1st half of the cycle and
read from in the 2nd half of the cycle.Thus the data written is the data read. The add
instruction isn’t a hazard.Disallow data hazards by
adding aninstruction called nop (no operation).
Now there aren’t anydata hazards.
sub $2,$1,$3nopnopand $12,$2,$5or $13,$6,$2add $14,$2,$2sw $15,100($2)
9/14
Computer Architecture - A Pipelined Datapath
Detecting And ForwardingEasy. Each pipeline register contains the Rs, Rt,
and Rd of the current instruction.If one of the next equalities is true there is a hazard:
EX/MEM.Rd == ID/EX.RsEX/MEM.Rd == ID/EX.RtMEM/WB.Rd == ID/EX.RsMEM/WB.Rd == ID/EX.Rs
A unit called the Forwarding Unit decides if there is a hazard and solves it by using forwarding.
The values are directed from the EX/MEM and MEM/WB registers to the ALU.
10/14
Computer Architecture - A Pipelined Datapath
The Forwarding Unit
Registers
Mux M
ux
ALU
ID/EX MEM/WB
Datamemory
Mux
Forwardingunit
EX/MEM
b. With forwarding
ForwardB
RdEX/MEM.RegisterRd
MEM/WB.RegisterRd
RtRtRs
ForwardA
Mux
ALU
ID/EX MEM/WB
Datamemory
EX/MEM
a. No forwarding
Registers
Mux
11/14
Computer Architecture - A Pipelined Datapath
Data Hazards and StallsSometimes Forwarding doesn’t work (load-use data hazard):
Reg
IM
Reg
Reg
IM
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6
Time (in clock cycles)
lw $2, 20($1)
Programexecutionorder(in instructions)
and $4, $2, $5
IM Reg DM Reg
IM DM Reg
IM DM Reg
CC 7 CC 8 CC 9
or $8, $2, $6
add $9, $4, $2
slt $1, $6, $7
DM Reg
Reg
Reg
DM
lw $2,20($1)
and $4,$2,$5
or $8,$2,$6
add $9,$4,$2
slt $1,$6,$7
12/14
Computer Architecture - A Pipelined Datapath
Inserting a Bubble The EX,MEM, and WB control fields of the ID/EX
register are set to 0. The PC and IF/ID register aren’t updated. This causes the and & or instructions to repeat cycle 3 during cycle 4.
lw $2, 20($1)
Programexecutionorder(in instructions)
and $4, $2, $5
or $8, $2, $6
add $9, $4, $2
slt $1, $6, $7
Reg
IM
Reg
Reg
IM DM
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6Time (in clock cycles)
IM Reg DM RegIM
IM DM Reg
IM DM Reg
CC 7 CC 8 CC 9 CC 10
DM Reg
RegReg
Reg
bubble
13/14
Computer Architecture - A Pipelined Datapath
Hazard Detection Unit
PCInstruction
memory
Registers
Mux
Mux
Mux
Control
ALU
EX
M
WB
M
WB
WB
ID/EX
EX/MEM
MEM/WB
Datamemory
Mux
Hazarddetection
unit
Forwardingunit
0
Mux
IF/ID
Inst
ruct
ion
ID/EX.MemRead
IF/ID
Wri
te
PC
Wri
te
ID/EX.RegisterRt
IF/ID.RegisterRd
IF/ID.RegisterRt
IF/ID.RegisterRt
IF/ID.RegisterRs
RtRs
Rd
Rt EX/MEM.RegisterRd
MEM/WB.RegisterRd
The hardware doesn’t depend on the compiler to detect and eliminate data hazards. A smart compiler will help in order to achieve better performance.
14/14
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