A Three-Port Pipelined Register File Implemented Using s ...ecse.rpi.edu/frisc/theses/ErdoganThesis/A Three-Port Pipelined Register File... · A Three-Port Pipelined Register File

A Three-Port Pipelined Register File Implemented Using a SiGe HBT BiCMOS Technology

by

Okan Erdogan

A Thesis Document Submitted to the Graduate

Faculty of Rensselaer Polytechnic Institute

in Partial Fulfillment of the

Requirements for the degree of

DOCTOR OF PHILOSOPHY

Major Subject: Computer and Systems Engineering

Approved by the Examining Committee:

_________________________________________ John F. McDonald, Thesis Adviser

_________________________________________ Christopher D. Carothers, Member

_________________________________________ Michael J. Wozny, Member

_________________________________________ Tong Zhang, Member

Rensselaer Polytechnic Institute Troy, New York

December, 2006 (For Graduation December, 2006)

ii

© Copyright 2006

by

Okan Erdogan

All Rights Reserved

iii

CONTENTS

A Three-Port Pipelined Register File Implemented Using a SiGe HBT BiCMOS Technology ................................................................................................................... i

CONTENTS ..................................................................................................................... iii

LIST OF TABLES............................................................................................................ vi

LIST OF FIGURES ......................................................................................................... vii

ABSTRACT ..................................................................................................................... xi

1. Introduction.................................................................................................................. 1

1.1 Semiconductor History....................................................................................... 1

1.2 Silicon-Germanium History............................................................................... 1

1.3 SiGe HBT Process Overview............................................................................. 2

1.4 Performance Advantages ................................................................................... 2

1.5 Graded Base HBTs............................................................................................. 3

1.6 SiGe HBT device comparisons .......................................................................... 4

1.6.1 Si Bipolar Junction Transistor (BJT) ..................................................... 4

1.6.2 Gallium Arsenide (GaAs) HBTs............................................................ 6

1.6.3 Complementary Metal Oxide Semiconductor (CMOS)......................... 8

1.7 State of Art IBM SiGe BiCMOS ....................................................................... 9

2. Design Strategy.......................................................................................................... 12

2.1 CML Logic Gates............................................................................................. 12

3. Register File Design .................................................................................................. 22

3.1 Design in 5HP .................................................................................................. 22

3.1.1 Structure of the Pipelined Register File ............................................... 22

3.1.2 Address decoders ................................................................................. 23

3.1.3 Comparator........................................................................................... 24

3.1.4 Pipeline Register .................................................................................. 25

3.1.5 Memory cell ......................................................................................... 26

iv

3.1.6 Word drivers......................................................................................... 28

3.1.7 Sense amplifier..................................................................................... 30

3.1.8 Multiplexer........................................................................................... 32

3.2 Fabricated test chip in 5DM............................................................................. 35

3.3 Design in 7HP .................................................................................................. 36

3.4 Fabricated test chip in 7HP .............................................................................. 40

3.5 7HP test chip simulation .................................................................................. 44

4. Buffer and Simple Gate Driving Capabilities............................................................ 45

5. Test Chip Design ....................................................................................................... 61

5.1 5DM register file test chip overview................................................................ 61

5.2 Address counter design .................................................................................... 64

5.3 Linear Feedback Shift Register........................................................................ 67

5.4 Voltage controlled oscillator ............................................................................ 69

5.5 Viewing register file test chip signals .............................................................. 72

5.6 Pad receiver design .......................................................................................... 74

5.7 Pad driver design.............................................................................................. 76

5.8 7HP register file test chip overview................................................................. 78

5.9 7HP register file test result............................................................................... 81

5.10 7HP test chip modifications ............................................................................. 82

6. Future Work............................................................................................................... 83

6.1 8HP................................................................................................................... 83

6.2 Power Saving ................................................................................................... 85

6.3 3D integration................................................................................................... 87

6.4 BiCMOS register file ....................................................................................... 90

7. Conclusion ................................................................................................................. 95

8. Publications................................................................................................................ 96

9. References.................................................................................................................. 97

v

A. Probe Diagrams…………………………………………………………………99

B. 3D Maskset Design…………………………………………………………….100

B1. Pillar Type Via…………………………………………………………100

B2. Bridge Type Via……………………………………………………….100

B3. Chain Structure………………………………………………………...101

B4. Folding Wafers Together………………………………………………103

B5. Testing…………………………………………………………………104

C. Design Netlist………………………………………………………………….106

vi

LIST OF TABLES

Table 1 Si BJT vs. SiGe HBT (LN1 and LN2 are low noise devices). ............................. 5

Table 2 Typical GaAs/AlGaAs HBT figures..................................................................... 6

Table 3 SiGe vs. GaAs HBTs. ........................................................................................... 7

Table 4 CMOS vs. SiGe BiCMOS. ................................................................................... 9

Table 5 Representative Device Parameters for the 3 SiGe BiCMOS IBM Technologies.

................................................................................................................................. 11

Table 6 Flow of pipeline stages. ...................................................................................... 22

Table 7 7HP simulation results........................................................................................ 58

Table 8 5DM simulation results. ..................................................................................... 59

Table 9 8T/8HP simulation results. ................................................................................. 60

Table 10 List of 5DM register file test chip pads and their functions. ............................ 62

Table 11 List of shift register latches that can be XOR'ed to produce LFSR's of different

sizes.......................................................................................................................... 68

Table 12 Output pad signal as a function of Select A3 and Select A2............................ 73

Table 13 Output pad signal as a function of Select A2, Select A3, Select B2, Select B3.

................................................................................................................................. 73

Table 14 Column selection as a function of Select C2, Select C3, Select B2, Select B3.74

Table 15 List of 7HP register file test chip pads and their functions. ............................. 78

vii

LIST OF FIGURES

Figure 1 Energy band diagram for Si BJT and graded-base SiGe both biased in forward

active mode at low injection. ..................................................................................... 3

Figure 2 Ge content design trade-off. ................................................................................ 4

Figure 3 SiGe HBT and SiGe BJT fT and fmax vs. IC. ........................................................ 5

Figure 4 Low noise Ge profile........................................................................................... 6

Figure 5 GaAs and SiGe circuit yield vs. complexity. ...................................................... 7

Figure 6 CMOS vs. SiGe HBT power delay product. .......................................................8

Figure 7 IBM 5HP fT vs. Ic. ............................................................................................. 10

Figure 8 CML buffer schematics. .................................................................................... 12

Figure 9 Input output characteristics of CML buffer....................................................... 13

Figure 10 CML buffer with level 2 emitter followers. .................................................... 15

Figure 11 CML buffer with level 3 emitter followers. .................................................... 16

Figure 12 Buffered Widlar current source schematics. ................................................... 17

Figure 13 2 input AND function schematics. .................................................................. 18

Figure 14 2 input XOR function schematics. .................................................................. 19

Figure 15 D type latch schematic. ................................................................................... 20

Figure 16 Top level view of register file. ........................................................................ 23

Figure 17 Two-bit decoder layout. .................................................................................. 23

Figure 18 Three-bit decoder layout. ................................................................................ 24

Figure 19 Five-bit comparator schematic. ....................................................................... 24

Figure 20 Five-bit comparator layout. ............................................................................. 25

Figure 21 Pipeline register schematic.............................................................................. 25

Figure 22 Pipeline register layout.................................................................................... 26

Figure 23 Memory cell schematic. .................................................................................. 27

Figure 24 Memory cell layout. ........................................................................................ 28

Figure 25 Read address word driver schematics. ............................................................ 29

Figure 26 Write address word driver schematic. ............................................................. 30

Figure 27 Sense amplifier schematic. .............................................................................. 31

Figure 28 Layout of memory cells and sense amplifiers for one memory bank (8 words

by 32-bits). ............................................................................................................... 32

viii

Figure 29 Two-to-one multiplexer schematic.................................................................. 33

Figure 30 Two-to-one multiplexer layout........................................................................ 33

Figure 31 Four-to-one multiplexer schematic. ................................................................ 34

Figure 32 Four-to-one multiplexer layout. ...................................................................... 34

Figure 33 Layout of the test chip designed with 5DM technology. ................................ 35

Figure 34 Microphoto of the test chip designed in 5DM technology.............................. 36

Figure 35 Layout and schematics of the memory cell used in 7HP design..................... 38

Figure 36 Register file layout, depicting different submodules. ..................................... 39

Figure 37 Top-level schematics for the register file chip designed with the 7HP

technology................................................................................................................ 41

Figure 38 The layout of the test chip designed in 7HP.................................................... 42

Figure 39 The microphoto of the test chip designed in 7HP. .......................................... 43

Figure 40 Simulation results of the register file test chip................................................ 44

Figure 41 Bipolar buffer schematic in 7HP..................................................................... 47

Figure 42 Bipolar buffer layout in 7HP........................................................................... 48

Figure 43 Tapered CMOS inverter schematic in 7HP..................................................... 48

Figure 44 CMOS inverter layout in 7HP......................................................................... 49

Figure 45 Simulation result depicting the rise time of bipolar buffer and tapered CMOS

inverter driving 0.5 pF capacitive load. ................................................................... 50

Figure 46 Simulation result depicting the fall time of bipolar buffer and tapered CMOS

inverter driving 0.5 pF capacitive load. ................................................................... 50


inverter driving 1 pF capacitive load. ...................................................................... 51


inverter driving 1 pF capacitive load. ..................................................................... 51


inverter driving 10 pF capacitive load. .................................................................... 52


inverter driving 10 pF capacitive load. .................................................................... 52


inverter driving 100 pF capacitive load. .................................................................. 53

ix


inverter driving 100 pF capacitive load. .................................................................. 53


inverter driving 50 Ω terminated transmission line. ............................................... 54


inverter driving 50 Ω terminated transmission line. ................................................ 54

Figure 55 Bipolar AND schematic in 7HP. ..................................................................... 55

Figure 56 Bipolar AND layout in 7HP. ........................................................................... 55

Figure 57 CMOS NAND schematic in 7HP.................................................................... 56

Figure 58 CMOS NAND layout in 7HP.......................................................................... 56

Figure 59 Simulation result depicting the rise time of bipolar AND and tapered CMOS

NAND driving 1 pF capacitive load........................................................................ 57

Figure 60 Simulation result depicting the fall time of bipolar AND and tapered CMOS

NAND driving 1 pF capacitive load....................................................................... 57

Figure 61 5DM test chip block diagram. ......................................................................... 62

Figure 62 5DM test chip pad arrangement. ..................................................................... 64

Figure 63 Read address counter gate level schematics.................................................... 66

Figure 64 Write address counter gate level schematics................................................... 67

Figure 65 8-bit data rotator/6-bit LFSR gate level schematics........................................ 69

Figure 66 VCO schematics.............................................................................................. 70

Figure 67 FFI stage schematics. ...................................................................................... 71

Figure 68 Pad receiver schematics. ................................................................................. 74

Figure 69 High frequency pad receiver schematics......................................................... 76

Figure 70 Pad driver schematics...................................................................................... 77

Figure 71 7HP test chip block diagram. .......................................................................... 78

Figure 72 7HP test chip pad arrangements. ..................................................................... 80

Figure 73 Revised 7HP test chip pad arrangement.......................................................... 80

Figure 74 7HP test chip result. ........................................................................................ 81

Figure 75 Resubmited 7HP register file test chip. ........................................................... 82

Figure 76 Layout size comparison of memory cell in 7HP (left) and 8HP (right). ......... 83

Figure 77 Layout of 8 words of 16 bits array of memory cells in 7HP........................... 84

x

Figure 78 Layout of 8 words of 16 bits array of memory cells in 8HP........................... 85

Figure 79 CML buffer with power saving features. ........................................................ 86

Figure 80 Register partitioned 3D register file.20 ............................................................ 89

Figure 81 Bit partitioned 3D register file.20..................................................................... 89

Figure 82 CMOS 3-port memory cell.............................................................................. 92

Figure A1 16 pin high frequency probe pad diagram. ………………………………….99

Figure A2 10 pin high frequency probe pad diagram. ………………………………….99

Figure A3 10 pin power probe pad diagram. …………………………………………...99

Figure B1 Three dimensional view of pillar type vias. ......…………………………...100

Figure B2 Three dimensional view of bridge type vias. …..………………………….101

Figure B3 Structure of pillar type vias. ……………………………………………….102

Figure B4 Structure of bridge type vias. ………………………………………………102

Figure B5 Test structure of pillar type vias. …………………………………………..103

Figure B6 Pillar type via dimensions. …………………………………………………104

Figure B7 Bridge type via dimensions. ……………………………………………….105

xi

ACKNOWLEDGEMENT

I would like to thank my fellow research group members for their help and support. I

would also like to thank my thesis advisor Professor John F. McDonald for giving me

the opportunity to participate in the project, also for his guidance and assistance

throughout the project. I would like to thank my doctoral committee members Professors

Michael Wozny, Christopher Carothers, Tong Zhang, and faculty and staff of Electrical,

Computer, and Systems Engineering Department, and Professors Ronald Gutmann and

James Lu for their support, assistance and advices.

I would also like to thank my mother, Fadime Erdoğan, my father Ahmet Erdoğan and

my sister Ayben Erdoğan for their belief and support.

xii

ABSTRACT

The goal of this work is to research, design, test and evaluate a pipelined register file

(PRF). A modified version of this register file is also integrated in a test engine with an

adder and finite state machine to demonstrate 3D wafer scale integration.

The PRF was implemented using Current Mode Logic (CML) with SiGe

heterojunction bipolar transistors (HBT) in two different generations of the BiCMOS

technology. The first process features 0.5 µm minimum emitter size HBTs with a cut-off

frequency (fT) of 48 GHz and maximum oscillation frequency (fmax) of 69 GHz and the

second process features 0.2 µm minimum emitter size HBTs with an fT of 120 GHz and

fmax of 100 GHz.

The PRF is composed of three pipeline stages and has one write and two read ports.

The PRF includes four 8 word by 32 bit memory banks for the 5DM design and an 8

word by 32 bit memory bank for 7HP design. The register file is designed to operate

with an 8 GHz clock for the 5DM design and 16 GHz 7HP design. The estimated power

dissipation of PRF is 7W using a 3.4 V voltage supply for the 7HP design.

1

1. Introduction

1.1 Semiconductor History

In early 1948, William Shockley conceived of a transistor to improve upon Bell Labs’

previous point contact transistor efforts by sandwiching a piece of p-type semiconductor

between to pieces of n-type semiconductor. Contrary to belief held at that time inside

Bell Labs that electrons moved only along the surface of a semiconductor, Shockley

asserted that his junction transistor would work with electrons moving through the body

of the semiconductor. This assertion was proven in February of 1948, when a physicist

named Richard Haynes attached probes to either side of a paper-thin slice of pure

germanium crystal and observed that a current could be induced through it.

In 1950, chemists at Bell Labs discovered how to grow crystals with the sandwich

structure impurities that Shockley had envisioned by doping melted germanium as they

moved a seed piece of germanium in and out of the molten material. Adding Antimony

made the material n-type, and adding gallium created a hole-rich p-type material. On

April 12, 1950, the group tested the device, and found that it amplified currents that were

applied to the middle, p-type germanium for low frequency signals.

Shockley hypothesized that in order to increase the device’s frequency handling

capabilities, the base needed to be thinner to decrease electron transit time. In January of

1951, Morgan Sparks, a chemist at Bell Labs successfully created a bipolar junction

transistor with a base thinner than before, which significantly improved the switching

frequency of the device. Bell Labs announced the invention of the bipolar junction

transistor.1

1.2 Silicon-Germanium History

IBM began investigating epitaxial growth using chemical vapor deposition to

manufacture bipolar devices in 1982 when scaling limitations of ion implantation

became evident, and device frequencies were projected to peak at 25 to 30 GHz. In

1994, IBM demonstrated successful production of Radio Frequency Integrated Circuits

(RFIC) in a Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT)

process, and in 1996, began the groundbreaking SiGe Bipolar-Complementary Metal

2

Oxide Semiconductor (BiCMOS) process. This process currently yields devices with

feature sizes of 0.18 µm (7HP) and 0.13 µm (8HP) and is slated for an upgrade in the

near future.

1.3 SiGe HBT Process Overview

A heterostructure device uses materials of different bandgaps at the p-n junction, which

creates a lowered barrier to hole or electron transport across the barrier, depending on

whether the p- or n-type material has the larger bandgap.

Silicon crystal has a lattice constant of 5.43, and germanium crystal has a lattice

constant of 5.6. The difference in the lattice constants introduces complications when

growing silicon germanium on silicon because there is a strain on the SiGe lattice

structure as it stretches to conform to the lattice constant of Si crystal. However, stable

SiGe crystal can be grown if the layer is thin enough. As the layer thickens, the strain

becomes greater and it is less likely that the crystal structure will hold.

As mentioned above, SiGe HBTs are formed by growing first a layer of SiGe on Si

substrate, while continuously grading the Ge concentration, and then growing another

layer of Si on top of the SiGe base. These layers are grown using molecular beam

epitaxy (MBE) and chemical vapor deposition (CVD), and more recently, ion

implantation has been used to implant Ge content into the base before growing the last

layer of Si. Implantation results have been less favorable than the previous two

methods, yielding devices more prone to collector-emitter leakage.2

1.4 Performance Advantages

Germanium has a bandgap of 0.661 eV, which is significantly smaller than that of

silicon (1.12 eV). In the silicon germanium heterojunction bipolar transistor, germanium

is added to the base to narrow its bandgap. In the case of an NPN HBT shown in Figure

13 the bandgap difference allows electrons to more easily overcome the emitter-base

junction. The bandgap difference also restricts hole injection across the base-emitter

junction.4

3

Using a narrow bandgap material in the base increases the common emitter current

gain β, allowing a higher doping level in the base, which in turn lowers base-spreading

resistance, an important limiting factor in device frequency determination.

Figure 1 Energy band diagram for Si BJT and graded-base SiGe both biased in forward active

mode at low injection.

1.5 Graded Base HBTs

In today’s SiGe HBT processes, the Ge content in the base is graded linearly to

introduce a built in drift field in the base. This drift field accelerates electrons through

the base of the device, reducing the base transit time, τb. As is evident in the band

diagram shown in Figure 1, the graded Ge content is not a necessary precondition for a

speed improvement over BJT, but it helps increase the speed of the device even more.5

However, it is also possible for the positive effects to be negated when the emitter is

more weakly doped by an increased minority charge distribution in the emitter caused by

a lowered Ge content at the base-emitter junction.6

4

Figure 2 Ge content design trade-off.

As shown in Figure 27, the Ge content can be altered in order to achieve different device

characteristics. The dashed Ge profile device exhibits higher fT and β, and lower noise.

However, the solid profile, though lower in fT, demonstrates a lower fT roll-off at high

injection.7

1.6 SiGe HBT device comparisons

1.6.1 Si Bipolar Junction Transistor (BJT)

SiGe HBTs offer significant performance advantages over Si BJTs, as shown in Figure

38. SiGe HBTs have demonstrated 1.2 to 1.6 times fT/fmax improvements over Si BJTs,

which were identically fabricated. Current production SiGe HBT technologies can

operate at frequencies upwards of 75 to 100 GHz, as will be explained in section 4.

SiGe HBTs can be implemented to realize power savings over BJTs by trading

bandwidth for power that is, operating at a much lower current while maintaining high

frequency operation. 9

5

Figure 3 SiGe HBT and SiGe BJT fT and fmax vs. IC.

In BJT current technologies, base profile control is a significant obstacle to high

yield in these processes. In contrast, SiGe HBT production processes yield exemplary

base profile control, resulting in devices that perform to tight tolerances in ac and dc

parameters. Higher current gain is also attainable in SiGe HBTs. This higher current gain

combined with the higher Early voltages, which give SiGe HBTs higher output

resistance, allows designers more freedom in power dissipation and improves amplifier

design in RF applications.10

Performance Si BJT SiGe HBT SiGe LN1 SiGe LN2

β at VBE=0.7V 67 113 350 261

VA (V) 19 60 58 113

BVceo (V) 3.5 3.2 2.7 2.7

RB (KΩ/cm) 12.8 9.8 10.3 10.7

Peak fT (GHz) 38 52 52 57

Peak fmax (GHz) 52 64 62 67

Table 1 Si BJT vs. SiGe HBT (LN1 and LN2 are low noise devices).

Table 1 7 shows the results of shows a comparison of Si BJT against several types of

SiGe HBTs. The regular SiGe HBT was treated with Ge content as shown in Figure 2.

LN1 and LN2 devices employed a low-noise specific Ge content shown below in Figure

4. Base resistance of SiGe HBTs is notably lower than in Si BJTs no matter what doping

6

profile is used, leading to a large increase in speed of the device. It can be seen in Table

1 that these low noise optimized doping profiles yield better performing devices.

Figure 4 Low noise Ge profile.

1.6.2 Gallium Arsenide (GaAs) HBTs

GaAs HBT devices offer slightly higher performance numbers in fT, fmax, or βF. Data

from a TRW GaAs/AlGaAs HBT process currently in production shows significant

advantages over current SiGe processes.

fT 40 GHz

fmax 70 GHz

βF 400 @ 1mA

Table 2 Typical GaAs/AlGaAs HBT figures.

It is easy to see how power can be traded for bandwidth using GaAs technology. A

current gain so high can offer a designer flexibility in Low Noise Amplifier (LNA)

designs.

Though data in Table 3 is dated 1997, the general trend remains the same. The

general idea is that SiGe BiCMOS processes are typically 2 to 4 times more cost

effective than GaAs processes. Yield is a problem for GaAs, because of Ga rich deposits

occurring in wafers. SiGe processes rely on proven Si processing techniques and have

great yield. Also, feature sizes of SiGe devices continue to shrink and stay ahead of

GaAs.11

7

Item GaAs SiGe Units

FET HBT HBT BiCMOS

Feature Size 0.5 2 0.5 0.5 um

Starting Material 200 600 200 200 $

Mask Steps 12 14 28 32

Photo Cost 1200 1400 2800 3200 $

Raw Cost 1400 2000 3000 3400 $

Wafer Diameter 100 100 200 200 mm

Yield 80 70 95 95 %

Total Cost 0.22 0.36 0.1 0.11 $/sq. mm

Table 3 SiGe vs. GaAs HBTs.

Figure 5 is data taken from the GaAs/AlGaAs HBT process from TRW mentioned

above. Clearly, yield plummets as IC complexity increases. Contrasted with SiGe

processes, which are based on traditional Si production and achieve high yield (~90%)

even at high integration levels, GaAs is evidently less cost effective.

Figure 5 GaAs and SiGe circuit yield vs. complexity.

8

1.6.3 Complementary Metal Oxide Semiconductor (CMOS)

Though CMOS is not thought of as a competing technology to bipolar devices any more,

with recent SiGe HBT technologies, there are numerous advantages for bipolar over

CMOS in the digital domain. CMOS digital designs require switching current on and off

at high speeds in a circuit. With inductive lines in power rails and long runs of wire in

large chips, the L dI/dt switching noise present begins to create floating grounds and

power bounce in circuits. This problem only gets worse as circuit speeds increase. Using

current steering logic, constant current can be fixed in a circuit; thereby nearly

eliminating these voltage swings.

Figure 6 CMOS vs. SiGe HBT power delay product.

For a given technology, a figure of merit is the product of the power consumption

and propagation delay, a constant known at the Power Delay Product (PDP).12 The

propagation time and power consumption of a gate are related by the speed at which a

given amount of energy can be stored on the gate capacitors. The faster the energy

transfer (or more power), the faster the gate. The PDP, the energy consumed by the gate

per switching event is:

9

)(

*

MHzFreq

GateEquiv

VI

PDP

=

Figure 613 compares the PDP of IBM’s CMOS and SiGe processes. Based on the

table and figure, the 1998 CMOS and 1999 BiCMOS processes have the same PDP,

while the future processes in both technologies give a large advantage in PDP to the

BiCMOS process.

SiGe processes offer great flexibility due to their integration of CMOS and bipolar

devices on the same die. This is extremely beneficial in RF applications, where SiGe

HBT circuits are used for amplifier circuits and drivers, but memory and other digital

logic is better suited for CMOS devices. Such high level integration allows

manufacturers to cut down on package count in these portable devices. This will not only

allows the overall package to be smaller, but also makes for more efficient electronics

with shorter wires. Thus performance will be increased and power dissipation will be

reduced.

Table 4 summarizes the PDP values of key CMOS and BiCMOS processes.

Technology Size Effective Size Vth Vdd PDP (µW/gate/MHz)

High Low

CMOS 1998 0.5u 0.36u 0.77 3.3 0.36 0.2

2000 0.25u 0.18u 0.5 2.5 0.18 0.08

2000 0.22u 0.12u 0.4 1.8 0.1 0.05

BiCMOS 5HP SiGe HBT 0.5u 0.42u 0.5 0.36

7HP SiGe HBT 0.20u 0.18u N/A 0.01

Table 4 CMOS vs. SiGe BiCMOS.

1.7 State of Art IBM SiGe BiCMOS

The simulated results of IC vs. fT results for first generation (5HP) BiCMOS process

HBTs are shown in the Figure 7 14 below.

10

Figure 7 IBM 5HP fT vs. Ic.

Combining attractive RF performance with the low cost high integration levels, and

excellent control of silicon based processes; SiGe BiCMOS technologies are gaining

increasing popularity for use in a wide variety of both wired and wireless consumer

telecommunication applications. IBM 5HP BiCMOS process is built in a 0.5 µm

generation technology featuring a 47 GHz fT and 70 GHz fmax. It has been shipping in

volume for seven years now.15

11

SiGe BiCMOS Technology 5HP 6HP 7HP

SiGe HBT Parameter

Drawn Emitter Width (um) 0.50 0.32 0.20

Actual Emitter Width (um) 0.42 0.30 0.18

Peak β 113 88 543

VA (V) 60 61 68

Peak fT (GHz) 48 50 120

Peak fmax (GHz) 69 65 100

BVCEO (V) 3.3 3.4 1.85

SiGe CMOS Parameters

Drawn L (um) 0.65 0.24 0.18

Leff (um) 0.25 0.18 0.11

VDD (V) 3.3 2.5 1.8

Table 5 Representative Device Parameters for the 3 SiGe BiCMOS IBM Technologies.

Table 516 summarizes the key parameters of IBM’s three generations of SiGe HBT

BiCMOS processes.

SiGe 5HP is the baseline SiGe BiCMOS technology while SiGe 6HP includes

laterally scaled SiGe HBT and fully scaled CMOS. SiGe 7HP includes laterally and

vertically scaled SiGe HBT and fully scaled CMOS.

12

2. Design Strategy

2.1 CML Logic Gates

Different digital circuit families are available for use with bipolar devices. Some of the

well known families are Resistor Transistor Logic (TRL), Transistor Transistor Logic

(TTL), Integrated Injection Logic (IIL), Emitter Coupled Logic (ECL), and Current

Mode Logic (CML). The switching speed of the devices and the circuit driving

requirements affect the choice of the digital circuit family.

In a bipolar device the amount of charge and the speed of the displacement of this

charge in the base region determine the conduction of current from the collector to the

emitter. In order to saturate the device a large amount of charge needs to be accumulated

in the base of the device. To achieve higher switching speeds saturation of the device has

to be avoided. The ECL and CML families operate the devices in the forward active and

cut-off regions so that the amount of charge required is significantly less than the other

circuit families, therefore these families provide higher switching speeds.

ECL and CML circuits are based on the following basic differential circuit known

as the CML buffer, shown in Figure 8.

Figure 8 CML buffer schematics.

If both devices Q1 and Q0 have the same base-emitter voltage (VBE) the current ratio

can be written as:

13

kT

qVV ii

eI

I )(

0

11110−

=

From the equation it can be seen that when Vi10 is much greater than the Vi11, the

current I1 will be much greater than the I0. If the Vi11 is much greater than the Vi10, then

I0 will be the larger current. In steady state the majority of the current from the current

source flows through only one of the two devices, while the other essentially cut-off.

Thus current is steered through the different paths of the circuit indicated by the input

signals and the current flow through the circuit remains constant.

Figure 9 Input output characteristics of CML buffer .

The simulated results shown in Figure 9 that at about 200 mV, at least 99% of the

current is flowing from one device in the CML buffer. This can be specified as the

minimum operating voltage swing. Throughout the design a 250 mV or larger voltage

swing is used.14

ECL and CML families have lower output voltage swing than the other families,

thus the amount of charge to be transported to the loading circuit will be smaller than the

other circuit families. This will result in higher switching speeds of the circuit to when

driving its loads.

ECL and CML circuits can be driven with either differential or single ended signals.

In single ended signals one of the inputs to the circuits is tied to a reference voltage

while the other input to the circuits is one of the outputs of a preceding ECL or CML

14

circuit. The output of the circuit is generally set be a logical high when the input to the

circuit is significantly greater than the reference voltage, and logical low when the input

is significantly smaller than the reference voltage. This means that due to the fact that

only one of the collector resistors will significantly conduct current, when the collector

resistors are correctly sized there will be a significant voltage difference between the

complementary output nodes. On differential input signals, the reference voltage is

eliminated. The outputs of the preceding circuit are both fed to the ECL or CML circuit.

Given the differential voltage on the outputs of the preceding circuit, most of the current

will flow through only one of the branches. Thus a differential output voltage is

generated.

Using differential input has some inherent advantages. First the complements of the

signals are already available, so the need for inverters in designs is eliminated. Second,

the immunity to common noises is increased, since the noise will be affecting both

inputs but the difference of the signals stay unaffected. Third, by designing correct

biasing currents, input levels, and resistor values the bipolar devices in the circuit will

never operate in the saturation region. With the help of the small voltage swing, avoiding

saturation will allow the circuit to switch faster by charging and discharging faster.

On the other hand using differential ECL or CML has certain disadvantages. First,

the complementary signal pair has to be skew-free. With the skew in the signal pair, flow

of current in the circuit can be interrupted. This problem can be prevented with adjacent

routing of each signal pair. Second the need of two wires per logical signal doubles the

number of wires in the design. There exists a trade-off between the increased noise

immunity and the switching speed and the number of wires. Third the constant current

flow in the circuit increases the static power, while there is a very small amount of

dynamic power consumed in the circuitry.

Logical computations can be performed using ECL and CML circuits by forming

current trees. An ECL or CML current tree consists of one or more current switches

interconnected to form a circuit that resembles a binary tree. Each current switch

corresponds to a node in the tree. The coupled emitters of the root pair are connected to a

current source while the dangling collectors of the leaf current switches are connected to

either of the collector resistors. The base terminals of the current switch nodes are the

15

inputs to the circuit and are driven by other ECL or CML gates. When driven properly,

each pair of devices acts as a switch that allows current to flow from one device’s

collector terminal to a coupled emitter connection.

For proper operation of current tree circuits, saturation of the devices must be

avoided. This can be achieved by offsetting common mode voltage levels of inputs

signal pairs. If the two current switches are driven by input signals with the same

common mode voltage levels, the collector voltage of the conducting device in the lower

current switch which is equal to the voltage of the emitters of the upper current switch,

will try to drop significantly below the base voltage of the conducting device in the

lower current switch, thus the conducting device in the lower current switch saturates.

Offsetting the inputs signals is achieved by connecting emitter follower stages to the

outputs of CML current tree circuits, creating ECL circuits. CML circuits differ from

ECL circuits in that a CML circuit has no emitter followers driving the output signal.

The emitter follower stages (Figure 10, Figure 11) offset the common mode voltage of

an output by one or more VBE. The common mode output voltage of a particular ECL or

CML circuit is categorized by assigning a level number to the signal pair. The number is

generally the number of VBE drops between the signal and the current switch output

generated by emitter followers.

Figure 10 CML buffer with level 2 emitter followers.

16

Figure 11 CML buffer with level 3 emitter followers.

Level 1 signals generally have values 0 V and -250 mV. Level 2 signals have values

-900 mV and -1.2 V. Level 3 signals have values -1.8 V and -2.05 V. Level 3 signals are

generated by emitter followers followed by a diode, which is a transistor with shorted

collector and base terminals, to generate an additional VBE drop.

The size of pull-up resistors (the collector resistors) is based upon the current source

to produce a nominal voltage swing of at least 250 mV. For 1 µm sized transistors biased

at a current of 0.6 mA the resistors are set to 500 Ω.

One of the key needs for the ECL or CML current tree circuit is a constant current

source. The tree current should be kept constant to maximize the switching speed. The

value of this current can be depicted from the process’ fT vs. Ic characteristics. For the

designs used the current here is 0.6 mA for 1 µm devices. The simplest approach for

setting the current in current tree circuits would be placing a resistor on the bottom of the

tree. This passive current source has a high common mode gain on the lowest differential

pair and often requires a large resistor.

A more common approach for setting the current in current tree circuits is using an

active current source. Buffered Widlar current mirror, which is shown in Figure 12, is

used as an active current source in designs. This circuit provides a constant current

source with relatively small resistors and high output resistances.

17

Vref

R1

250Ω

Vcc

Vee

Q12x

2x

1.2 mA

Vee

500Ω

0.6 mA

Q2

Emitter

degeneracy

resistors

Figure 12 Buffered Widlar current source schematics.

The emitter degeneracy resistor typically has 0.3 V across it and it is used to control

currents which are smaller or larger than the mirror current. For instance, if a 4 µm

transistor requires 2.4 mA, then a 125 Ω emitter resistor will be used. The transistor Q2

is used for base current compensation and supplies the base current to all connected

circuits. It allows a larger number of sources to be used and prevents current degradation

when adding sources. The value of the resistor R1 is determined by the supply voltage.

18

Figure 13 2 input AND function schematics.

A current tree implementing a 2 input AND function (Z11=I11·J21) is shown in Figure

13 above. The current switch consisting of Q21 and Q20 steers current between the

current switches connected to it, depending the value of J21 and J20. If J21 is true, current

flows through Q11 when I11 is true, creating a voltage drop that indicates Z10 is false, and

thus Z11 is true. If I11 is false while J21 is true, current flows through Q10, creating a

voltage drop that indicates Z11 is false. If J21 is false, no matter what input I11 is, current

flows through Q20 creating a voltage drop that indicates Z11 is false.

A 2 input OR function (Z11=I11+J21) can be implemented with the same circuit if the

input polarities and output polarities are reversed.

19

Figure 14 2 input XOR function schematics.

A current tree implementing a 2 input exclusive-OR (XOR) function

(Z11=I11·J20+I10·J21) is shown in Figure 14. The current switch consisting Q21 and Q20

steers current between the current switches connected to it, depending the value of J21

and J20. If J21 is true, current flows through Q11 when I11 is true, creating a voltage drop

that indicated Z11 is false. If I11 is false while J21 is true, current flows through Q10,

producing a voltage of approximately Vcc on Z11, indicating Z11 is true. If J21 is false,

current flows through Q00 when I10 is false creating a voltage drop that indicates Z11 is

false. If I11 is true while J21 is false current flows through Q01, providing the voltage at

Z11 approaches Vcc, which make Z11 true.

A 2 input multiplexer can also be implemented with the same circuit, when upper

current switches are driven by different signals, i.e. Ia1 and Ia0 for Q11 and Q10, and Ib1

and Ib0 for Q01 and Q00. In this circuit J21 and J20 serve as a select signal for the inputs.

20

In order to store a logical value, latch circuitry is used. The latch is implemented

using an ECL or CML circuit as shown in Figure 15.

Figure 15 D type latch schematic.

When w21 signal is high, the latch enters write mode, allowing current to flow

through Q21 and the current switch consisting of Q11 and Q10. So in write mode the signal

values presented in d11 and d10 will be stored in the z11 and z10 lines. When w20

becomes high the current will flow through Q20 and the current switch consisting of Q01

and Q00. A positive feedback is achieved by connecting the bases of the devices Q01 and

Q00 to the output lines z11 and z10, as well as the collector of the opposite current switch

transistor. This maintains the voltage levels in the output terminals that were set in write

mode. That is, if d11 and z11 are high when w21 becomes low, current switches from

flowing through Q21 and Q11 to flowing through Q20 and Q01. This current continues to

flow through RC1, however, insuring that the voltage at the base of Q00 is sufficiently

21

lower than the voltage at the base of Q01. This prevents Q00 from conducting significant

current. Therefore, the current flow through Q01 will be maintained as long as w21 is

low, storing a true value in the latch. If d11 and z11 are false while w21 is high, similar

reasoning can be used to show that current flow is transferred from Q21 and Q10 to Q20

and Q00 when w20 becomes high, requiring z11 to remain false while w20 is high.

22

3. Register File Design

3.1 Design in 5HP

In the core of the pipeline register file lies four memory banks. Each of these memory

banks holds eight words of thirty two bits. All the memory cells have three ports; two

ports for read, and one port for write. These ports are designed to be used

simultaneously.

3.1.1 Structure of the Pipelined Register File

The register file is designed in three pipeline stages, as shown in Table 6. The first stage

(Address Decode, AD) decodes the addresses to be used in writing and reading from the

register file. The two reading addresses and writing address are compared in the first

pipeline stage as well. The second pipeline stage (MEMory operations, MEM) deals

with the memory writing and reading, as well as an initial selection process. Since the

memory banks composed of two read and one write port, it is possible to have an

overlapping reading address and writing address. In order to reduce the latency any

overlapping reading addresses and writing address is compared in the AD pipeline, and

it is fed to the second pipeline stage with a match signal stored in AD stage’s pipeline.

This match signal selects between the memory bank output and the data fed into the

register file to be written. After this selection process, the correct data is stored in the

MEM pipeline register. On the last pipeline (Thread Select, TS) the desired reading

thread is selected and stored in the TS pipeline register, and output from the pipelined

register file.

AD MEM TS

AD MEM TS

AD MEM TS

AD MEM TS

Table 6 Flow of pipeline stages.

23

Figure 16 Top level view of register file.

Figure 16 shows the block diagram of pipelined structure.

3.1.2 Address decoders

Address decoding is done by basic logic of NOR gates. The input addresses are driven to

the decoders with the buffers. The five bit address to each memory word is decoded in

two separate parts; two bits and three bits. The correct word location is determined by

combining the two bit and three bit decoders in another NOR gate. Layout of 2-bit and

3-bit address decoders are shown in Figure 17 and Figure 18 respectively.

Figure 17 Two-bit decoder layout.

24

Figure 18 Three-bit decoder layout.

3.1.3 Comparator

The comparator design is straight forward with each bit to be compared feeding a NOR

gate and all the bitwise comparison results and the write signal then being combined in

an AND gates to generate the match signal. If there is no writing involved the

comparator will automatically generate a low output. Figure 19 depicts the 5-bit

comparator schematic. Layout of the 5-bit comparator design is shown in Figure 20.

Figure 19 Five-bit comparator schematic.

25

Figure 20 Five-bit comparator layout.

3.1.4 Pipeline Register

This device stores the information until the next clock cycle. The stored information is

used in the pipeline stage right after the pipeline register. A master-slave latch is used in

the register file design. This provides a way to store data presented in the input of the

master-slave latch on the edge of the clock. The latches used in this circuitry are the

same storage elements mentioned in Chapter 2. The clock feeding the master is inverted

and fed to the slave in order to get the edge detection and triggering. Figure 21 and

Figure 22 show the schematic of the pipeline register and layout of the pipeline register

respectively.

Figure 21 Pipeline register schematic.

26

Figure 22 Pipeline register layout.

3.1.5 Memory cell

The memory cell, shown in Figure 2317, consists of four current switches and two

collector resistors. During a write operation, about 19.2 mA of current flows through

WW1 while no current flows through WW0. About 0.6 mA of the current flowing

through WW1 is directed through either Qd1 or Qd0, depending on the differential voltage

applied between WB1 and WB0 by the corresponding bit line driver. The current

through Qd1 or Qd0 produces a differential voltage between MC1 and MC0. The

magnitude of this voltage is determined primarily by the amount of current flowing

through WW1 that is directed through either Qd1 or Qd0 and the size of the collector

resistors, which in this case results in a differential voltage magnitude of 0.25 V. At the

end of the write operation, the current flowing through WW1 is redirected through

WW0. About 0.6 mA of this current flows through either Qf1 or Qf0, depending on

27

whether MC1 or MC0 is at a higher potential as a result of the write operation. The

positive feedback configuration of the devices Qf1 or Qf0 maintains the differential

voltage between MC1 and MC0 for as long as current is flowing through WW0. In this

way, the memory cell stores data in a manner similar to that of a D-latch. However, the

current switch that directs current between Qd1 and Qd0 or Qf1 and Qf0 based on whether

or not a write is asserted is not found in the memory cell. Choosing the current level

used in the memory cell is a compromise between providing as much current as possible

to write new values into a row of memory cells quickly and maintaining reasonable word

line metal widths without violating electromigration rules. Also, keeping the power

consumption to a reasonable level was a factor in the decision.

Figure 23 Memory cell schematic.

When a memory cell row is selected for a read operation through read port A, about

19.2 mA of current flows through RAW. For a particular memory cell, about 0.6 mA of

this current either flows through QRA1 or QRA0, depending on whether MC1 or MC0 is at

a higher potential, which in turn causes most of this current to flow through either RAB1

or RAB0. The value stored in the memory cell is determined by the sense amplifier

connected to RAB1 and RAB0, based on the current flowing in these two bit lines. The

28

value stored in the memory cell can be read simultaneously through port B using similar

methods. Layout of the memory cell in 5DM processing technology is shown in Figure

24.

Figure 24 Memory cell layout.

3.1.6 Word drivers

Each read word line driver consists of a single large device capable of handling as much

as 20 mA of current. This is necessary to drive a read port in every memory cell for a

single row. The base of each device is driven by the corresponding NOR gate from the

decoder. The emitters of all 32 devices are connected to a single current source as shown

in Figure 25. Since only one of the NOR gates is producing a high output signal, the VBE

of the read word driver device connected to this gate is significantly larger than that of

the other read word line driver devices. Therefore, nearly all the current sunk by the

current source flows through the selected read word line driver device, while the other

read word line driver devices are cutoff. Since the collector of each read word line driver

device is connected to the appropriate read word line of the corresponding row of

memory cells, current flows only through the selected read word line of each read port.

29

In this way, each memory cell in a selected row is able to drive its stored value onto the

appropriate set of bit lines while memory cells that are not selected for this read

operation do not significantly affect the state of the bit lines. The current source draws

about 19.2 mA, providing 0.6 mA for each of the 32 bit lines of a particular read port.

Figure 25 Read address word driver schematics.

The write word line driver, shown in Figure 26, consists of a pair of emitter-coupled

devices with emitters attached to a current source. When the NOR gate output is false,

no write operation is occurring. This means that WD0 is at a higher voltage than WD1,

causing current to flow through QR to drive the word line WW0. This results in current

flow through either Qf1 or Qf0 in the memory cells of the row driven by this particular

write word line driver, allowing the stored values in these memory cells to be

maintained. During a write operation for a particular row, the NOR gate output becomes

true. At this point, WD1 is at a higher voltage than WD0, causing current to flow

through QW to drive the word line WW1. This results in current flow through either Qd1

or Qd0 in the memory cells of the row driven by this particular write word line driver,

allowing the values driven onto the write bit lines to be written into these memory cells.

The current source in each write word line driver draws 19.2 mA of current to supply all

the memory cells of a particular row with the required current through either WW1 or

WW0, as described above. Because of the large amount of current handled by the write

word drivers, extremely large devices are required. To drive these devices more

effectively, the device sizes and current flowing through the emitter followers of the

ECL NOR gate were doubled.

30

WD1 WD0

Ics

Vee

QW Q

R

WW1 WW0

Figure 26 Write address word driver schematic.

3.1.7 Sense amplifier

As shown in Figure 27, in the sense amplifier a majority of the current flowing through

the read bit lines is provided by Qrb1 and Qrb0 in this case as well, producing a

differential voltage across o1 and o0 that is proportional to the difference in current

flowing on the two read bit lines. Rather than using a fixed bias voltage for Qrb1 and Qrb0,

however, a cross-coupled diode circuit is used to allow the voltages on the bit lines to

influence the biasing. This scheme improves the common mode rejection of the sense

amplifier. For instance, if rb1 and rb0 both rise due to noise coupling in this case, the

cross-coupled diodes force the bias voltages at the base of both Qrb1 and Qrb0 to rise as

well, resulting in no significant change in the voltage across the base-emitter junctions of

these devices. Therefore, there is no significant change in the current flowing through

Qrb1 and Qrb0, and as a result, no significant change in the output differential voltage of

the sense amplifier.

Since the voltage of every read bit line is biased about one VBE drop below VCC by

the sense amplifiers, it is necessary to insure that the memory cell current switches that

direct current between the read bit lines are driven at level 2 to avoid saturation.

Although this could be done by connecting TW of the memory cells to VCC using emitter

followers to level shift the voltages at nodes MC1 and MC0 to level 2, it would require an

additional four devices in every memory cell as well as a significantly larger power

dissipation. Instead, a single diode was connected between VCC and TW for each row of

memory cells to shift the level of MC1 and MC0 to level 2 for every memory cell. This

solution only requires 32 diodes capable of handling the current drawn by the write word

line drivers. Because MC1 and MC0 are at level 2, the memory cell devices Qf1 and Qf0

31

are driven at level 2. For this reason it is necessary for the write word line drivers to

receive level 3 inputs to prevent devices in the write word line drivers from saturating.

Because the memory cell current switches that direct current between the read bit lines

are driven at level 2, it is also necessary for each read word line driver to receive a level

3 input to prevent the read word line driver devices from saturating. Finally, since MC1

and MC0 are at level 2 and the write word line drivers receive level 3 inputs, it is

necessary to drive the memory cell devices Qd1 and Qd0 at level 2 by the bit line drivers.

Driving Qd1 and Qd0 at level 1 would saturate the devices, while driving them at level 3

would saturate devices in the write word line drivers.

Figure 27 Sense amplifier schematic.

Layout of the array of memory cells and sense amplifiers are shown in Figure 28.

32

Figure 28 Layout of memory cells and sense amplifiers for one memory bank (8 words by 32-bits).

3.1.8 Multiplexer

The multiplexers are formed in a way described in Chapter 2. The circuits and layouts of

2:1 and 4:1 multiplexers are shown in the Figures 29 through 32.

33

Figure 29 Two-to-one multiplexer schematic.

Figure 30 Two-to-one multiplexer layout.

34

Figure 31 Four-to-one multiplexer schematic.

Figure 32 Four-to-one multiplexer layout.

35

3.2 Fabricated test chip in 5DM

The fabricated test chip using the 5DM processing technology is shown in the Figure 33

and Figure 34.

Figure 33 Layout of the test chip designed with 5DM technology.

36

Figure 34 Microphoto of the test chip designed in 5DM technology.

3.3 Design in 7HP

A chip featuring the register file design along with some testing circuitry was designed.

The chip includes a register file of 8 words of 32 bits. To simplify the design and to

minimize the area requirements a single memory bank was put into the design. This

simplified design can be used to test the functionality of the design. The design features

two pipeline stages. The first pipeline stage is used to decode the addresses, and the

second stage executes the memory read and write operations based on the decoded

address signals from the first pipeline stage. A Voltage Controlled Oscillator (VCO)

was also incorporated to generate adjustable clock signal required for operation.

Counters were used to generate the test signals both for read and write addresses along

with data input to the registers. The output selection is managed by a bank of

multiplexers. A triggering signal is generated by dividing the clock by 16 in frequency.

The same design is also used in a CPU core test chip as well. Two 8 words by 32

bits register files are used in the CPU core chip. One of these register files is used for

instruction storage, while the second register file is used for data storage. A pipelined

37

structure is used in the register files to increase the frequency of operation to keep up

with the ALU. The first pipeline stage executes address decoding and address collusions

while the second pipeline stage executes the memory read/write operation as well as

correct output selection if needed due to address collusion.

For correct operation on the edges of the clocks, master-slave latches are used for

pipeline registers. D-type latches are implemented in CML logic trees. In data output

pipeline registers a hybrid form of a CML tree that performs multiplexer operation along

with latching is used for the master latches, whereas a conventional D-type CML tree

latch is used in slave latches.

The basic memory cell used in the register files is based on CML logic and has 3

ports: two read-out ports, and one write-in port. Due to multi operations performed

during one cycle, there exists an inherent possibility that a data word is requested to be

read while it is requested to be written in the same cycle. In order to avoid such a

collision of read and write addresses two comparator circuits are introduced in the

address decoding cycle of the address pipeline of the register file. One of the

comparators is assigned to detects a collusion between first read port address (read port

A) and write address, while the second is assigned to detect collision between second

read port address (read port B) and write address. If such a collision occurs, the result of

the comparator is stored on the pipeline register to be used as a select signal for the

register file output multiplexer.

The addresses fed to the register file is first decoded and stored in the pipeline

register to be driven to the word lines in the second pipeline stage. The data that is to be

written to the register file is also stored in pipeline registers to be used in the second

pipeline stage that executes the memory operations.

To reduce the wire length and the time delay associated to it, the 32-bit words are

divided into two for the layout. Between the 16-bit portions are placed the necessary

address decoding circuitry with necessary pipeline registers. This approach, compared to

feeding the necessary word lines from one side of the 32 bit circuitry, reduces the wire

length reaching out to the far end memory cell by a factor of two. This can be seen in the

following Figure 36.

38

Figure 35 Layout and schematics of the memory cell used in 7HP design.

39

Figure 36 Register file layout, depicting different submodules.

The addressing circuitry modules in Figure 36 (modules M, N, P, R and S) divide

the memory cell arrays into identical 16 bit modules, that can be seen on the west and

east side of the addressing circuitry. These addressing modules can be described as

follows:

M. Address decoder for first read port (readA) and pipeline registers for

decoded results.

S. Address decoder for second read port (readB) and pipeline registers for

decoded results.

R. Address decoder for write port and pipeline registers for decoded results.

40

N, P. Comparators for request collusions between write address and readA and

readB, respectively.

G. 8 words of 16 bits array of memory cells.

F, H. Sense amplifiers for readA and readB, respectively.

E, J. Level shifter drivers for readA and readB, respectively.

D, K. Output multiplexer / output master latch for pipeline registers.

B, L. Output slave latches with emitter followers for pipeline register.

C. Write bit line drivers

A. Data input master-slave latches.

The address inputs and the write enable signal are fed to the register file from the

west side. The data that is to be written are fed to the circuit from the north side. The

outputs of readA and readB are from the north and south side of the register file

respectively.

3.4 Fabricated test chip in 7HP

The sections of the design that are shown in Figure 37:

A. VCO used to generate the clocking signal.

B. Multiplexer used to select between on-board clock signal and external clock

signal.

C. Series of buffers used to repeat and drive the clock signal.

D. Bondpads, pad drivers and pad receivers used to for input and output.

E. Complete register file design including decoders, sense amplifiers and output

selectors.

F. Counters used for address signal generation and date input generation.

G. A master-slave latch to synchronize the externally input write enable signal

to the clock.

H. A counter used to carry out divide by 16 function that generates the trigger

signal.

J. Output multiplexer to select the signal to be observed on the output.

41

Figure 37 Top-level schematics for the register file chip designed with the 7HP technology.

42

Figure 38 The layout of the test chip designed in 7HP.

The layout of the test chip designed in 7HP, which is shown in Figure 38, consists

of the following sections:

A. Bondpads, pad drivers and pad receivers.

B. Memory cell arrays.

C. Data input circuitry with first stage pipeline registers and readA port

circuitry along with second stage pipeline registers.

D. Read port B circuitry along with second stage pipeline registers.

E. VCO.

F. Counters used as data and address generators.

G. Output select multiplexers.

H. Address decoders and first stage pipeline registers.

43

Figure 39 The microphoto of the test chip designed in 7HP.

Figure 39 shows the microphoto of the test chip designed in 7HP.

44

3.5 7HP test chip simulation

Figure 40 Simulation results of the register file test chip.

An initial simulation with a 21 GHz clock is shown above in Figure 40. This

simulation result does not include parasitics. Simulations including parasitics are

currently in progress. With parasitics included, the estimated clock rate is expected to

drop down into the 16 GHz range.

45

4. Buffer and Simple Gate Driving Capabilities

This section shows the result of a study of SiGe and CMOS drive capacity for use in

either clock driving applications or large off chip I/O load driving. In standard

computational structures CMOS has a size and power advantage over SiGe CML. In

applications where a large load is being driven by the circuit CMOS devices tend to be

limited by the large turn on resistance of the devices. The turn on resistance of the

CMOS devices are, for a given process, affected by the width to length ratios of the

devices as well as the power supply voltage.

This study compares these two circuit families in the IBM high performance

processes. It has been noted in literature18 that comparably sized buffers for SiGe

perform 4 or more times faster than there CMOS counterpart. The SiGe advantage will

be further increased when input driver loading and CMOS tapering are taken into

account. Even though these simulations will demonstrate a significant bipolar advantage

the advantage is constrained by the presence of deep trench isolation (DTI) in the bipolar

devices, compounded by the somewhat more constraining design rules for the bipolar

devices. Another process-based disadvantage, which the bipolar devices are subject to, is

the wire sizing to prevent electro-migration. Even though the CMOS devices and the

Bipolar devices might need to source and sink comparatively large currents, the CMOS

device sources and sinks these currents solely during switching transient, whereas the

Bipolar devices have a static current flowing through the emitter follower which is used

to source and sink current from the load. In consequence, when designing the circuit the

CMOS device may take advantage of the less stringent limitations placed on RMS

current flowing through wires, whereas the bipolar device needs to satisfy the design

rules for DC current. This constraint limits the level of compactness possible in the

design of the bipolar circuit. New materials as well as a better conducting copper wires

with a defect free structure could increase the current permissible without inducing

electro-migration. In consequence, the comparisons are limited not only by the relative

strengths and weaknesses of the two devices but also by the process limitations. More

research into increasing the placement density of bipolar devices would certainly make

their performance significantly better for a given area.

46

The bipolar transistors that have larger emitter areas are slower than smaller emitter

sized bipolar transistors, as can be seen in the design manuals of SiGe design kits. They

have a lower peak fT point. However since heavy loads are being charged, the peak fT is

not the dominating factor it is instead the current available to charge and discharge the

loads. This current must be taken away from the emitter-followers or added to the

emitter followers depending on whether the circuit is charging or discharging. This can

also be seen when viewing the current in the simulation. The changes in current prevent

the emitter-follower from switching exactly at peak-fT. And the extent to which current

can be sourced or sinked is limited by the current source and the internal resistance of

the transistors.

Layout of two inverters driving a capacitive load is needed, one being bipolar, the

other CMOS with the W/L ratios of the nFET and pFETs sized to make the two layouts

have approximately the same area. This will require approximately 10-20:1 ratio. Then

attempt to reproduce the figure that is in one of the references which shows the bipolar

device exhibiting a faster rise time. The on resistance of the minimal W/L =1 FET is

about 9 KΩ using a 5 V supply. It increases linearly with lower voltages, so at 2.5 V one

might see 18 KΩ. The on resistance of an emitter follower might be 180 Ω, a factor of

100 lower. For width to length ratios of 10-20 the advantage still goes to the bipolar.

However, this assumes that the HBT will laterally shrink as the FET does. But DTI is

not shrinking in available design kits. Also, the voltage is falling towards 0.5V for FETs,

in which case the FETs on resistance climbs to 90 KΩ. Some features of the FET, such

as contact areas, won't shrink either.

47

Figure 41 Bipolar buffer schematic in 7HP.

The 7HP designs of bipolar and CMOS circuitry is used as a comparison basis for

5DM and 8HP designs. The 7HP buffer schematic is shown in Figure 41. The current

source of the Current Mode Logic (CML) tree is constructed with an nMOS devices in

order to minimize the layout size and device count of the circuit. The bipolar devices in

the first buffer stage have dimensions of 0.2 µm by 3 µm. The bipolar devices in the

second emitter follower stage are in the dimensions of 0.2 µm by 18 µm. The selection

of device sizes provides minimum loading on the source of the circuit while maximizing

the driving capability. The currents of the bipolar devices are set to the peak collector

currents to achieve the maximum operating frequency.

48

Figure 42 Bipolar buffer layout in 7HP.

Layout of the bipolar buffer as shown in Figure 42 uses an area of approximately 24

µm by 24 µm.

Figure 43 Tapered CMOS inverter schematic in 7HP.

In order for CMOS inverters to be driven by a minimum feature a size CMOS

device tapered buffer structure is used in CMOS inverters. The layout area of the CMOS

inverter is chosen so that it would match the area of the bipolar buffer. The depth of the

tapered chain is determined by the layout size of the design. The effective width to

49

length ratio of the NMOS is 538 and the effective width to length ratio for PMOS is

1458. Schematic of the tapered CMOS inverter is shown in Figure 43.

Figure 44 CMOS inverter layout in 7HP.

Layout of the tapered CMOS inverter as shown in Figure 44, uses an area of

approximately 63um by 10.5um.

50

Figure 45 Simulation result depicting the rise time of bipolar buffer and tapered CMOS inverter

driving 0.5 pF capacitive load.

Figure 45 shows the simulation results of the rise time of the bipolar buffer (on the

left, 14 ps) and tapered CMOS inverter (on the right, 59ps) driving 0.5 pF capacitive

load.

Figure 46 Simulation result depicting the fall time of bipolar buffer and tapered CMOS inverter

driving 0.5 pF capacitive load.

Figure 46 shows the simulation results of the fall time of the bipolar buffer (on the

left, 13.5 ps) and tapered CMOS inverter (on the right, 59 ps) driving a 0.5 pF capacitive

load.

51


driving 1 pF capacitive load.


left, 18 ps) and tapered CMOS inverter (on the right, 79 ps) driving 1 pF capacitive load.




left, 18.5 ps) and tapered CMOS inverter (on the right, 75.5 ps) driving 1 pF capacitive

load.

52




left, 79 ps) and tapered CMOS inverter (on the right, 414 ps) driving 10 pF capacitive

load.




left, 114 ps) and tapered CMOS inverter (on the right, 383 ps) driving 10 pF capacitive

load.

53




left, 690 ps) and tapered CMOS inverter (on the right, 3.85 ns) driving 100 pF capacitive

load.




left, 1.25 ns) and tapered CMOS inverter (on the right, 3.52 ns) driving 100 pF

capacitive load.

54


driving 50 Ω terminated transmission line.


left, 10.3 ps) and tapered CMOS inverter (on the right, 62 ps) driving 50 Ω terminated

transmission line (3 mm long with .5 c velocity of propagation).


driving 50 Ω terminated transmission line.


left, 12.2 ps) and tapered CMOS inverter (on the right, 41.5 ps) driving 50 Ω terminated

transmission line (3 mm long with .5 c velocity of propagation).

55

Figure 55 Bipolar AND schematic in 7HP.

Figure 55 depicts bipolar AND schematic in 7HP. The bipolar devices in the AND

stage have dimensions of 0.2 µm by 3 µm. The bipolar devices in the second emitter

follower stage have dimensions of 0.2 µm by 18 µm.

Figure 56 Bipolar AND layout in 7HP.

56

Layout of the bipolar AND in 7HP which is shown in Figure 56 uses an area of

approximately 39 µm by 17 µm.

Figure 57 CMOS NAND schematic in 7HP.

Figure 57 depicts CMOS NAND schematic in 7HP. Effective width to length ratio

on NMOS devices are 600 and PMOS devices are 867.

Figure 58 CMOS NAND layout in 7HP.

The layout of the CMOS NAND which is shown in Figure 58 uses an area of

approximately 40 µm by 18.5 µm.

57

Figure 59 Simulation result depicting the rise time of bipolar AND and tapered CMOS NAND


Figure 59 shows the simulation results of the rise time of the bipolar AND (on the

left, 19.5 ps) and tapered CMOS NAND (on the right, 107.5 ps) driving 1 pF capacitive

load.

Figure 60 Simulation result depicting the fall time of bipolar AND and tapered CMOS NAND


Figure 60 shows the simulation results of the fall time of the bipolar AND (on the

left, 18.5 ps) and tapered CMOS NAND (on the right, 90.5 ps) driving 1 pF capacitive

load.

58

7HP Simulation Results 0.5 pF (ps)

1 pF (ps)

10 pF (ps)

100 pF (ps)

50 Ω terminated

transmission line

Bipolar Buffer Rise time 14 18 79 690 10.3

Bipolar Buffer Fall time 13.5 18.5 114 125 12.2

Tapered CMOS inverter Rise time

59 79 390 3850 40

Tapered CMOS inverter Fall time

59 75.5 414 3520 22

Bipolar AND Rise time 15 19.5 79 656 12

Bipolar AND Fall time 13.5 18.5 110 1190 12

CMOS NAND Rise time 83 107.5 616 5850 46

CMOS NAND Fall time 63 90.5 557 5300 30

Table 7 7HP simulation results.

7HP simulation results are summarized in Table 7. Bipolar devices of 0.2 µm by 3

µm and 0.2 µm by 18 µm are used in 7HP simulations. The bipolar devices’ currents are

set to the peak collector currents to achieve the maximum operating frequency. On

CMOS circuits voltage sources of 1.5 V are used in accordance with design manuals to

maximize the performance of circuits

59

5DM Simulation Results 0.5 pF (ps)

1 pF (ps)

10 pF (ps)

100 pF (ps)

50 Ω terminated

transmission line

Bipolar Buffer Rise time 24.30 32.92 131.28 1409.28 27.86

Bipolar Buffer Fall time 22.04 32.14 207.83 2313.93 27.95


586 1071.84 10230.8 101656 124.22


376.29 673.31 6258.5 62400.2 156.278

Bipolar AND Rise time 24.76 33.05 129.67 1346.05 28.92

Bipolar AND Fall time 21.42 31.28 200.60 2269.64 28.87

CMOS NAND Rise time 2977.46 5857.82 115022 1142900 23.52

CMOS NAND Fall time 539.822 1049.23 10259 101874 11.53

Table 8 5DM simulation results.

5DM simulation results are summarized in Table 8. In the 5DM simulations bipolar

devices of size 0.5 µm by 3 µm and 0.5 µm by 18 µm devices are used. This yielded

comparable layout sizes to the 7HP designs. The bipolar devices currents are set to the

peak collector currents to achieve the maximum operating frequency. The CMOS

devices used in the 5DM analysis are selected so that they would match the layout

requirements of the similar 7HP design. The tapered CMOS inverter structure is used to

minimize the loading effect of the circuit while maximizing the output driving

capability. On the CMOS circuits voltage sources of 3.6 V are used in accordance with

design manuals to maximize the performance of circuits.

60

8T/8HP1 Simulation Results 0.5 pF (ps)

1 pF (ps)

10 pF (ps)

100 pF (ps)

50 Ω terminated

transmission line

Bipolar Buffer Rise time 9.02 11.93 50.75 436.36 6.64

Bipolar Buffer Fall time 8.39 11.95 90.86 978.91 6.66


62.55 93.51 635.92 5974 63.59


42.66 55.63 320.15 3051.6 28.46

Bipolar AND Rise time 9.27 12.24 51.32 443.07 6.68

Bipolar AND Fall time 8.51 12.14 91.61 993.89 6.69

CMOS NAND Rise time 40.85 54.07 328.30 3049.76 37.83

CMOS NAND Fall time 47.41 71.57 517.59 5016.7 21.01

Table 9 8T/8HP simulation results.

8T/8HP simulation results are summarized in Table 9. The bipolar devices on the

current available 8HP design kit have multiple emitters. For a fair comparison bipolar

devices of the 8T design kit are used. The dimensions of bipolar devices are 0.12 µm by

3 µm and 0.12 µm by 18 µm. The currents of bipolar devices are set to the peak collector

currents to achieve the maximum operating frequency. On CMOS circuits voltage

sources of 1.5 V are used in accordance with design manuals to maximize the

performance of circuits. The tapered CMOS inverter chain starts with the minimum size

devices and the depth of the tapered chain is determined by the layout area of the tapered

chain.

While the CMOS simulations in 7HP and 8HP results are similar in scale, 5DM

results differ radically. The reasons why the 5DM results differ is still under

investigation.

1 Bipolar circuits using 8T, CMOS circuits using 8HP.

61

5. Test Chip Design

5.1 5DM register file test chip overview

The purpose of the 5DM register file test chip is to provide means of testing the

functionality and performance of the register file. The testing scheme is similar to a

scheme developed to test 1-Kb RAM implemented in using IBM SiGe 5HP

technology17. A block diagram of the test chip is show in Figure 61. During normal

operation, three5-bit counters supply the register file with repeating patterns of

sequential addresses for read and write operations. A rotator/LFSR (Linear Feedback

Shift Register) supplies the register file columns with a repeating pattern that is used as

input data for write operations. Using these circuits, data can be written into the register

file and then read using either read port to determine whether or not the register file is

functioning properly. A scan mode also exists in which the counters and the

rotator/LFSR are linked in a scan chain that allows data to be serially loaded into the

counters and the rotator/LFSR. This is useful for providing specific patterns of input data

for the rotator as well as for offsetting the addresses of the counters by a set amount.

Table 10 lists the register file test chip I/O pads, along with descriptions of their

functions.

62

Counter Rotator/LFSR Counter Counter

Scan

VCO

Control

External

Clock

Clock

Select

Shift In

Clock

Muxes

Mux

Muxes

8 5 55

16 16

External

Write

Write

Select

Write

Enable

Write

Delay

`Write Address Data In Read Address Read Address

Register File

Data Out A Data Out B

Write Enable

Match A

Clock

Mux

Mux

Output Select B

Output Select C

2

2

1

Frequency

Divider

Write

Generator

Synch

Out

Scope Output

2 Output Select A

Figure 61 5DM test chip block diagram.

Pad Name Description

Analog Control Selects VCO frequency within the selected band.

Clock Select Selects between VCO and external clock.

External Clock Clock for shift operations. Can be used in test mode as well.

External Write Enables an asynchronous write operation.

Output Select Selects signal that is driven off-chip for viewing.

Scope Output Produces an output signal to be viewed on an oscilloscope.

Sync Output Produces a trigger signal for the oscilloscope.

Scan Selects between scan and test modes of test chip operation.

Shift In Provides data for the scan chain.

Write Delay Selects clock delay to optimize synchronous write operations.

Write Enable Enables synchronous write based on the selected clock.

Write Select Selects between external and synchronous write signals.

Table 10 List of 5DM register file test chip pads and their functions.

63

Each address decoder is designed as a 5-bit stat machine. Each counter is composed

of a 5-bit register which stores the state of the counter, and a next state decoder, which

computes the new state to load into the register during the next clock cycle. Edge

triggered latches are required in the register implementation for the state machine to

function properly. These types of latches capture and store data on each rising or falling

clock edge. Without this capability, data appearing at the outputs of the register can

propagate back through the next state decoder and alter the original data written into the

latches before the write operation of the original data has completed. One method of

approximating edge-triggered behavior is to use what is known as master-slave latch.

This latch is simply two D-latches connected in series, where the clocking drives the first

latch (the master) is inverted with respect to the clock driving the second latch (the

slave). If the clocks are arranged such that the slave latch writes when the clock is high

and the master latch writes when the clock is low, data to be latched into the master-

slave latch is first stored in the master when the clock is low. When the clock becomes

high, data stored in the master is then written into the slave and the master stops writing

new data. Therefore, if the input data changes after the initial rising edge of the clock,

the data is not passed on o the slave, resulting in the preservation of the data written into

the slave at the rising edge of the clock. At the falling edge of the clock, data can again

be written into the master, but at this point the slave has stopped writing data. Therefore,

the data is not written into the slave until the next rising clock edge. A falling edge-

triggered master-slave latch can be made simply by allowing the master to write when

the clock is high and allowing the slave to write when the clock is low.

64

Select A3

Select A2

Power

Ground

Select B3

Select B2

Power

Ground

Select C3

Select C2

Power

Ground

Figure 62 5DM test chip pad arrangement.

5.2 Address counter design

The gate level schematics for the read address counter, that is shown in Figure 63,

contain five rising edge-triggered master-slave latches. These store the state of the

counter. The next state decoder is simple conceptually. During normal operation, for

each bit, if every lower order is high, the bit should change its state at the next rising

clock edge. In all other cases, the bit should keep the same state. For the least significant

bit, this implies that this bit should change state on every rising clock edge. This

algorithm will produce a 16-cycle repeating pattern from 0 to 15 using a five digit binary

format, that is stored in the master-slave latches. The next state logic is implemented

using XOR and AND gates. Some of these gates are combined in a single current tree.

The XOR gates serve as programmable inverters. Assuming one input terminal of the

XOR gate is the data and the other input terminal is the control, when the control input

terminal is low, the data passes through the XOR gate unaffected. However, when the

control input terminal is high, the data going through the XOR gate is inverted.

65

Therefore, an XOR gate can be used to change the state of a particular stored bit, which

is fed into the XOR gate data input terminal, given the AND of all the low order stored

bits produces a high value, which is fed into the XOR gate control input terminal. Note

that each master-slave latch has a 2-to-1 multiplexer combined into the master slave

latch. This allows input data from the next state decoder to be selected during normal

operation to provide counting operation, or data from the previous latch in the scan chain

to be selected during scan operation. In scan mode, data shifts through the address

counters from least significant bit to the most significant bit. Since the read address

counters must drive the read address decoders of the register file, level 2 outputs were

included on every latch. The write address counter, shown in Figure 64 is identical to the

read address counters with the exception of additional level 3 outputs that used for

feeding register file comparators.

66

I1

I0

S

Q1

Q2

Q3

I1

I0

S

Q1

Q2

Q3

I1

I0

S

Q1

Q2

I1

I0

S

Q1

Q2

I1

I0

S

Q1

Q2

SHIN1

SCAN2b

CLK3

Q20

Q21

Q22

Q23

Q24

SHOUT1L1 L1

L1

L1

L1

L1

Figure 63 Read address counter gate level schematics.

67

I1

I0

S

Q1

Q2

Q3

I1

I0

S

Q1

Q2

Q3

SHIN1

SCAN2b

CLK3

Q20

Q21

Q22

Q23

Q24

SHOUT1L1 L1

L1

L1

L1

L1

I1

I0

S

Q1

Q2

Q3

I1

I0

S

Q1

Q2

Q3

I1

I0

S

Q1

Q2

Q3 Q34

Q33

Q32

Q31

Q30

Figure 64 Write address counter gate level schematics.

5.3 Linear Feedback Shift Register

An LFSR is a shift register with feedback to allow it to produce a sequential bit pattern

that is a pseudo-random in nature. The feedback signal, which is the XOR of the last

latch output and one or more other latch outputs from the shift register, is fed into the

input of the first latch of the shift register. Therefore, the LFSR requires no input data.

The feedback is designed to allow the LFSR to visit each of the possible states except

68

state 0, where all the latches store signals representing 0. Since XOR of any number of 0

inputs is a 0 output, an LFSR with all latches in the false state will continuously shift

false values through the shift register, remaining in state 0 indefinitely. Therefore, an

LFSR with N latches will have all the states except 0, (2^N)-1 states it visits normally.

This means that a repeating pattern of (2^N)-1 bits can be obtained by using the output

of any of the LFSR latches. Of course patterns at the outputs of the latches will be

identical, but just shifted in time. Table 11 shows possible sets of latch outputs that can

be fed into a XOR gate to produce a LFSR out of a shift register for a number of

different size shift registers.

Size XOR bits Size XOR bits

1 0 5 1,4

2 0,1 6 0,5

3 0,2 7 0,6

4 0,3 8 0,4,5,7

Table 11 List of shift register latches that can be XOR'ed to produce LFSR's of different sizes.

For the 5DM register file chip, a 6-bit LFSR that is capable of 63-bit pattern is used

for data generation. This 63-bit pattern was sufficient to test initial design of 4 register

file banks for the test chip. Each register file is composed of 8 words of 32-bits. The 4

register file bank approach is later reduced to two register file banks for sake of

simplicity and testability in the test chip.

A LFSR design that was previously fabricated and tested is selected to be used in

the 5DM test chip in order to increase the testability. This circuit incorporates a 8-bit

rotator to the LFSR and designed by Dr. Sam Steidl17 using a, a former member research

group.

The schematics of data rotator/LFSR is shown is shown in Figure 65. The circuit

contains eight shift register latches. The first latch in the shift register chain contains an

integrated multiplexer. In scan mode, this multiplexer selects the scan in data form the

write address counter. However, in test mode the multiplexer selects data from another

multiplexer with an integrated XOR gate feeding one of its inputs. Therefore in test

mode, if the rotate option is selected, the second multiplexer selects data from the last

latch on the scan chain, allowing the data in the shift register to cycle through the latches

69

indefinitely, producing a rotating data pattern. However, if the LFSR option is selected,

the second multiplexer selects the XOR of the first and the sixth latches on the scan

chain, producing a LFSR state machine using the first six latches in the shift register. In

this case the last two latches in the shift register simply produce shifted versions of the

63-bit LFSR pattern, which is

101010110011011101101001001110001011110010100011000010000011111. In the

event the LFSR starts up in a state where all latches are in zero state, the LFSR will

remain in this state indefinitely as long as the test chip is in the test mode. The test chip

can be placed in scan mode, however, to allow a new state to be shifted into the LFSR.

This will allow the LFSR to function properly when the test chip is returned to test

mode.

Figure 65 8-bit data rotator/6-bit LFSR gate level schematics.

5.4 Voltage controlled oscillator

The common approach in the design of a standard ring oscillator stage without feed

forwarding is to use delay interpolation as shown in Figure 6614. The idea is to split the

input signal into slow and fast path and create a weighted sum of the two to form the

output. Common pull-up resistors, level 3 control inputs, and emitter resistors for

linearity make this possible. The slow path need only delay the signal longer than the

fast path, a simple capacitor can do the trick. The benefits of this VCO stage include a

uniform output voltage swing, a fairly linear response, no limits of operation, and easy

minimum frequency control through the capacitor.

70

n

n-1

n-2

B

C

A

D

Figure 66 VCO schematics.

The fast path could be implemented as the signal from the stage before the previous

stage and the slow path could be the previous stage in order to simplify the design. This

approach will increase the speed of the VCO.

This makes Feed Forward Interpolated (FFI) VCO a delay interpolated VCO with the

normal and delayed signals created from different stages rather than from within each

stage. This implies each stage has to have two inputs rather than one. The schematic for

the FFI stage is shown in Figure 67.

71

Figure 67 FFI stage schematics.

The FFI VCO linearly interpolates the signals received from the previous two

stages. The current, which remains the same through the tree, is gradually shifted

between the two inputs. The previous input (p) arrives from the stage back, and the leap

input (l) arrives from the stage prior to that. Two signals are weighted by the control

signal and summed by the control pull-up resistors.

The minimum frequency operating frequency is defined by the oscillation of the

system when the leap signal is ignored, and only the previous signal is used. In this case,

the system is running as four stage ring oscillator. When the control voltage is switched

the other direction, the leap signal is used, and the previous stage's output is ignored. In

this configuration the system is running as two separate two stage ring oscillators.

The effective delay of a stage is defined to be the delay of a four stage oscillator that

has the same frequency as the feed forward oscillator. This parameter is found by setting

the intrinsic delay of a stage to T, setting s equal to the weighting factor between 0 and

1, and looking at the output transition times of stages, n, n-1 and n-2. The weighting

factor is a constant that indicates how much of the leap signal is being used. Set to the 0

72

the ring acts as a normal 5 stage oscillator, and set to 1 the ring acts as a 2 stage

oscillator.

The edge time of the stage n is given by, 12 )1( −− −++= nnn tsstTt which is the

intrinsic delay through the stage, plus the weighted sum of the previous two stages.

Solving for the time difference between two stages yields:

)1(1 s

TttT nneff +

=−= −

T

s

Tf

effVCO 8

)1(

8

1 +== ,

which is the effective delay and the frequency of the VCO in terms of the intrinsic

delay of each stage. The factor of eight is needed because it takes two complete cycles

through four stages to equal one period of VCO.

For s equal to 0, the effective delay is equal to the intrinsic delay of the stage. At the

other extreme, when s equals 1, the effective delay is one half of the intrinsic delay. This

makes sense because the system in this configuration is has two stages rather than four.

The use of feed forwarding techniques allows the VCO to exceed the maximum

frequency achievable by a simple four stage ring oscillator. Current through the FFI

stage is linearly switched between the previous and feed forward stages. This forces the

total current running through the stage to remain constant. This is important for keeping

a constant voltage swing, which ensures consistent operation in a system where a

variation in voltage swing would cause a change in frequency. This signal to noise

(SNR) ratio is also dependent on the output voltage swing.

Differential signaling is used for the control input and throughout the rest of the

design. This is crucial when designing for low noise operations since differential wires

have strong common-mode rejection.

5.5 Viewing register file test chip signals

Because of limited chip probing capability, only one output pad is available on the test

chip. For this reason, a tree of multiplexers is used to select data to view from particular

register file column through either read port. The test chip design only allows one to

observe the output of one half of the register file columns from each reach port. Four 4-

73

to-1 multiplexers are used to select the output of four columns from the 16 available

columns for each read port. Another 4-to-1 multiplexer is used to select the output of

four selected columns for each read port. Other signals that can be observed include the

most significant bit of each counter and the last rotator bit, which are selected using a 4-

to-1 multiplexer. This multiplexer also receives input data from a 2-to-1 multiplexer,

which is used to select between the clock and the read port A match signal for

observation. Finally, a 4-to-1 multiplexer is used to select between the above mentioned

signals for observation through the pad driver. The manner in which these signals are

selected is illustrated in Figure 61. Six select signals obtained from input pads control

the selection through the multiplexer tree. The manner in which these signals determine

the output signals determine the output signal selection is summarized in Table 12

through Table 14.

Select A3 Select A2 Description

0 0 Chip clock or Match signal

0 1 Read port A output

1 0 Read port B output

1 1 Counter, Rotator/LFSR

Table 12 Output pad signal as a function of Select A3 and Select A2.

Select B3 Select B2 Select A3=0

Select A2=0

Select A3=0

Select A2=1

Select A3=1

Select A2=0

Select A3=1

Select A2=1

0 0 Clock Column Column Rotator/LFSR

0 1 Clock Column Column Read Counter B

1 0 Match A Column Column Write Counter

1 1 Match A Column Column Read Counter A

Table 13 Output pad signal as a function of Select A2, Select A3, Select B2, Select B3.

Select B3, B2, C3, C2 Column Select B3, B2, C3, C2 Column

0000 0 1000 16

0001 2 1001 18

0010 4 1010 20

0011 5 1011 21

74

0100 8 1100 24

0101 10 1101 26

0110 12 1110 28

0111 13 1111 29

Table 14 Column selection as a function of Select C2, Select C3, Select B2, Select B3.

5.6 Pad receiver design

The circuit design for a level 2 and level 3 pad receiver that accepts a single-ended

signal from an input pad is shown in Figure 68. To provide protection against damage to

the bipolar device connected to the pad large diodes knows as electrostatic discharge

(ESD) devices are connected between the pad and the Vcc and the between pad and the

Vee. The diodes are reverse biased under normal condition and therefore have little

influence in the normal circuit behavior. However, in the event of a large electrostatic

build up on the pad, the charge is shunted to either Vcc or Vee through one of these

diodes.

z30

Vcc

Vee

z31z20

z21

Pad

4x

4x4x

4x

4x

4x

4x

4x

4x

320 Ω 320 Ω

4 mA 4 mA 4 mA 4 mA1 mA

Vref

Figure 68 Pad receiver schematics.

75

The input pad drives an emitter follower, which in turn drives one side of a single

ended ECL buffer. The emitter follower devices are much less susceptible to damage

from electrostatic discharge. Another emitter follower circuit is used to generate a

reference voltage (Vref) for a number of pad receiver circuits. Its input is tied to Vcc while

its output drives the other current switch terminal of the ECL buffer. Therefore, when

input pad voltage is Vcc, both pad receiver output voltage levels are about equal. When

the pad input voltage becomes significantly greater than Vcc, the output differential

voltage of the pad receiver indicates a high logic value. When the pad input voltage

becomes significantly less than Vcc, however, the output voltage of the pad receiver

indicates a low logic value. If the input is left floating, a diode connected between Vcc

and the input pad is turned on, making the input pad voltage a diode drop below Vcc.

Therefore, the pad receiver produces a differential voltage corresponding to a low logic

value when the input left floating. For pad receivers requiring output levels other than

level 2 or level 3, the output emitter follower stages can be altered or removed. The input

impedance of a pad receiver circuit is fairly high under normal conditions since the

impedance looking into the base of the emitter follower input device as well as the

impedance looking into the reverse biased diodes is high. This does not cause any

serious problems when the pad is driven by a 50 Ω line, however, since the signals that

drive the pad receiver circuits are control signals that are essentially static under normal

testing conditions.

76

Figure 69 High frequency pad receiver schematics.

When high frequency signals needed to be interfaced to the chip the pad receiver

shown in Figure 68 is not sufficient. In order to match characteristic impedance of the

receiver a 50 Ω resistor is placed right after the ESD protection diodes between the pad

input and Vcc. A metal-insulator-metal (MIM) capacitor is added between the pad and

the one input of an ECL buffer to provide AC coupling. The value of the capacitor is

selected by frequency response plots available in the process technology model guides.

The voltage dividers in front of the ECL buffer inputs provide the offset and reference

voltages. The output of this ECL buffer is fed to another buffer for preserving signal

shape then sent to emitter followers to provide level 2 and level 3 outputs.

5.7 Pad driver design

The output pad driver shown in Figure 70, is used to drive single ended signal off chip to

a 50 Ω line. This design is similar to a differential output pad driver used in register file

test chips designed by Sam Steidl. The driver has a pair of emitter followers that drive an

emitter coupled pair. The collector of one the emitter-coupled pair devices is connected

to the pad. This allows current to either be drawn from the 50 Ω line to produce a low

output signal, or drawn from Vcc to produce a high output signal on the 50 Ω line. The

current source for the emitter-coupled pair draws 8 mA that produces a low voltage 0.4

77

V below Vcc, assuming the line is properly terminated. Since no current is flowing

through the 50 Ω line when the output is high, the nominal high voltage on the line is

Vcc. A diode is connected between Vcc and the output pad to provide a path for current

to flow in the event the output pad is not connected or not terminated properly. Use of a

diode allows the output impedance of the driver to remain high while the line is

terminated, since this device is reverse biased in this case. This is advantageous in that

the voltage swing on the output pad is larger than if a collector resistor is used. Although

a 50 Ω collector resistor would make the output of the impedance match the transmission

line impedance, it would cut the voltage swing at the output pad in half since the

effective impedance under steady state conditions is then 25 Ω. A similar diode is used

above the collector of the emitter coupled pair other side to maintain symmetry. Large

diodes are connected between Vcc and the pad, and between Vee and the output pad to

prevent damage to the driver devices due to electrostatic discharge.

Figure 70 Pad driver schematics.

78

5.8 7HP register file test chip overview

Figure 71 7HP test chip block diagram.

Pad Name Description

VCO Control Selects VCO frequency within the selected band.

Clock Select Selects between VCO and external clock.

External Clock Clock for shift operations. Can be used in test mode as well.

Output Select Selects signal that is driven off-chip for viewing.

Scope Output Produces an output signal to be viewed on an oscilloscope.

Counter Stop Stops the address and data counters.

Sync Out Produces a trigger signal for the oscilloscope.

Write Enable Enables synchronous write based on the selected clock.

Write Select Selects between external and synchronous write signals.

Table 15 List of 7HP register file test chip pads and their functions.

A block diagram of the 7HP test chip is shown in Figure 71. In order to simplify the test

chip design the scan mode and data shift in is omitted in this design. Removal of the

scan chain also removed the ability to control prevention of LFSR unstable all zero state

79

as described in LFSR section. A counter is used to generate bits that are written on the

register file. The replacement of LFSR with a counter is also simplified the layout.

During normal operation address counters supply register file columns with a repeating

patterns. The data counter output is fed to buffers to better drive the data inputs on the

register file. The counter stop input of the test chip provides a means to stop all the

counters to observe the outputs of the register file at that state. On chip VCOs frequency

is controlled by the VCO control input pad. There is also an external clock input pad to

supply the clock to the chip from external pattern generators. The clock that is used in

the test chip is selected by the clock select input pad, between the on chip VCO

generated clock or externally generated clock. The write enable signal fed to the circuit

is synchronized with the chip clock by write generator block, and this signal is fed to

data counter and write address counter. When the externally supplied write enable signal

is logically low, both data counter and write address counter is disabled, which in turn

disables the write operation on the register file. The on chip clock is divided by sixteen

in frequency by the frequency divider module to provide a trigger signal outputted from

the chip to view the chip outputs correctly on an oscilloscope. The register file read port

outputs, one address counter LSB output, write address counter LSB output along with

address collision match signal can be viewed on the scope output pad by switching the

the output select signals.

80

Figure 72 7HP test chip pad arrangements.

Power

Ground

Power

Ground

Ground

Power

Ground

Power

Unused

Signal

(Vcc!)

Unused

Signal

(Vcc!)

Figure 73 Revised 7HP test chip pad arrangement.

81

5.9 7HP register file test result

Figure 74 7HP test chip result.

Testing of the register file yielded approximately 13 GHz operation. Further frequency

changes were not possible due to pad receiver errors.

82

5.10 7HP test chip modifications

Figure 75 Resubmited 7HP register file test chip.

Another revision of 7HP register file test chip is submitted for fabrication on November

6th, 2006. Modifications include pad receiver corrections, additional pads for power and

modifications on on-chip VCO.

83

6. Future Work

6.1 8HP

A faster SiGe BiCMOS processing technology just became available. This process

features 0.12 µm devices that have an fT of 180 GHz. Even though these devices provide

faster devices and smaller devices, the device shape is changed minimally. The deep

trench isolation surrounding the HBTs has stayed the same. So overall there is virtually

no size advantage gained on the process. Along with this there is a design rule change

that affects the local density of the deep trench isolation layer on layouts. This rule

enforces a lower density of HBTs allowed per unit area of the layout. The affect can be

illustrated in the following figures.

Figure 76 Layout size comparison of memory cell in 7HP (left) and 8HP (right).

As Figure 76 shows the memory cell core layout size is increased from 32 µm by 13

µm in 7HP to 46 µm by 14 µm in 8HP in order to pass design rules.

84

Figure 77 Layout of 8 words of 16 bits array of memory cells in 7HP.

85

Figure 78 Layout of 8 words of 16 bits array of memory cells in 8HP.

The effects of the new deep trench isolation local density rule is seen more clearly

for the same size array of memory cells implemented in 7HP and 8HP, as shown in

Figure 78 and Figure 78. The size is grown from 270 µm by 210 µm in 7HP to 400 µm

by 300 µm in 8HP.

The benefits of faster process can be captured by possibly a smaller size design.

6.2 Power Saving

Even though CML/ECL circuits have speed advantages over other logic families, the

power consumption can cause problems to large scale circuits. The static power

consumption of these circuits dominates the total power consumption. Tree current can

be lowered in order to meet lower power consumption requirements. This power saving

in turn reduces the frequency of operation. With the help of a variable current source,

CML gates can be adjusted to operate in performance mode (high frequency, high

power) mode or power saving mode (lower frequency, lower power).

86

The power saving scheme implemented on High Speed SiGe Field Programmable

Gate Array19 can be used to reduce power consumption of CML circuits. This scheme,

shown in Figure 79, uses diodes and resistors that replace the pull-up resistors of

conventional CML circuits. The use of variable reference currents can maintain a

consistent voltage swing on the outputs. The number of available power supply voltages

determines the how many multi speed load modules can be used. The output voltage

swing should be kept at least 200 mV for the CML circuits to ensure a full switch of

current from one side of the tree to the other.

i10 i11

z10z11

Vcc-slow

Vee

Vcc-fast

Vref

Rfast Rfast

Rslow Rslow

Figure 79 CML buffer with power saving features.

Although the above mentioned power saving scheme can provide notable power savings,

it complicates the layout of the design significantly. It would require addition of multiple

power rails, diodes and extra resistors to a conventional CML layout.

87

6.3 3D integration

3D integration is a new technology that has promising leads to increase transistor density

while offering faster on chip communication. 3D integration stacks multiple die

connected with a very high density and low latency interface which provides increased

device density and the ability to place and route in the third dimension. Partitioning the

register file across multiple die reduces the lengths of many critical wires, which

provides both latency and energy benefits.

The performance of many high end microprocessors are increasingly limited not by

computation delay, but rather by communication delay. Although transistor size and

speed continue to improve, the relative speed of wires has not improved at the same rate.

High port count of physical register files found in modern superscalar processors worsen

the wire delay problem.

There are three possible organizations to stack dies. Dies can be oriented face to face,

face to back or back to back. In face to face organization, the vias are simply masked and

deposited on top of the top metal layer using conventional metal deposition techniques.

Therefore, the vias can be as dense as regular on die interconnects and the realizable

pitch is only limited by aligning the two die. If vias must be etched through the back side

of a die then the pitch will be less dense due to the need to etch through the backside

silicon. The physical characteristics of die-to-die vias determine the signal propagation

delay between the two die. The general approach of thinning of one of the dies reduces

the distance that die-to-die via must cross to connect the two die. Face to face vias do not

pass through the device layer and therefore do not impose any floorplanning and

placement constraints on the underlying devices.

Modern superscalar processors capable of issuing many instructions per cycle require a

large number of read and write ports from the register file, and the size of an memory

cell increases dramatically with increasing port requirements. The physical register file

is a critical component of modern processors in terms of impact on clock frequency and

instructions per second rates. As a result, many microarchitecture level proposals have

been made to deal with the size, latency and power of the physical register file, including

register caching and register file banking. While these techniques can reduce the average

88

latency of register file access they significantly complicate the processor data and

control paths.

A two die register partitioned 3D register file, shown in Figure 80, takes half of the

register file entries and places them on the second die. As a result, vertical distance along

bitlines are halved, which can greatly reduce the latency and power associated with

toggling of bitlines. The row decoder’s height is also halved, which reduces the length of

critical path associated with accessing the farthest entry in the register file. Overall

footprint of the register file has also been halved.

The bit partitioned register file, shown in Figure 81, can be viewed as the dual of register

partition organization: one folds the register file upon itself in horizontal direction while

other folds in the vertical direction. The bottom die stores the least significant bits of the

register file values and the top die stores the most significant bits. The bit partitioned

register file reduces the wire length and gate loading on the wordline, which provides

both latency and energy benefits. The bit partitioned 3D register file requires that the

row decoder outputs be fanned out to the different die. This extra communication incurs

a small overhead, but the latency reduction due to the halving of the wordline length still

provides a significant net benefit.

It has been reported20 that for a 128-entry, 2 die, 3D register file, the bit partitioning

approach provides the greatest latency reduction. The wordline is heavily loaded by the

two access transistors per column and so splitting the wordline across two die reduces a

major component of the wire latency.

When considering a 256 entry register file the height of the overall structure increases,

thus making the row decoder and bitline sense amplifier delay more critical. In this

situation the register partitioning approach provides greater benefit.

The register partitioning approach effectively halves the bitline length for each doubling

of the number of the stacked die. The shorter bitlines greatly reduces the loading of the

sense amplifier, which in turn may be sized smaller to consume even less energy.

89

Figure 80 Register partitioned 3D register file.20

Figure 81 Bit partitioned 3D register file.20

90

6.4 BiCMOS register file

CMOS logic circuits in this technology dissipate much less power than comparable ECL

and CML logic circuits. This is due to the fact that ECL and CML logic circuits dissipate

a large amount of static power since there is a steady state current flowing through these

circuits. CMOS circuits dissipate only a small amount of static power due to leakage

current that flows through the circuits when they are not switching. This leakage current

is due to the fact that CMOS devices tend to appear like reverse-biased diodes when cut

off. Most of the power dissipation in CMOS circuits is dynamic. That is, CMOS circuits

dissipate power mainly in charging and discharging load capacitance to switch logic

states. The dynamic power dissipation of the ECL and CML circuits designed using this

SiGe HBT BiCMOS technology are only a very small fraction of the static power

dissipation of these circuits. In fact, given ideal current sources, the average total power

dissipation of ECL and CML circuits should always equal the static power dissipation of

the circuits since all current must eventually flow through the current sources. An

investigation of a BiCMOS register file design was undertaken, therefore, to attempt to

find a way to lower the power dissipation of the register file.

A standard CMOS single-port static memory cell consists of two inverters that are cross-

coupled in such a manner that a high voltage (VDD) at the output of one of the inverters

produces a low voltage (VSS) at the output of the other inverter, which in turn maintains

the high voltage at the output of the first inverter. This positive feedback allows a value

to be stored in the cross-coupled inverter pair as long as power is applied or until the

voltages are forced to the opposite values through a write operation to the cell. A write

operation is performed by placing high and low voltages on the bit lines corresponding

to the value to be written, and then by bringing the word line voltage high. The pass

transistors with gates connected to the word line pull the voltage levels at the inputs of

the memory cell inverters to the voltages found on the corresponding bit lines. Note that

the width-to-length ratios of the devices in the memory cell inverters are sized such that

the value stored through the positive feedback can be overridden by the voltage levels on

the bit lines, when the bit line values are set to particular values. To perform a read

operation of the memory cell, the bit lines are placed in a high impedance state or

allowed to float to a high value using pull-up devices. Then, when the word line voltage

91

is brought high, the pass transistors allow the bit line voltages to be brought to the levels

of the memory cell inverter output voltages. The bit line voltages can then be read by a

sense amplifier to determine the value stored in the memory cell. Note that if pull-up

devices are used to set the bit line voltages before a read operation takes place, the width

to-length ratios of the pull-up devices must be small enough relative to the memory cell

devices to insure that the value stored in the memory cell is not lost due to fluctuations in

the memory cell voltages during the read operation.

For a BiCMOS register file with the same capabilities as the bipolar register file, a

memory cell is needed that can perform two read accesses and one write access

simultaneously. This type of memory cell can be created by simply adding two

additional pairs of pass transistors to the CMOS single-port static memory cell with

schematics shown in Figure 82. A CMOS memory cell with read ports using pass

transistors, however, is not directly compatible with the bipolar read address decoder

described in Chapter 3. One could use a CMOS read address decoder, but based on the

propagation delay data in Chapter 4, a CMOS read address decoder is likely to

significantly lengthen the read access time of the BiCMOS register file relative to the

bipolar register file. One could design an interface between the bipolar read address

decoder and the CMOS memory cell, but this would still require a CMOS word line

driver to properly control the pass transistors. This solution will have a significant

impact on the read access time, therefore, due to the slow propagation delay of the

CMOS word line driver and the propagation delay associated with passing the memory

cell voltages to the read bit lines. A better solution is to use a memory cell with read

ports that are directly compatible with the bipolar read address decoder described in

Chapter 3.

92

MPA

MRB

MC1MC0

VSS

MPB

MNA MNB

RAWRBWWW

RAB RABbRBB RBBbWBBb WBB

VDD

MRBbMRAbMRA

MWb MW

Figure 82 CMOS 3-port memory cell.

Figure 82 illustrates a CMOS memory cell with two read ports and one write port.

Additional circuits are required to translate the ECL signals from the address decoder to

levels which are compatible with CMOS word line drivers in order to replace bipolar

memory cells with CMOS counterparts. The CMOS three-port memory cell stores data

in the same manner as the CMOS single-port memory cell. In addition, a write operation

is performed in the same manner to store new data in the CMOS three-port memory cell

as the CMOS single-port memory cell, using MW and MWb as the pass transistors to

facilitate the write operation. To perform a read operation using read port A of the

CMOS three-port memory cell, the word line driver draws current through RAW. MRA

and MRAb act as a current switch, resulting in a portion of the current flowing through

RAW to be conducted through either MRA or MRAb, depending on whether MC or MCb

is at a higher potential, which in turn flows through either RAB or RABb. The value

stored in the memory cell is determined by a sense amplifier connected to RAB and

RABb, such as the bipolar sense amplifier described in Chapter 3, based on the current

flowing in these two bit lines. The value stored in the memory cell can be read

simultaneously through port B using similar methods.

The size of each PFET in the memory cell cross-coupled inverters was sized for the

minimum width given the length is twice the minimum allowed value. This allows a

one-to-one width-to-length ratio to be used for each PFET without violating the

minimum gate area constraint. The width-to-length ratio of each NFET in the cross-

coupled inverters was chosen to be the smallest possible ratio while still using the

minimum gate length and minimum gate area, resulting in a width-to-length ratio of

93

four-to-one for these devices. Therefore, given the difference in width-to-length ratios

between the PFETs and the NFETs, the cross-coupled inverters in the CMOS memory

cell are weak inverters in the sense that the drive strength of the NFETs is much greater

than the drive strength of the PFETs. This means that the inverter will be able to switch

from a high voltage to a low voltage much more quickly than it can switch from a low

voltage to a high voltage. This scenario is necessary in the case of a memory cell to

allow the output voltage levels of the cross-coupled inverters to be overridden by the

voltage levels passed through the pass transistors MW and MWb during a write operation.

This occurs much more easily if the memory cell node held at VDD by the undersized

PFET can be overpowered by an NFET pulling the corresponding write bit line to VSS ,

and hence, the memory cell node to VSS as well through the pass transistor. Using

devices in the cross-coupled inverters of the memory cell that have the minimum gate

area helps improve the write access time of the BiCMOS register file by minimizing the

parasitic capacitance that must be driven in order to switch the value of a memory cell.

Also, by sizing devices in the cross-coupled inverters of the memory cell such that the

devices have the minimum gate area, the size of the memory cells are made smaller,

which reduces wire parasitics on the bit lines and word lines since these wires can be

shorter if the memory cells are smaller.

To make write operations work correctly in the BiCMOS register file, a circuit is

required to translate the ECL logic voltage levels from the write address decoder to

CMOS voltage levels that the write word line drivers can handle. One solution, found in 21, 22,involves replacing a stage of the write address decoder with the version found in

the read address decoder utilizing a single-ended output. The output of this decoder stage

drives a PMOS style inverter, which in turn drives a CMOS inverter. The CMOS

inverter drives the write word line driver, which drives a feedback circuit to aid the

PMOS style inverter in its falling edge transitions as well as a word line. Therefore, two

additional gate delays are added to the write access propagation delay. Even with the

feedback to improve performance, each gate delay is likely to be at least 25 ps, given the

results shown in Chapter 4. Therefore, due to the translation circuit, the write access time

and the pipeline clock period will rise substantially beyond the higher values predicted

for the BiCMOS register file with the assumption that the write address decoder could

94

drive the write word line drivers directly. This makes the BiCMOS register file even less

attractive for pipelined systems in which the write access time is as critical as the read

access time17. For this reason, the bipolar register file was chosen over the BiCMOS

register file as a topic of research.

95

7. Conclusion

Pipelined Register File designs are completed using IBM’s 5DM and 7HP HBT

BiCMOS design technologies. These designs are fabricated and chips were received.

Further testing will be conducted on the fabricated chips.

Partially extracted simulations shows the 7HP design can operate with a clock of 16

GHz frequency. Fabricated test chip results show an operation in 13 GHz range.

Corrections made on the design and design is resubmitted for fabrication.

CPU core test chip testing resulted operation at 4.4 GHz range with on chip VCO.

Corrections made on the design of pad receiver to input high frequency clock signals and

design is submitted for fabrication.

96

8. Publications

• "Face to Face Wafer Bonding for 3D Chip Stack Fabrication to Shorten Wire Lengths", J.F.

McDonald, O. Erdogan, et al., Proceedings of the 17th International VLSI Multilevel Interconnection

Conference, VMIC 2000, June 2000.

• "3-D Integration Using Novel Wafer Bonding Techniques", J.-Q. Lu, J.F. McDonald, R.J. Gutmann,

O. Erdogan, et al., Proceedings of the Advanced Metallization Conference, AMC 2000, vol. 16, pp.

515-521, Oct. 2000.

• "IP Core-Based Design, High-Speed Processor Design and Multiplexing LAN Architectures Enabled

by 3D Wafer Bonding Technologies", J.-Q. Lu, O. Erdogan, J.F. McDonald, et al., CD of DesignCon

2001: Wireless and Optical Broadband Design Conference, paper #: WB-13, February 2001.

• "Design and Fabrication of Damascene Patterned Interconnections for Face-to-Face Wafer Bonded

3D-Stacked IC Test Structures", J.-Q. Lu, O. Erdogan, et al., Proceedings of the 18th International

VLSI Multilevel Interconnection Conference, VMIC 2001, Sept. 2001.

• "Three-dimensional (3D) ICs: A Technology platform for using dielectric bonding on 200 mm

wafers", J.-Q Lu, O. Erdogan, J.F. McDonald, et al., Materials Research Society Digest, 2002.

• "3D direct vertical interconnect microprocessors test vehicle", J. Mayega, Okan Erdogan, J. F.

McDonald, et al., Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, pp. 141-146,

April 2003.

• "Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D

Memory", J.-R. Guo, O. Erdogan, J. F. McDonald, et al., Proceedings of the 13th International

Conference on Field Programmable Logic and Applications, FPL 2003, pp. 125-135, Sep. 2003.

• "The Gigahertz FPGA: Design consideration and Applications", J.-R. Guo, O. Erdogan, J. F.

McDonald, et al., Proceedings of the ACM/SIGDA 12th International Symposium on Field

Programmable Gate Arrays, FPGA 2004, pp. 248, February 2004.

• "SiGe HBT Microprocessor Core Test Vehicle", P.M. Belemjian, O. Erdogan, R. P. Kraft, J. F.

McDonald, Proceeding of IEEE, Vol. 93 (#9), Sep. 2005, pp. 1669-1678.

• "Predicting the Performance of a 3D Processor - Memory Chip Stack", P. Jacob, O. Erdogan, et al,

IEEE Design and Test of Computers, Special issue on 3D integration, pp. 540-547, Nov-Dec 2005.

97

9. References

1 “Transistorized.” PBS Documentary, Item Code: A4082, Twin Cities Public Television, 1999. 2 M. Mitchell et al., “Characterization of NPN and PNP SiGe Heterojunction Bipolar Transistors formed

by Ge+ Implantation.”, IEEE 0-7803-5298-X, 1999. 3 J. D. Cressler, “On the Potential of SiGe HBTs for Extreme Environment Electronics”, Proceedings of

the IEEE, Vol. 93, No. 9, pp. 1559-1582, Sep 2005. 4 M. Shur, “Introduction to Electronic Devices”, John Wiley & Sons, 1996, ISBN 0-471-10348-9. 5 M. Friedrich, H.-M. Rein, “Analytical Current-Voltage Relations for Compact SiGe HBT Models — Part

I: The “Idealized” HBT”, IEEE Transactions on Electron Devices, Vol. 46, No. 7, pp. 1384-1393, July

1999. 6 M. Friedrich, H.-M. Rein, “Analytical Current-Voltage Relations for Compact SiGe HBT Models — Part

II: Application to Practical HBTs and Parameter Extraction.”, IEEE Transactions on Electron Devices,

Vol. 46, No. 7, pp. 1394-1401, July 1999. 7 G. Niu, et al., “Noise Modeling and SiGe Profile Design Tradeoffs for RF Applications [HBTs]”, IEEE

Transactions on Electron Devices, Vol. 47, No. 11, pp. 2037-2044, Nov 2000. 8 K. Aufinger, et. al., “High-frequency and noise characteristics of advanced Si and Si/SiGe bipolar

transistors”, EUROCOMM 2000. Information Systems for Enhanced Public Safety and Security.

IEEE/AFCEA, pp. 408-411, May 2000. 9 Mehmet Soyuer, et al., “Low-Power Multi-GHz and Multi-Gbps SiGe BiCMOS Circuits”, Proceedings

of the IEEE, Vol. 88, No. 10, pp. 1572-1582, Oct 2000. 10 A. Pascht, et. al., “Comparison of advanced transistor technologies with regard to their noise figures”,

High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO. 1999

Symposium, pp. 125 -130, Nov 1999. 11 J.M. Moniz., “Is SiGe the Future of GaAs for RF Applications?”, 19th Annual Gallium Arsenide

Integrated Circuit (GaAs IC) Symposuium Technical Digest, pp. 229-231, Oct. 1997. 12 H. Greub, J.F. McDonald, T. Yamaguchi, “High-Performance Standard Cell Library and Modeling

Technique for Differential Advanced Bipolar Current Tree Logic”, IEEE Journal of Solid-State Circuits,

Vol. 26, No. 5, pp. 749-762, May 1991. 13 B.S. Goda, “SiGe HBT BiCMOS Field Programmable Gate Arrays for Fast Reconfigurable

Computing”, Doctoral Thesis, Rensselaer Polytechnic Institute, Department of Electrical Engineering,

Apr 2001. 14 T.W. Krawczyk, “Circuits for the Design of a Serial Communication System Utilizing SiGe HBT

Technology”, Doctoral Thesis, Rensselaer Polytechnic Institute, Department of Electrical Engineering,

Nov 2000. 15 D.R. Greenberg, et. al., “HBT low-noise performance in a 0.18 um SiGe BiCMOS technology”, 2000

IEEE MTT-S International, Microwave Symposium Digest, Vol. 1, pp. 9 -12, Jun 2000.

98

16 J.D. Cressler, et. al., “The effects of proton irradiation on the lateral and vertical scaling of UHV/CVD

SiGe HBT BiCMOS technology”, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2515 -2520,

Dec 2000. 17 S.A. Steidl, “A 32-Word by 32-Bit Three-Port Bipolar Register File Implemented Using a SiGe HBT

BiCMOS Technology”, Doctoral Thesis, Rensselaer Polytechnic Institute, Department of Electrical

Engineering, May 2001. 18 Y. Leblebici, S.-M. Kang, “CMOS Digital Integrated Circuits: Analysis and Design”, WCB/ McGraw-

Hill, ISBN # 0-07-292508-8, p. 519, 1999 19 J.-R. Guo, “A High Speed Silicon Germanium Field Programmable Gate Array For Giga-Hertz

Applications”, Doctoral Thesis, Rensselaer Polytechnic Institute, Department of Electrical Engineering,

Dec 2005. 20 K. Puttaswamy, G. H. Loh, “Implementing Register Files for High-Performance Microprocessors in a

Die-Stacked (3D) Technology”, IEEE Proceedings off the Emerging VLSI Technologies and

Architectures (ISVLSI), Vol. 00, pp. 6, Mar 2006. 21 C.-C. Chao, B.A. Wooley, “A 1.3-ns 32-word by 32-bit three-port BiCMOS register file,” Proceedings

of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN,pp. 91-94, Oct 1994. 22 C.-C. Chao, B. A. Wooley, “A 1.3-ns 32-word x 32-bit three-port BiCMOS register file,” IEEE Journal

of Solid-State Circuits, Vol. 31, No. 6, pp. 758-766, Jun 1996.

99

Appendix A – Probe diagrams

16 pin probe

S S P S S P G PG S S GS S S S

P Power pad Vee!

S Signal pad G Ground PadVcc!

Low speed signal pins

High speed signal pins




16 pin probe

S SS S P S S P G PG S S GS S S SS S

P Power pad Vee!

S Signal pad G Ground PadVcc!






Figure A1 16 pin high frequency probe pad diagram.

10 pin probe

S S P G S GS P S S




Ground padVcc!

P Power pad Vee!

S Signal pad G

10 pin probe

S S P G S GS P S S




Ground padVcc!

P Power pad Vee!

S Signal pad G

Figure A2 10 pin high frequency probe pad diagram.

Ground padVcc!


P Power pad Vee!

S Signal pad G

10 pin power probe

S P G P G PG G P S


Ground padVcc!


P Power pad Vee!

S Signal pad G

10 pin power probe

S P G P G PG G P S


Figure A3 10 pin power probe pad diagram.

100

Appendix B – 3D mask set design

B1 - Pillar type via

The first type of via chain we constructed used the stacked via method. In this method

the metal pads on each chip are lined up so they are on top of one another. The bottom

layer is solid metal pad, whereas the upper layer has a whole cut out of the pad. A via is

then made through both chips that goes through the hole in the upper pad and ends on

the lower pad. This hole is then filled with metal, creating an electrical connection

between the two pads. There are several parameters that were varied, to determine what

would give us the best result. The first variable was the size of the via. We used 1, 2, 3

and 4u vias. The second variable is the size of the hole cut into the upper pad. Here there

were only two variations. The first was that the hole was cut to the exact size of the via.

The second was that it was 1u larger. The third variable was the size of the metal pads.

The dimension that was changed was the amount the pads would hang out from the hole

in the upper pad. These sizes were 0.5, 1 and 2 µm.

Test Pad

Metal From 2nd Wafer

Test Pad

Metal From 2nd Wafer

Figure B1 Three dimensional view of the pillar type vias.

B2 – Bridge type via

The second type of via chain was using the bridge type via. In this the two metal

pads are not lined up. Vias are made down to each pad and then filled with metal. These

101

are then connected on the top. There were two variables, via size and overhang size.

Like the pillar vias, the via size was varied between 1, 2, 3 and 4 µm. The overhang was

also varied between 0.5, 1 and 2 µm.

Metal From 1st Wafer

Via between wafers

Via Plug

Test Pad

Metal From 1st Wafer

Via between wafers

Via Plug

Test Pad

Figure B2 Three dimensional view of the bridge type vias.

B3 - Chain Structure

Both types of vias were put together into chains of various lengths. For the pillar

types the chain sizes are 1, 2, 4, 6, 12, 18, 24, 30, 36 and 42. These numbers indicated

the number of vias per chain. The last size, 42, is the maximum number of maximum

size vias that can be fit into the area between pads. The chain sizes for the bridge type

vias are 4, 8, 12, 24, 36 and 48. These numbers represent the number of vias in the chain.

However, the number of links is half that. This is because two vias are necessary to

create a link. The chains are lined up vertically and connect to the chains above and

below them. Each chain also has a connection to a pad that will go on the top of the

stack.

102

Landing Layer

Via Layer

Collet Layer

Opening Layer

Pad Layer

Via Chains

Test Pads

Landing Layer

Via Layer

Collet Layer

Opening Layer

Pad Layer

Via Chains

Test Pads

Figure B3 Chain Structure of the pillar type vias.

Landing Layer

Via Layer

Collet Layer

Opening Layer

Pad Layer

Test Pads

Via Chains

Landing Layer

Via Layer

Collet Layer

Opening Layer

Pad Layer

Test Pads

Via Chains

Figure B4 Structure of the bridge type vias.

103

B4 - Folding the wafers together

The design tools that we are using have no concept of a 3D-chip stack, so some

effort had to be made to draw things that would end up in 3D. As well, the need to keep

costs down made making only one mask set a desirable alternative. For the via chains all

of the metal that would reside on the bottom chip was drawn on one metal layer and that

for the top chip was drawn on another. Both metals were drawn where they would be

once the wafers were folded together. The top level of metal was then mirrored over a

vertical line of symmetry that would mark the center of the chip. This mirrored metal

was then changed to be on the same layer as the bottom layer of metal. This gives a

design that contains both the top and bottom layers of metal on the same wafer. When

two wafers are folded together the top and bottom metals line up and the vias can be

created. It should be noted that this is only using half of the reticle for each completed

stack. This is because the pillar scheme is not symmetric between the top and bottom

designs. The top layer of metal needs to have a hole in the middle of the pad, while the

bottom doesn't.

Test Pads

Via Chains

Test Pads

Via Chains

Figure B5 Test Structure of the pillar type vias

104

B5 - Testing

For each scheme of vias there is a 26x26 array of test pads. The via chains are

placed vertically between these pads. Each column of pads is connected through the via

chains located next to them. This arrangement of pads allows for two methods of testing.

The first is to test along a column of via chains. A signal can be fed in at the first pad

and then be read at each of the other pads. The second method involves the use of two

probes. Both probes are placed horizontally on the chip and a signal is sent from one to

the other.

B6 - Final Editing on the Design

1. 8 µm vias are added for both the plug and the bridge type.

2. Cross marks are added for each layer –namely Metal1, Via1, Via2, Metal3

layers- which have dimensions ranging from 0.2 µm to 1 µm (0.2 µm, 0.3 µm, 0.4 µm,

0.5 µm, 0.6 µm, 0.8 µm, 1 µm) on the right side of the landing pad array.

Plug Guide (metal w/opening)

Plug Type Via

Difference betweenOpening and Via

3 µm

2 µm

0.5 µm0.5 µm

Number of plugs betweenthe shown and the next pad

Test Pad

Plug typevia teststructure

2 µm

0.5 µm 0.5 µm (Constant)

Plug Landing (metal w/o opening)

Plug Guide (metal w/opening)

Plug Type Via

Difference betweenOpening and Via

3 µm

2 µm

0.5 µm0.5 µm

Number of plugs betweenthe shown and the next pad

Test Pad

Plug typevia teststructure

2 µm

0.5 µm 0.5 µm (Constant)

Plug Landing (metal w/o opening)

Figure B6 Pillar type via dimensions.

105

Deep ViaShallow Via

Bridge

Number of plugsbetween the shownand the next pad

Test Pad

Bridge typevia teststructure

3 µm

1 µm

2 µm2 µm

3 µm2 µm2 µm

Deep ViaShallow Via

Bridge

Number of plugsbetween the shownand the next pad

Test Pad

Bridge typevia teststructure

3 µm

1 µm

2 µm2 µm

3 µm2 µm2 µm

Figure B7 Bridge type via dimensions.

106

Appendix C – Design Netlist

// Library name: regfil7hpv4_7M

// Cell name: buf_fet_L1_2x

// View name: schematic

subckt buf_fet_L1_2x Vref i10 i11 z10 z11 inh_substrate

TN330 (net028 Vref Vee! inh_substrate) nfet25 l=320.0n w=5.2u nf=1 m=1 \

ad=2.42e-12 as=2.42e-12 pd=11.22u ps=11.22u nrd=0.0584 nrs=0.0584 \

gcon=1 rsx=50 nqsmod=0 dtemp=0

RN1 (Vcc! z11 inh_substrate) opppcres r=157.29 w=3.0u l=1.6u m=1 \

pbar=1 s=1 dtemp=0 rsx=50 bp=6



I1 (Vee! inh_substrate) subc l=800.0n w=800.0n dtemp=0

Q0 (z11 i10 net18 inh_substrate) npn mult=(1) enl=1.28u enw=200.0n \

nstripes=1 dtemp=0 sh=1 ii=1 bv=1 hb=0 rsx=50 rel=0 pbm1=420.0n \

pbm2=320.0n

Q1 (z10 i11 net18 inh_substrate) npn mult=(1) enl=1.28u enw=200.0n \


pbm2=320.0n

Q4 (net026 net026 net028 inh_substrate) npn mult=(1) enl=1.28u \

enw=200.0n nstripes=1 dtemp=0 sh=1 ii=1 bv=1 hb=0 rsx=50 rel=0 \

pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends buf_fet_L1_2x

// End of subcircuit definition.


// Cell name: ef_fet_L3_4x


subckt ef_fet_L3_4x Vref i10 i11 z30 z31 inh_substrate

TN331 (net038 Vref Vee! inh_substrate) nfet25 l=320.0n w=10.5u nf=1 \

m=1 ad=4.91e-12 as=4.91e-12 pd=21.82u ps=21.82u nrd=0.0287 \

nrs=0.0287 gcon=1 rsx=50 nqsmod=0 dtemp=0




107


Q0 (net036 net036 z30 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q1 (net039 net039 z31 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q2 (Vcc! i10 net036 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n

Q7 (z31 z31 net038 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n

ends ef_fet_L3_4x






I0 (Vref i10 i11 net14 net13 inh_substrate) buf_fet_L1_2x

I1 (Vref net14 net13 z30 z31 inh_substrate) ef_fet_L3_4x

ends buf_fet_L3_4x



// Cell name: buf_fet_L1_2x_L3in


subckt buf_fet_L1_2x_L3in Vref i30 i31 z10 z11 inh_substrate







108



Q0 (net037 i30 net18 inh_substrate) npn mult=(1) enl=1.28u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends buf_fet_L1_2x_L3in






I0 (Vref i30 i31 net14 net13 inh_substrate) buf_fet_L1_2x_L3in





// Cell name: mux2_fet_L1_L2in_1x


subckt mux2_fet_L1_L2in_1x Vref a20 a21 b20 b21 s30 s31 z10 z11 \

inh_substrate





109

RPPC0 (Vcc! z11 inh_substrate) opppcres r=318.59 w=3.0u l=3.46u m=1 \




Q0 (net069 a20 net040 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q15 (z11 z11 net069 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q4 (net040 s30 net039 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q7 (net057 b20 net046 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q6 (net054 b21 net046 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends mux2_fet_L1_L2in_1x



// Cell name: static_0p9V


subckt static_0p9V Vref_0p9 inh_substrate

110

Q1 (Vref_0p9 Vref_0p9 net8 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q0 (Vcc! Vcc! Vref_0p9 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

TN0 (net8 net8 Vee! inh_substrate) nfet l=180.0n w=1.94u nf=1 m=1 \




ends static_0p9V



// Cell name: Vref_0.6mA_CLB_backup


subckt _sub0 Vref inh_substrate

RPPC1 (Vcc! net4 inh_substrate) oprrpres r=1.99763K w=3.0u l=4.48u m=1 \

pbar=1 s=1 dtemp=0 rsx=50.0 bp=3

RRRP0 (net021 Vref inh_substrate) oprrpres r=2.09639K w=3.0u l=4.66u \

m=1 pbar=1 s=1 dtemp=0 rsx=50.0 bp=3

RPPC2 (net016 Vee! inh_substrate) opppcres r=200.51 w=4.0u l=2.62u m=1 \



Q2 (net4 net021 net016 inh_substrate) npn mult=(1) enl=5.0u enw=280.0n \


pbm2=320.0n

Q0 (Vcc! net4 Vref inh_substrate) npn mult=(1) enl=5.0u enw=280.0n \

nstripes=1 dtemp=0 sh=1 ii=1 bv=1 hb=1 rsx=50.0 rel=0 pbm1=420.0n \

pbm2=320.0n

ends _sub0



// Cell name: VCO_ctrl


subckt VCO_ctrl Vin o20 o21 inh_substrate

I8 (net036 inh_substrate) _sub0

RPPC16 (Vcc! Vin inh_substrate) oprrpres r=1.00281K w=2.0u l=2.04u m=1 \


RRRP1 (net074 net043 inh_substrate) oprrpres r=6.01247K w=2.0u l=8.04u \

111




RRRP3 (net041 Vee! inh_substrate) oprrpres r=6.01247K w=2.0u l=8.04u \


RRRP0 (Vcc! net074 inh_substrate) oprrpres r=2.40552K w=2.0u l=3.72u \





enw=280.0n nstripes=1 dtemp=0 sh=1 ii=1 bv=1 hb=1 rsx=50.0 rel=0 \

pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q19 (o20 net036 net088 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n

Q20 (o21 net036 net086 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q15 (Vcc! Vin net061 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

Q18 (Vcc! net66 o21 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q16 (Vcc! net074 net080 inh_substrate) npn mult=(1) enl=1.64u \


112

pbm1=420.0n pbm2=320.0n

RPPC13 (Vcc! net66 inh_substrate) opppcres r=900.4 w=2.0u l=6.14u m=1 \




RPPC14 (Vee! net092 inh_substrate) opppcres r=200.51 w=4.0u l=2.62u \








RPPC8 (Vee! net62 inh_substrate) opppcres r=200.51 w=4.0u l=2.62u m=1 \


RPPC11 (net70 net68 inh_substrate) opppcres r=550.83 w=2.0u l=3.64u \


RPPC3 (net32 net70 inh_substrate) opppcres r=550.83 w=2.0u l=3.64u m=1 \


ends VCO_ctrl



// Cell name: Vref_2mA_3.4V


subckt _sub1 Vref inh_substrate

RRRP0 (net017 Vref inh_substrate) oprrpres r=801.19 w=4.0u l=2.8u m=1 \


RN0 (Vcc! net011 inh_substrate) oprrpres r=735.82 w=4.0u l=2.64u m=1 \


RN1 (net5 Vee! inh_substrate) oprrpres r=199.63 w=15.0u l=2.7u m=1 \





pbm2=320.0n

Q0 (Vcc! net011 Vref inh_substrate) npn mult=(1) enl=7.0u enw=800.0n \


pbm2=320.0n

ends _sub1


113


// Cell name: diffleap_4u_v1_6GHz


subckt diffleap_4u_v1_6GHz Vref i20 i21 j20 j21 o20 o21 s30 s31 \

inh_substrate







Q10 (net70 Vref net62 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n

Q9 (net66 s31 net68 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

Q8 (net44 s30 net32 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

Q7 (o21 j20 net66 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

Q6 (o20 j21 net66 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

Q5 (o20 i21 net44 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

Q4 (o21 i20 net44 inh_substrate) npn mult=(1) enl=1.64u enw=200.0n \


pbm2=320.0n

RPPC13 (Vcc! o21 inh_substrate) opppcres r=426.67 w=1.6u l=2.12u m=1 \


RPPC12 (Vcc! o20 inh_substrate) opppcres r=426.67 w=1.6u l=2.12u m=1 \


RPPC8 (Vee! net62 inh_substrate) opppcres r=200.51 w=4.0u l=2.62u m=1 \




114

RPPC3 (net32 net70 inh_substrate) opppcres r=799.73 w=2.0u l=5.42u m=1 \


ends diffleap_4u_v1_6GHz



// Cell name: dualleap_4u_v2_6GHz


subckt dualleap_4u_v2_6GHz Vref s30 s31 w20 w21 x20 x21 y20 y21 z20 z21 \

inh_substrate

I60 (Vref y20 y21 x20 x21 z20 z21 s30 s31 inh_substrate) \

diffleap_4u_v1_6GHz

I59 (Vref x20 x21 w20 w21 y20 y21 s30 s31 inh_substrate) \

diffleap_4u_v1_6GHz

I58 (Vref w20 w21 z21 z20 x20 x21 s30 s31 inh_substrate) \

diffleap_4u_v1_6GHz

I43 (Vref z20 z21 y20 y21 w21 w20 s30 s31 inh_substrate) \

diffleap_4u_v1_6GHz

ends dualleap_4u_v2_6GHz



// Cell name: ef2


subckt ef2 i10 i11 vref z20 z21 inh_substrate

Q5 (net051 vref net041 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n

Q4 (z20 vref net043 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n

Q2 (z21 vref net039 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n

Q0 (net060 vref net037 inh_substrate) npn mult=(1) enl=2.0u enw=280.0n \


pbm2=320.0n


RRRP0 (net037 Vee! inh_substrate) opppcres r=401.08 w=4.0u l=5.54u m=1 \



115






RPPC8 (Vcc! net069 inh_substrate) opppcres r=1.00108K w=2.0u l=6.86u \




RPPC11 (Vcc! net058 inh_substrate) opppcres r=500.49 w=2.0u l=3.28u \


RPPC12 (Vcc! net055 inh_substrate) opppcres r=500.49 w=2.0u l=3.28u \


Q3 (Vcc! net063 z21 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q12 (net063 net058 net051 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q1 (Vcc! net069 z20 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q14 (net055 i11 net060 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends ef2



// Cell name: VCO_tcircuit_10.5GHz


subckt _sub2 _net0 w20 w21 x20 x21 y20 y21 z20 z21 inh_substrate

I37 (_net0 net045 net035 inh_substrate) VCO_ctrl



116



I0 (net044 net045 net035 net36 net35 net47 net48 net37 net38 net30 \

net29 inh_substrate) dualleap_4u_v2_6GHz

I13 (net37 net38 net048 y20 y21 inh_substrate) ef2

I15 (net36 net35 net0142 w20 w21 inh_substrate) ef2

I14 (net47 net48 net0142 x20 x21 inh_substrate) ef2

I16 (net30 net29 net048 z20 z21 inh_substrate) ef2


ends _sub2



// Cell name: and3_fet_L1_1x


subckt and3_fet_L1_1x Vref a10 a11 b20 b21 c30 c31 z10 z11 inh_substrate









Q0 (z10 a11 net040 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q4 (net040 b21 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n

Q6 (net18 c31 net042 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


117

pbm2=320.0n

Q5 (net043 c30 net042 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm2=320.0n

ends and3_fet_L1_1x















pbm2=320.0n



pbm2=320.0n

Q2 (Vcc! i10 z20 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends ef_fet_L2_4x


118













Q0 (net037 i20 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q1 (net034 i21 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n




// Cell name: ef_fet_L2to3_1x


subckt ef_fet_L2to3_1x Vref i20 i21 z30 z31 inh_substrate







119




pbm2=320.0n



pbm2=320.0n

Q2 (net032 i20 z30 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q3 (net035 i21 z31 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q7 (Vcc! Vcc! net035 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n

ends ef_fet_L2to3_1x



// Cell name: latch_fet_L1_1x


subckt latch_fet_L1_1x Vref c20 c21 d10 d11 z10 z11 inh_substrate









Q12 (z10 d11 net39 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n


120


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends latch_fet_L1_1x



// Cell name: mslatch_fet_L1_1x


subckt mslatch_fet_L1_1x Vref c20 c21 d10 d11 z10 z11 inh_substrate

I0 (Vref c21 c20 d10 d11 net20 net19 inh_substrate) latch_fet_L1_1x

I1 (Vref c20 c21 net20 net19 z10 z11 inh_substrate) latch_fet_L1_1x

ends mslatch_fet_L1_1x



// Cell name: xor2_fet_L1_1x


subckt xor2_fet_L1_1x Vref a10 a11 b20 b21 z10 z11 inh_substrate











pbm2=320.0n



pbm2=320.0n

121



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends xor2_fet_L1_1x



// Cell name: andxor3_fet_L1_1x


subckt andxor3_fet_L1_1x Vref a10 a11 a30 a31 x20 x21 z10 z11 \

inh_substrate











pbm2=320.0n



pbm2=320.0n

Q11 (z11 x20 net043 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n

Q10 (z10 x21 net043 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \

122


pbm2=320.0n

Q4 (net040 x21 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q3 (net055 x20 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q6 (net18 a31 net042 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n

ends andxor3_fet_L1_1x



// Cell name: counter_3bit


subckt counter_3bit clk20 clk21 q0B_L1 q0_L1 q1B_L1 q1_L1 q2B_L1 q2_L1 \

q0B_L2 q0_L2 q1B_L2 q1_L2 q2B_L2 q2_L2 inh_substrate

I5 (Vref q1_L1 q1B_L1 q1_L2 q1B_L2 inh_substrate) ef_fet_L2_4x



I15 (Vref q0_L2 q0B_L2 net059 net058 inh_substrate) buf_fet_L1_1x_L2in

I16 (Vref q0_L2 q0B_L2 net030 net029 inh_substrate) buf_fet_L1_1x_L2in

I9 (Vref q1_L2 q1B_L2 net5 net3 inh_substrate) ef_fet_L2to3_1x

I13 (Vref inh_substrate) static_0p9V

I0 (Vref clk20 clk21 q0B_L1 q0_L1 q0_L1 q0B_L1 inh_substrate) \

mslatch_fet_L1_1x

I3 (Vref clk20 clk21 net30 net29 q1_L1 q1B_L1 inh_substrate) \

mslatch_fet_L1_1x

I6 (Vref clk20 clk21 net13 net32 q2_L1 q2B_L1 inh_substrate) \

mslatch_fet_L1_1x

I4 (Vref net059 net058 q1_L2 q1B_L2 net30 net29 inh_substrate) \

xor2_fet_L1_1x

I7 (Vref net030 net029 net5 net3 q2_L2 q2B_L2 net13 net32 \

123

inh_substrate) andxor3_fet_L1_1x

ends counter_3bit



// Cell name: counter_3bit_data


subckt counter_3bit_data clk30 clk31 ctrstop_20 ctrstop_21 q020 q021 q120 \

q121 q220 q221 wren_20 wren_21 inh_substrate

I1 (Vref net16 net15 wren_20 wren_21 clk30 clk31 net30 net29 \

inh_substrate) and3_fet_L1_1x

I2 (Vref net30 net29 net22 net21 inh_substrate) ef_fet_L2_4x


I9 (Vref ctrstop_20 ctrstop_21 net16 net15 inh_substrate) \

buf_fet_L1_1x_L2in

I0 (net22 net21 net40 net39 net38 net37 net36 net35 q020 q021 q120 \

q121 q220 q221 inh_substrate) counter_3bit

ends counter_3bit_data



// Cell name: counter_3bit_address


subckt counter_3bit_address clk30 clk31 ctrstop_20 ctrstop_21 q020 q021 \

q120 q121 q220 q221 inh_substrate



pbm2=320.0n

I1 (Vref net16 Vcc! ctrstop_20 ctrstop_21 clk30 clk31 net30 net29 \


I2 (Vref net30 net29 net22 net21 inh_substrate) ef_fet_L2_4x


I0 (net22 net21 net40 net39 net38 net37 net36 net35 q020 q021 q120 \

q121 q220 q221 inh_substrate) counter_3bit

ends counter_3bit_address



// Cell name: mux4_fet_L1_1x


subckt mux4_fet_L1_1x Vref a10 a11 b10 b11 c10 c11 d10 d11 s20 s21 s30 s31 \

124

z10 z11 inh_substrate











pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q4 (net040 s20 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n

Q7 (z11 b10 net046 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



125

pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q23 (z11 c10 net065 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q22 (z10 c11 net065 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

ends mux4_fet_L1_1x



// Cell name: mux_outv2


subckt mux_outv2 a20 a21 b20 b21 c20 c21 d20 d21 s20 s21 s30 s31 z20 z21 \

inh_substrate



I4 (Vref a10 a11 b10 b11 c10 c11 d10 d11 s20 s21 s30 s31 net30 net29 \

inh_substrate) mux4_fet_L1_1x

I0 (Vref a20 a21 a10 a11 inh_substrate) buf_fet_L1_1x_L2in

I1 (Vref b20 b21 b10 b11 inh_substrate) buf_fet_L1_1x_L2in

I2 (Vref c20 c21 c10 c11 inh_substrate) buf_fet_L1_1x_L2in

I3 (Vref d20 d21 d10 d11 inh_substrate) buf_fet_L1_1x_L2in

ends mux_outv2



// Cell name: mux_out


subckt mux_out a20 a21 b20 b21 c20 c21 d20 d21 s20 s21 s30 s31 z30 z31 \

inh_substrate



I4 (Vref a10 a11 b10 b11 c10 c11 d10 d11 s20 s21 s30 s31 net30 net29 \

inh_substrate) mux4_fet_L1_1x

I0 (Vref a20 a21 a10 a11 inh_substrate) buf_fet_L1_1x_L2in

I1 (Vref b20 b21 b10 b11 inh_substrate) buf_fet_L1_1x_L2in

I2 (Vref c20 c21 c10 c11 inh_substrate) buf_fet_L1_1x_L2in

126

I3 (Vref d20 d21 d10 d11 inh_substrate) buf_fet_L1_1x_L2in

ends mux_out



// Cell name: mux2_fet_L1_1x


subckt mux2_fet_L1_1x Vref a10 a11 b10 b11 s20 s21 z10 z11 inh_substrate











pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends mux2_fet_L1_1x



127

// Cell name: decode3_wen_part


subckt decode3_wen_part Vref a20 a21 b20 b21 c20 c21 wren20 wren21 z10 z11 \

inh_substrate

I4 (Vref net30 net29 Vcc! net14 wren21 wren20 z10 z11 inh_substrate) \

mux2_fet_L1_1x

I1 (Vref c21 c20 net37 net36 inh_substrate) ef_fet_L2to3_1x

I2 (Vref a21 a20 net41 net40 inh_substrate) buf_fet_L1_1x_L2in

I0 (Vref net41 net40 b21 b20 net37 net36 net30 net29 inh_substrate) \

and3_fet_L1_1x



pbm2=320.0n

ends decode3_wen_part
















pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n


128


pbm1=420.0n pbm2=320.0n












// Cell name: decode3_wen


subckt decode3_wen i010 i011 i110 i111 i210 i211 wren20_in wren21_in z010 \

z011 z110 z111 z210 z211 z310 z311 z410 z411 z510 z511 z610 z611 \

z710 z711 inh_substrate




I0 (Vref ls_bit_20 ls_bit_21 mid_bit_20 mid_bit_21 ms_bit_20 ms_bit_21 \

wren_20 wren_21 z010 z011 inh_substrate) decode3_wen_part















I10 (Vref i210 i211 ms_bit_20 ms_bit_21 inh_substrate) \

buf_fet_L2_4x_L2in

129

I9 (Vref i110 i111 mid_bit_20 mid_bit_21 inh_substrate) \

buf_fet_L2_4x_L2in

I8 (Vref i010 i011 ls_bit_20 ls_bit_21 inh_substrate) \

buf_fet_L2_4x_L2in

I17 (Vref wren20_in wren21_in wren_20 wren_21 inh_substrate) \

buf_fet_L2_4x_L2in

ends decode3_wen



// Cell name: decode3_part


subckt decode3_part Vref a20 a21 b20 b21 c20 c21 z10 z11 inh_substrate

I1 (Vref c21 c20 net20 net18 inh_substrate) ef_fet_L2to3_1x

I2 (Vref a21 a20 net14 net13 inh_substrate) buf_fet_L1_1x_L2in

I0 (Vref net14 net13 b21 b20 net20 net18 z10 z11 inh_substrate) \

and3_fet_L1_1x

ends decode3_part



// Cell name: decode3


subckt decode3 i010 i011 i110 i111 i210 i211 z010 z011 z110 z111 z210 z211 \

z310 z311 z410 z411 z510 z511 z610 z611 z710 z711 inh_substrate





z010 z011 inh_substrate) decode3_part












130




I8 (Vref i010 i011 ls_bit_20 ls_bit_21 inh_substrate) \

buf_fet_L2_4x_L2in

I9 (Vref i110 i111 mid_bit_20 mid_bit_21 inh_substrate) \

buf_fet_L2_4x_L2in

I10 (Vref i210 i211 ms_bit_20 ms_bit_21 inh_substrate) \

buf_fet_L2_4x_L2in

ends decode3



// Cell name: latch_fet_L1in_L3clk_1x


subckt latch_fet_L1in_L3clk_1x Vref c30 c31 d10 d11 z10 z11 inh_substrate











pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



131

pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends latch_fet_L1in_L3clk_1x



// Cell name: latch_fet_L1in_L3clk_1x_ma


subckt latch_fet_L1in_L3clk_1x_ma Vref c30 c31 d10 d11 z10 z11 \

inh_substrate











pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

132



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends latch_fet_L1in_L3clk_1x_ma



// Cell name: address_mslatch


subckt address_mslatch Vref clk30 clk31 d10 d11 z30 z31 inh_substrate


I1 (Vref clk30 clk31 net20 net18 net13 net11 inh_substrate) \

latch_fet_L1in_L3clk_1x

I0 (Vref clk30 clk31 d10 d11 net20 net18 inh_substrate) \

latch_fet_L1in_L3clk_1x_ma

ends address_mslatch



// Cell name: address_mslatch_8


subckt address_mslatch_8 Vref clk30 clk31 d1_hi_0 d1_hi_1 d1_hi_2 d1_hi_3 \

d1_hi_4 d1_hi_5 d1_hi_6 d1_hi_7 d1_lo_0 d1_lo_1 d1_lo_2 d1_lo_3 \

d1_lo_4 d1_lo_5 d1_lo_6 d1_lo_7 z3_hi_0 z3_hi_1 z3_hi_2 z3_hi_3 \

z3_hi_4 z3_hi_5 z3_hi_6 z3_hi_7 z3_lo_0 z3_lo_1 z3_lo_2 z3_lo_3 \

z3_lo_4 z3_lo_5 z3_lo_6 z3_lo_7 inh_substrate

I0 (Vref clk30 clk31 d1_lo_0 d1_hi_0 z3_lo_0 z3_hi_0 inh_substrate) \

address_mslatch


address_mslatch


address_mslatch

133


address_mslatch


address_mslatch


address_mslatch


address_mslatch


address_mslatch

ends address_mslatch_8



// Cell name: xor2_fet_L2_1x_L2in


subckt xor2_fet_L2_1x_L2in Vref a20 a21 b30 b31 z20 z21 inh_substrate











pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n


134


pbm2=320.0n

Q13 (net049 net049 z21 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends xor2_fet_L2_1x_L2in



// Cell name: xor2_fet_L1_1x_L2in


subckt xor2_fet_L1_1x_L2in Vref a20 a21 b30 b31 z10 z11 inh_substrate











pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n

135



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends xor2_fet_L1_1x_L2in



// Cell name: compare3


subckt compare3 a020 a021 a120 a121 a220 a221 b020 b021 b120 b121 b220 \

b221 match10 match11 Vref inh_substrate

I1 (Vref a120 a121 net38 net37 z20 z21 inh_substrate) \

xor2_fet_L2_1x_L2in

I2 (Vref a220 a221 net33 net32 net47 net49 inh_substrate) \

xor2_fet_L2_1x_L2in


I3 (Vref net47 net49 z30 z31 inh_substrate) ef_fet_L2to3_1x

I6 (Vref b020 b021 net28 net27 inh_substrate) ef_fet_L2to3_1x



I0 (Vref a020 a021 net28 net27 z10 z11 inh_substrate) \

xor2_fet_L1_1x_L2in

I4 (Vref z11 z10 z21 z20 z31 z30 match10 match11 inh_substrate) \

and3_fet_L1_1x

ends compare3



// Cell name: match_mslatch


subckt match_mslatch Vref clk30 clk31 d10 d11 z20 z21 inh_substrate


136

I1 (Vref clk30 clk31 net20 net18 net13 net11 inh_substrate) \


I0 (Vref clk30 clk31 d10 d11 net20 net18 inh_substrate) \

latch_fet_L1in_L3clk_1x_ma

ends match_mslatch



// Cell name: address_cct_fix


subckt address_cct_fix ad_A_2hi_0 ad_A_2hi_1 ad_A_2hi_2 ad_A_2lo_0 \

ad_A_2lo_1 ad_A_2lo_2 ad_B_2hi_0 ad_B_2hi_1 ad_B_2hi_2 ad_B_2lo_0 \

ad_B_2lo_1 ad_B_2lo_2 ad_W_2hi_0 ad_W_2hi_1 ad_W_2hi_2 ad_W_2lo_0 \

ad_W_2lo_1 ad_W_2lo_2 clk30_adda clk30_addb clk30_addw \

clk30_matcha clk30_matchb clk31_adda clk31_addb clk31_addw \

clk31_matcha clk31_matchb match20A match20B match21A match21B \

reada3_0 reada3_1 reada3_2 reada3_3 reada3_4 reada3_5 reada3_6 \

reada3_7 readb3_0 readb3_1 readb3_2 readb3_3 readb3_4 readb3_5 \

readb3_6 readb3_7 wr_hi3_0 wr_hi3_1 wr_hi3_2 wr_hi3_3 wr_hi3_4 \

wr_hi3_5 wr_hi3_6 wr_hi3_7 wr_lo3_0 wr_lo3_1 wr_lo3_2 wr_lo3_3 \

wr_lo3_4 wr_lo3_5 wr_lo3_6 wr_lo3_7 wren20 wren21 inh_substrate

I4 (ad_W_2lo_0 ad_W_2hi_0 ad_W_2lo_1 ad_W_2hi_1 ad_W_2lo_2 ad_W_2hi_2 \

wren20 wren21 w1lo_0 w1hi_0 w1lo_1 w1hi_1 w1lo_2 w1hi_2 w1lo_3 \

w1hi_3 w1lo_4 w1hi_4 w1lo_5 w1hi_5 w1lo_6 w1hi_6 w1lo_7 w1hi_7 \

inh_substrate) decode3_wen

I0 (ad_A_2lo_0 ad_A_2hi_0 ad_A_2lo_1 ad_A_2hi_1 ad_A_2lo_2 ad_A_2hi_2 \

a1lo_0 a1hi_0 a1lo_1 a1hi_1 a1lo_2 a1hi_2 a1lo_3 a1hi_3 a1lo_4 \

a1hi_4 a1lo_5 a1hi_5 a1lo_6 a1hi_6 a1lo_7 a1hi_7 inh_substrate) \

decode3

I2 (ad_B_2lo_0 ad_B_2hi_0 ad_B_2lo_1 ad_B_2hi_1 ad_B_2lo_2 ad_B_2hi_2 \

b1lo_0 b1hi_0 b1lo_1 b1hi_1 b1lo_2 b1hi_2 b1lo_3 b1hi_3 b1lo_4 \

b1hi_4 b1lo_5 b1hi_5 b1lo_6 b1hi_6 b1lo_7 b1hi_7 inh_substrate) \

decode3

I1 (net90 clk30_adda clk31_adda a1hi_0 a1hi_1 a1hi_2 a1hi_3 a1hi_4 \

a1hi_5 a1hi_6 a1hi_7 a1lo_0 a1lo_1 a1lo_2 a1lo_3 a1lo_4 a1lo_5 \

a1lo_6 a1lo_7 reada3_0 reada3_1 reada3_2 reada3_3 reada3_4 \

reada3_5 reada3_6 reada3_7 net88_0 net88_1 net88_2 net88_3 net88_4 \

net88_5 net88_6 net88_7 inh_substrate) address_mslatch_8

I3 (net83 clk30_addb clk31_addb b1hi_0 b1hi_1 b1hi_2 b1hi_3 b1hi_4 \

b1hi_5 b1hi_6 b1hi_7 b1lo_0 b1lo_1 b1lo_2 b1lo_3 b1lo_4 b1lo_5 \

b1lo_6 b1lo_7 readb3_0 readb3_1 readb3_2 readb3_3 readb3_4 \

137

readb3_5 readb3_6 readb3_7 net81_0 net81_1 net81_2 net81_3 net81_4 \

net81_5 net81_6 net81_7 inh_substrate) address_mslatch_8

I5 (net76 clk30_addw clk31_addw w1hi_0 w1hi_1 w1hi_2 w1hi_3 w1hi_4 \

w1hi_5 w1hi_6 w1hi_7 w1lo_0 w1lo_1 w1lo_2 w1lo_3 w1lo_4 w1lo_5 \

w1lo_6 w1lo_7 wr_hi3_0 wr_hi3_1 wr_hi3_2 wr_hi3_3 wr_hi3_4 \

wr_hi3_5 wr_hi3_6 wr_hi3_7 wr_lo3_0 wr_lo3_1 wr_lo3_2 wr_lo3_3 \

wr_lo3_4 wr_lo3_5 wr_lo3_6 wr_lo3_7 inh_substrate) \

address_mslatch_8

I6 (ad_B_2lo_0 ad_B_2hi_0 ad_B_2lo_1 ad_B_2hi_1 ad_B_2lo_2 ad_B_2hi_2 \

ad_B_2hi_0 ad_B_2lo_0 ad_B_2hi_1 ad_B_2lo_1 ad_B_2hi_2 ad_B_2lo_2 \

net45 net44 net061 inh_substrate) compare3

I7 (ad_A_2lo_0 ad_A_2hi_0 ad_A_2lo_1 ad_A_2hi_1 ad_A_2lo_2 ad_A_2hi_2 \

ad_A_2hi_0 ad_A_2lo_0 ad_A_2hi_1 ad_A_2lo_1 ad_A_2hi_2 ad_A_2lo_2 \

net12 net30 net046 inh_substrate) compare3

I8 (net046 clk30_matcha clk31_matcha net12 net30 match20A match21A \

inh_substrate) match_mslatch

I9 (net061 clk30_matchb clk31_matchb net45 net44 match20B match21B \

inh_substrate) match_mslatch

I10 (net90 inh_substrate) static_0p9V



ends address_cct_fix















pbm2=320.0n



pbm2=320.0n

138

Q2 (Vcc! i10 z20 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q3 (Vcc! i11 z21 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends ef_fet_L2_1x



// Cell name: ef_fet_L2_1x_16


subckt ef_fet_L2_1x_16 i1_hi_15 i1_hi_14 i1_hi_13 i1_hi_12 i1_hi_11 \

i1_hi_10 i1_hi_9 i1_hi_8 i1_hi_7 i1_hi_6 i1_hi_5 i1_hi_4 i1_hi_3 \

i1_hi_2 i1_hi_1 i1_hi_0 i1_lo_15 i1_lo_14 i1_lo_13 i1_lo_12 \

i1_lo_11 i1_lo_10 i1_lo_9 i1_lo_8 i1_lo_7 i1_lo_6 i1_lo_5 i1_lo_4 \

i1_lo_3 i1_lo_2 i1_lo_1 i1_lo_0 z2_hi_15 z2_hi_14 z2_hi_13 \

z2_hi_12 z2_hi_11 z2_hi_10 z2_hi_9 z2_hi_8 z2_hi_7 z2_hi_6 z2_hi_5 \

z2_hi_4 z2_hi_3 z2_hi_2 z2_hi_1 z2_hi_0 z2_lo_15 z2_lo_14 z2_lo_13 \

z2_lo_12 z2_lo_11 z2_lo_10 z2_lo_9 z2_lo_8 z2_lo_7 z2_lo_6 z2_lo_5 \

z2_lo_4 z2_lo_3 z2_lo_2 z2_lo_1 z2_lo_0 inh_substrate


I0 (Vref i1_lo_15 i1_hi_15 z2_lo_15 z2_hi_15 inh_substrate) \

ef_fet_L2_1x


ef_fet_L2_1x


ef_fet_L2_1x


ef_fet_L2_1x


ef_fet_L2_1x


ef_fet_L2_1x

I6 (Vref i1_lo_9 i1_hi_9 z2_lo_9 z2_hi_9 inh_substrate) ef_fet_L2_1x

139










ends ef_fet_L2_1x_16



// Cell name: vref_0p2mA_2x


subckt vref_0p2mA_2x vref_0p6mA inh_substrate




m=1 pbar=1 s=1 dtemp=0 rsx=50 bp=6


Q0 (Vcc! net018 vref_0p6mA inh_substrate) npn mult=(1) enl=1.28u \


pbm1=420.0n pbm2=320.0n

Q1 (net018 vref_0p6mA net7 inh_substrate) npn mult=(1) enl=1.28u \


pbm1=420.0n pbm2=320.0n



pbm2=320.0n

ends vref_0p2mA_2x



// Cell name: sense_amp


subckt sense_amp Vref rbit0 rbit1 sa0 sa1 inh_substrate





140


RPPC2 (Vcc! sa1 inh_substrate) opppcres r=799.03 w=3.0u l=9.0u m=1 \


RPPC3 (Vcc! sa0 inh_substrate) opppcres r=799.03 w=3.0u l=9.0u m=1 \


RPPC4 (net11 Vee! inh_substrate) opppcres r=1.59861K w=3.0u l=18.22u \


RPPC5 (net7 Vee! inh_substrate) opppcres r=1.59861K w=3.0u l=18.22u \


Q4 (rbit0 Vref net11 inh_substrate) npn mult=(1) enl=640.0n enw=280.0n \


pbm2=320.0n

Q5 (rbit1 Vref net7 inh_substrate) npn mult=(1) enl=640.0n enw=280.0n \


pbm2=320.0n

Q0 (sa1 net35 rbit0 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q1 (net35 net35 rbit1 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q2 (net32 net32 rbit0 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q3 (sa0 net32 rbit1 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

ends sense_amp



// Cell name: latch_out_fet_L1_1x


subckt latch_out_fet_L1_1x Vref c30 c31 d20 d21 z10 z11 inh_substrate








141


Q0 (net057 d21 net19 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q1 (net054 d20 net19 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n

ends latch_out_fet_L1_1x



// Cell name: mux2_fet_latched_L2_1x


subckt mux2_fet_latched_L2_1x Vref a10 a11 b10 b11 c30 c31 s20 s21 z20 z21 \

inh_substrate






142













pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

Q8 (net050 c30 net055 inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n



pbm2=320.0n


143


pbm1=420.0n pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

Q2 (Vcc! z10 z20 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q25 (Vcc! z11 z21 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends mux2_fet_latched_L2_1x



// Cell name: sec_pipe_portb


subckt sec_pipe_portb Vref_buf Vref_latch Vref_muxlatch Vref_sens \

bitlineb_0 bitlineb_1 bportout10 bportout11 clk30_latch \

clk30_muxlatch clk31_latch clk31_muxlatch match_20 match_21 \

wrtbitline20 wrtbitline21 inh_substrate

I2 (Vref_sens bitlineb_0 bitlineb_1 net34 net33 inh_substrate) \

sense_amp

I3 (Vref_buf wrtbitline20 wrtbitline21 net29 net28 inh_substrate) \

buf_fet_L1_1x_L2in

I0 (Vref_latch clk30_latch clk31_latch net16 net15 bportout10 \

bportout11 inh_substrate) latch_out_fet_L1_1x

I1 (Vref_muxlatch net29 net28 net34 net33 clk31_muxlatch \

clk30_muxlatch match_20 match_21 net16 net15 inh_substrate) \

mux2_fet_latched_L2_1x

ends sec_pipe_portb


144


// Cell name: sec_pipe_portb_16


subckt sec_pipe_portb_16 bitlineb_hi_0 bitlineb_hi_1 bitlineb_hi_2 \

bitlineb_hi_3 bitlineb_hi_4 bitlineb_hi_5 bitlineb_hi_6 \



bitlineb_hi_15 bitlineb_lo_0 bitlineb_lo_1 bitlineb_lo_2 \

bitlineb_lo_3 bitlineb_lo_4 bitlineb_lo_5 bitlineb_lo_6 \



bitlineb_lo_15 bportout1_hi_0 bportout1_hi_1 bportout1_hi_2 \

bportout1_hi_3 bportout1_hi_4 bportout1_hi_5 bportout1_hi_6 \



bportout1_hi_15 bportout1_lo_0 bportout1_lo_1 bportout1_lo_2 \

bportout1_lo_3 bportout1_lo_4 bportout1_lo_5 bportout1_lo_6 \



bportout1_lo_15 clk30 clk31 sel20 sel21 wrtbitline2_hi_0 \

wrtbitline2_hi_1 wrtbitline2_hi_2 wrtbitline2_hi_3 \





wrtbitline2_lo_0 wrtbitline2_lo_1 wrtbitline2_lo_2 \





wrtbitline2_lo_15 inh_substrate

I32 (Vref_latch net23 net21 clk30_latch clk31_latch inh_substrate) \

buf_fet_L3_4x_L3in

I31 (Vref_latch clk30 clk31 net23 net21 inh_substrate) \

buf_fet_L3_4x_L3in

I33 (Vref_muxlatch net23 net21 clk30_muxlatch clk31_muxlatch \

inh_substrate) buf_fet_L3_4x_L3in

I35 (Vref_buf sel20 sel21 match20 match21 inh_substrate) \

buf_fet_L2_4x_L2in

I37 (Vref_buf inh_substrate) static_0p9V

145

I34 (Vref_muxlatch inh_substrate) static_0p9V

I36 (Vref_latch inh_substrate) static_0p9V

I25 (Vref_sens inh_substrate) vref_0p2mA_2x

I0 (Vref_buf Vref_latch Vref_muxlatch Vref_sens bitlineb_lo_0 \

bitlineb_hi_0 bportout1_lo_0 bportout1_hi_0 clk30_latch \

clk30_muxlatch clk31_latch clk31_muxlatch match20 match21 \

wrtbitline2_lo_0 wrtbitline2_hi_0 inh_substrate) sec_pipe_portb



































146



























ends sec_pipe_portb_16



// Cell name: bportcomplete


subckt bportcomplete bitlineb_hi_0 bitlineb_hi_1 bitlineb_hi_2 \




bitlineb_hi_15 bitlineb_lo_0 bitlineb_lo_1 bitlineb_lo_2 \




bitlineb_lo_15 bportout2_hi_0 bportout2_hi_1 bportout2_hi_2 \

147








bportout2_lo_15 clk30 clk31 sel20 sel21 wrtbitline2_hi_0 \












I1 (out1_hi_0 out1_hi_1 out1_hi_2 out1_hi_3 out1_hi_4 out1_hi_5 \

out1_hi_6 out1_hi_7 out1_hi_8 out1_hi_9 out1_hi_10 out1_hi_11 \

out1_hi_12 out1_hi_13 out1_hi_14 out1_hi_15 out1_lo_0 out1_lo_1 \

out1_lo_2 out1_lo_3 out1_lo_4 out1_lo_5 out1_lo_6 out1_lo_7 \


out1_lo_14 out1_lo_15 bportout2_hi_0 bportout2_hi_1 bportout2_hi_2 \








bportout2_lo_15 inh_substrate) ef_fet_L2_1x_16

I0 (bitlineb_hi_0 bitlineb_hi_1 bitlineb_hi_2 bitlineb_hi_3 \








148






out1_lo_14 out1_lo_15 clk30 clk31 sel20 sel21 wrtbitline2_hi_0 \











wrtbitline2_lo_15 inh_substrate) sec_pipe_portb_16

ends bportcomplete



// Cell name: memcell


subckt memcell rbita0 rbita1 rbitb0 rbitb1 rworda rwordb tword wbit0 wbit1 \

wword0 wword1 inh_substrate

RPPC0 (tword mc0 inh_substrate) opppcres r=465.32 w=2.0u l=3.32u m=1 \


RPPC1 (tword mc1 inh_substrate) opppcres r=465.32 w=2.0u l=3.32u m=1 \


Q1 (mc1 wbit0 wword1 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q0 (mc0 wbit1 wword1 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q2 (mc0 mc1 wword0 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q3 (mc1 mc0 wword0 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

149

Q4 (rbitb1 mc1 rwordb inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q5 (rbitb0 mc0 rwordb inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q6 (rbita0 mc0 rworda inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

Q7 (rbita1 mc1 rworda inh_substrate) npn mult=(1) enl=640.0n \


pbm1=420.0n pbm2=320.0n

ends memcell



// Cell name: memcell_1word16bit


subckt memcell_1word16bit rbita_hi_15 rbita_hi_14 rbita_hi_13 rbita_hi_12 \

rbita_hi_11 rbita_hi_10 rbita_hi_9 rbita_hi_8 rbita_hi_7 \

rbita_hi_6 rbita_hi_5 rbita_hi_4 rbita_hi_3 rbita_hi_2 rbita_hi_1 \

rbita_hi_0 rbita_lo_15 rbita_lo_14 rbita_lo_13 rbita_lo_12 \

rbita_lo_11 rbita_lo_10 rbita_lo_9 rbita_lo_8 rbita_lo_7 \

rbita_lo_6 rbita_lo_5 rbita_lo_4 rbita_lo_3 rbita_lo_2 rbita_lo_1 \

rbita_lo_0 rbitb_hi_15 rbitb_hi_14 rbitb_hi_13 rbitb_hi_12 \

rbitb_hi_11 rbitb_hi_10 rbitb_hi_9 rbitb_hi_8 rbitb_hi_7 \

rbitb_hi_6 rbitb_hi_5 rbitb_hi_4 rbitb_hi_3 rbitb_hi_2 rbitb_hi_1 \

rbitb_hi_0 rbitb_lo_15 rbitb_lo_14 rbitb_lo_13 rbitb_lo_12 \

rbitb_lo_11 rbitb_lo_10 rbitb_lo_9 rbitb_lo_8 rbitb_lo_7 \

rbitb_lo_6 rbitb_lo_5 rbitb_lo_4 rbitb_lo_3 rbitb_lo_2 rbitb_lo_1 \

rbitb_lo_0 rworda rwordb tword wbit_hi_15 wbit_hi_14 wbit_hi_13 \

wbit_hi_12 wbit_hi_11 wbit_hi_10 wbit_hi_9 wbit_hi_8 wbit_hi_7 \


wbit_hi_0 wbit_lo_15 wbit_lo_14 wbit_lo_13 wbit_lo_12 wbit_lo_11 \

wbit_lo_10 wbit_lo_9 wbit_lo_8 wbit_lo_7 wbit_lo_6 wbit_lo_5 \

wbit_lo_4 wbit_lo_3 wbit_lo_2 wbit_lo_1 wbit_lo_0 wword0 wword1 \

inh_substrate

I0 (rbita_lo_15 rbita_hi_15 rbitb_lo_15 rbitb_hi_15 rworda rwordb \

tword wbit_lo_15 wbit_hi_15 wword0 wword1 inh_substrate) memcell



150









I6 (rbita_lo_9 rbita_hi_9 rbitb_lo_9 rbitb_hi_9 rworda rwordb tword \

wbit_lo_9 wbit_hi_9 wword0 wword1 inh_substrate) memcell



















I30 (Vee! inh_substrate) subc l=1.0u w=24.0u dtemp=0













151



ends memcell_1word16bit



// Cell name: memcell_8word16bit


subckt memcell_8word16bit rbita_hi_0 rbita_hi_1 rbita_hi_2 rbita_hi_3 \



rbita_hi_15 rbita_lo_0 rbita_lo_1 rbita_lo_2 rbita_lo_3 rbita_lo_4 \









rworda_0 rworda_1 rworda_2 rworda_3 rworda_4 rworda_5 rworda_6 \

rworda_7 rwordb_0 rwordb_1 rwordb_2 rwordb_3 rwordb_4 rwordb_5 \

rwordb_6 rwordb_7 tword_0 tword_1 tword_2 tword_3 tword_4 tword_5 \

tword_6 tword_7 wbit_hi_0 wbit_hi_1 wbit_hi_2 wbit_hi_3 wbit_hi_4 \


wbit_hi_11 wbit_hi_12 wbit_hi_13 wbit_hi_14 wbit_hi_15 wbit_lo_0 \



wbit_lo_13 wbit_lo_14 wbit_lo_15 wword_hi_0 wword_hi_1 wword_hi_2 \

wword_hi_3 wword_hi_4 wword_hi_5 wword_hi_6 wword_hi_7 wword_lo_0 \

wword_lo_1 wword_lo_2 wword_lo_3 wword_lo_4 wword_lo_5 wword_lo_6 \

wword_lo_7 inh_substrate

I0 (rbita_hi_15 rbita_hi_14 rbita_hi_13 rbita_hi_12 rbita_hi_11 \


rbita_hi_4 rbita_hi_3 rbita_hi_2 rbita_hi_1 rbita_hi_0 rbita_lo_15 \



rbita_lo_3 rbita_lo_2 rbita_lo_1 rbita_lo_0 rbitb_hi_15 \



rbitb_hi_3 rbitb_hi_2 rbitb_hi_1 rbitb_hi_0 rbitb_lo_15 \

152



rbitb_lo_3 rbitb_lo_2 rbitb_lo_1 rbitb_lo_0 rworda_0 rwordb_0 \

tword_0 wbit_hi_15 wbit_hi_14 wbit_hi_13 wbit_hi_12 wbit_hi_11 \





wbit_lo_2 wbit_lo_1 wbit_lo_0 wword_lo_0 wword_hi_0 inh_substrate) \

memcell_1word16bit



















memcell_1word16bit













153







memcell_1word16bit



















memcell_1word16bit
















154




memcell_1word16bit



















memcell_1word16bit



















155

memcell_1word16bit



















memcell_1word16bit

ends memcell_8word16bit



// Cell name: vref_0p6mA_2x


subckt vref_0p6mA_2x vref_0p6mA inh_substrate






Q0 (Vcc! net9 vref_0p6mA inh_substrate) npn mult=(1) enl=1.28u \


pbm1=420.0n pbm2=320.0n

Q1 (net9 vref_0p6mA net7 inh_substrate) npn mult=(1) enl=1.28u \


pbm1=420.0n pbm2=320.0n

ends vref_0p6mA_2x


156


// Cell name: worddrv_word_16bit


subckt worddrv_word_16bit Vref in3a in3b irefa irefb iworda iwordb wr30 \

wr31 wword0 wword1 inh_substrate




Q0 (iworda in3a irefa inh_substrate) npn mult=(1) enl=10.24u \


pbm1=420.0n pbm2=320.0n

Q1 (iwordb in3b irefb inh_substrate) npn mult=(1) enl=10.24u \


pbm1=420.0n pbm2=320.0n

Q2 (wword1 wr31 net23 inh_substrate) npn mult=(1) enl=10.24u \


pbm1=420.0n pbm2=320.0n

Q3 (wword0 wr30 net23 inh_substrate) npn mult=(1) enl=10.24u \


pbm1=420.0n pbm2=320.0n

Q4 (net23 Vref net13 inh_substrate) npn mult=(1) enl=10.24u enw=200.0n \


pbm2=320.0n

ends worddrv_word_16bit



// Cell name: worddrv_8word_16bit


subckt worddrv_8word_16bit iworda_0 iworda_1 iworda_2 iworda_3 iworda_4 \

iworda_5 iworda_6 iworda_7 iwordb_0 iwordb_1 iwordb_2 iwordb_3 \

iwordb_4 iwordb_5 iwordb_6 iwordb_7 reada3_0 reada3_1 reada3_2 \

reada3_3 reada3_4 reada3_5 reada3_6 reada3_7 readb3_0 readb3_1 \

readb3_2 readb3_3 readb3_4 readb3_5 readb3_6 readb3_7 wr_hi3_0 \

wr_hi3_1 wr_hi3_2 wr_hi3_3 wr_hi3_4 wr_hi3_5 wr_hi3_6 wr_hi3_7 \

wr_lo3_0 wr_lo3_1 wr_lo3_2 wr_lo3_3 wr_lo3_4 wr_lo3_5 wr_lo3_6 \

wr_lo3_7 wword_hi_0 wword_hi_1 wword_hi_2 wword_hi_3 wword_hi_4 \

wword_hi_5 wword_hi_6 wword_hi_7 wword_lo_0 wword_lo_1 wword_lo_2 \

wword_lo_3 wword_lo_4 wword_lo_5 wword_lo_6 wword_lo_7 \

inh_substrate

I15 (Vref inh_substrate) vref_0p6mA_2x

157

I12 (Vrefb inh_substrate) vref_0p6mA_2x

I9 (Vrefa inh_substrate) vref_0p6mA_2x

I0 (Vref reada3_0 readb3_0 irefa irefb iworda_0 iwordb_0 wr_lo3_0 \

wr_hi3_0 wword_lo_0 wword_hi_0 inh_substrate) worddrv_word_16bit















I8 (Vee! inh_substrate) subc l=800.0n w=16.0u dtemp=0

I18 (Vee! inh_substrate) subc l=800.0n w=16.0u dtemp=0

RPPC1 (net0163 Vee! inh_substrate) opppcres r=31.79 w=16.0u l=1.78u \


RPPC0 (net0165 Vee! inh_substrate) opppcres r=31.79 w=16.0u l=1.78u \


Q0 (irefb Vrefb net0165 inh_substrate) npn mult=(1) enl=10.24u \


pbm1=420.0n pbm2=320.0n

Q1 (irefa Vrefa net0163 inh_substrate) npn mult=(1) enl=10.24u \


pbm1=420.0n pbm2=320.0n

ends worddrv_8word_16bit



// Cell name: tword_16bit


subckt tword_16bit tword inh_substrate

Q1 (Vcc! Vcc! tword inh_substrate) npn mult=(1) enl=10.24u enw=200.0n \


pbm2=320.0n

ends tword_16bit

158



// Cell name: tword_8word16bit


subckt tword_8word16bit tword_0 tword_1 tword_2 tword_3 tword_4 tword_5 \

tword_6 tword_7 inh_substrate

I0 (tword_0 inh_substrate) tword_16bit








ends tword_8word16bit















pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

159



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends ef_fet_L2_2x











// Cell name: sec_pipe_porta


subckt sec_pipe_porta Vref_buf Vref_latch Vref_muxlatch Vref_sens \

Vref_worddrv aportout10 aportout11 bitlinea_0 bitlinea_1 \

clk30_latch clk30_muxlatch clk31_latch clk31_muxlatch match20 \

match21 wrtbit20 wrtbit21 wrtbitline20 wrtbitline21 inh_substrate

I2 (Vref_sens bitlinea_0 bitlinea_1 net51 net50 inh_substrate) \

sense_amp

I4 (Vref_latch clk30_latch clk31_latch net37 net33 aportout10 \

aportout11 inh_substrate) latch_out_fet_L1_1x

I3 (Vref_muxlatch net40 net39 net51 net50 clk31_muxlatch \

clk30_muxlatch match20 match21 net37 net33 inh_substrate) \

mux2_fet_latched_L2_1x

I1 (Vref_buf wrtbitline20 wrtbitline21 net40 net39 inh_substrate) \

buf_fet_L1_1x_L2in

I0 (Vref_worddrv wrtbit20 wrtbit21 wrtbitline20 wrtbitline21 \


ends sec_pipe_porta



// Cell name: sec_pipe_porta_16

160


subckt sec_pipe_porta_16 aportout1_hi_0 aportout1_hi_1 aportout1_hi_2 \

aportout1_hi_3 aportout1_hi_4 aportout1_hi_5 aportout1_hi_6 \



aportout1_hi_15 aportout1_lo_0 aportout1_lo_1 aportout1_lo_2 \

aportout1_lo_3 aportout1_lo_4 aportout1_lo_5 aportout1_lo_6 \



aportout1_lo_15 bitlinea_hi_0 bitlinea_hi_1 bitlinea_hi_2 \

bitlinea_hi_3 bitlinea_hi_4 bitlinea_hi_5 bitlinea_hi_6 \



bitlinea_hi_15 bitlinea_lo_0 bitlinea_lo_1 bitlinea_lo_2 \

bitlinea_lo_3 bitlinea_lo_4 bitlinea_lo_5 bitlinea_lo_6 \



bitlinea_lo_15 clk30 clk31 sel20 sel21 wrtbit1_hi_0 wrtbit1_hi_1 \

wrtbit1_hi_2 wrtbit1_hi_3 wrtbit1_hi_4 wrtbit1_hi_5 wrtbit1_hi_6 \

wrtbit1_hi_7 wrtbit1_hi_8 wrtbit1_hi_9 wrtbit1_hi_10 wrtbit1_hi_11 \

wrtbit1_hi_12 wrtbit1_hi_13 wrtbit1_hi_14 wrtbit1_hi_15 \

wrtbit1_lo_0 wrtbit1_lo_1 wrtbit1_lo_2 wrtbit1_lo_3 wrtbit1_lo_4 \

wrtbit1_lo_5 wrtbit1_lo_6 wrtbit1_lo_7 wrtbit1_lo_8 wrtbit1_lo_9 \

wrtbit1_lo_10 wrtbit1_lo_11 wrtbit1_lo_12 wrtbit1_lo_13 \

wrtbit1_lo_14 wrtbit1_lo_15 wrtbitline2_hi_0 wrtbitline2_hi_1 \





wrtbitline2_hi_14 wrtbitline2_hi_15 wrtbitline2_lo_0 \






inh_substrate

I28 (Vref_sens inh_substrate) vref_0p2mA_2x

I33 (Vref_muxlatch net31 net29 clk30_muxlatch clk31_muxlatch \


I32 (Vref_latch net31 net29 clk30_latch clk31_latch inh_substrate) \

buf_fet_L3_4x_L3in

161

I31 (Vref_worddrv clk30 clk31 net31 net29 inh_substrate) \

buf_fet_L3_4x_L3in

I0 (Vref_buf Vref_latch Vref_muxlatch Vref_sens Vref_worddrv \

aportout1_lo_0 aportout1_hi_0 bitlinea_lo_0 bitlinea_hi_0 \


match21 wrtbit1_lo_0 wrtbit1_hi_0 wrtbitline2_lo_0 \

wrtbitline2_hi_0 inh_substrate) sec_pipe_porta



































162










































163

I35 (Vref_buf sel20 sel21 match20 match21 inh_substrate) \

buf_fet_L2_4x_L2in

I19 (Vref_muxlatch inh_substrate) static_0p9V

I16 (Vref_worddrv inh_substrate) static_0p9V

I25 (Vref_buf inh_substrate) static_0p9V

I22 (Vref_latch inh_substrate) static_0p9V

ends sec_pipe_porta_16



// Cell name: datain_mslatch


subckt datain_mslatch Vref_ef Vref_mlatch Vref_slatch clkm30 clkm31 clks30 \

clks31 d20 d21 z20 z21 inh_substrate

I2 (Vref_ef net29 net27 z20 z21 inh_substrate) ef_fet_L2_1x

I1 (Vref_mlatch clkm31 clkm30 d20 d21 net22 net20 inh_substrate) \

latch_out_fet_L1_1x

I0 (Vref_slatch clks30 clks31 net22 net20 net29 net27 inh_substrate) \


ends datain_mslatch



// Cell name: datain_mslatch_16mod


subckt datain_mslatch_16mod clk30 clk31 d2_hi_0 d2_hi_10 d2_hi_11 d2_hi_12 \

d2_hi_13 d2_hi_14 d2_hi_15 d2_hi_1 d2_hi_2 d2_hi_3 d2_hi_4 d2_hi_5 \

d2_hi_6 d2_hi_7 d2_hi_8 d2_hi_9 d2_lo_0 d2_lo_10 d2_lo_11 d2_lo_12 \

d2_lo_13 d2_lo_14 d2_lo_15 d2_lo_1 d2_lo_2 d2_lo_3 d2_lo_4 d2_lo_5 \

d2_lo_6 d2_lo_7 d2_lo_8 d2_lo_9 z2_hi_0 z2_hi_1 z2_hi_2 z2_hi_3 \


z2_hi_12 z2_hi_13 z2_hi_14 z2_hi_15 z2_lo_0 z2_lo_1 z2_lo_2 \


z2_lo_11 z2_lo_12 z2_lo_13 z2_lo_14 z2_lo_15 inh_substrate

I0 (Vref_ef Vref_mlatch Vref_slatch clkm30 clkm31 clks30 clks31 \

d2_lo_15 d2_hi_15 z2_lo_15 z2_hi_15 inh_substrate) datain_mslatch






164


























I32 (Vref_mlatch net20 net18 clkm30 clkm31 inh_substrate) \

buf_fet_L3_4x_L3in

I31 (Vref_mlatch clk30 clk31 net20 net18 inh_substrate) \

buf_fet_L3_4x_L3in

I33 (Vref_slatch net20 net18 clks30 clks31 inh_substrate) \

buf_fet_L3_4x_L3in

I22 (Vref_mlatch inh_substrate) static_0p9V

I21 (Vref_slatch inh_substrate) static_0p9V

I20 (Vref_ef inh_substrate) static_0p9V

ends datain_mslatch_16mod



// Cell name: aportcomplete_mod


subckt aportcomplete_mod ahi alo aportout2_hi_0 aportout2_hi_1 \

165




aportout2_hi_14 aportout2_hi_15 aportout2_lo_0 aportout2_lo_1 \




aportout2_lo_14 aportout2_lo_15 bhi bitlinea_hi_0 bitlinea_hi_1 \




bitlinea_hi_14 bitlinea_hi_15 bitlinea_lo_0 bitlinea_lo_1 \




bitlinea_lo_14 bitlinea_lo_15 blo chi clk30 clk30_datams clk31 \

clk31_datams clo dhi dlo sel20 sel21 wrtbitline2_hi_0 \

















out1_lo_14 out1_lo_15 bitlinea_hi_0 bitlinea_hi_1 bitlinea_hi_2 \




bitlinea_hi_15 bitlinea_lo_0 bitlinea_lo_1 bitlinea_lo_2 \




166

bitlinea_lo_15 clk30 clk31 sel20 sel21 z2_hi_0 z2_hi_1 z2_hi_2 \


z2_hi_11 z2_hi_12 z2_hi_13 z2_hi_14 z2_hi_15 z2_lo_0 z2_lo_1 \


z2_lo_10 z2_lo_11 z2_lo_12 z2_lo_13 z2_lo_14 z2_lo_15 \






wrtbitline2_hi_15 wrtbitline2_lo_0 wrtbitline2_lo_1 \





wrtbitline2_lo_14 wrtbitline2_lo_15 inh_substrate) \

sec_pipe_porta_16

I3 (clk30_datams clk31_datams chi bhi ahi chi bhi ahi dhi bhi ahi chi \

bhi ahi chi bhi ahi chi clo blo alo clo blo alo dlo blo alo clo \

blo alo clo blo alo clo z2_hi_0 z2_hi_1 z2_hi_2 z2_hi_3 z2_hi_4 \


z2_hi_13 z2_hi_14 z2_hi_15 z2_lo_0 z2_lo_1 z2_lo_2 z2_lo_3 z2_lo_4 \


z2_lo_13 z2_lo_14 z2_lo_15 inh_substrate) datain_mslatch_16mod






out1_lo_14 out1_lo_15 aportout2_hi_0 aportout2_hi_1 aportout2_hi_2 \








aportout2_lo_15 inh_substrate) ef_fet_L2_1x_16

ends aportcomplete_mod


167


// Cell name: sec_pipe_complete_16mod


subckt sec_pipe_complete_16mod ahi alo aportout2_hi_0 aportout2_hi_1 \




aportout2_hi_14 aportout2_hi_15 aportout2_lo_0 aportout2_lo_1 \




aportout2_lo_14 aportout2_lo_15 bhi blo bportout2_hi_0 \




bportout2_hi_13 bportout2_hi_14 bportout2_hi_15 bportout2_lo_0 \




bportout2_lo_13 bportout2_lo_14 bportout2_lo_15 chi clk30_A \

clk30_B clk30_data clk31_A clk31_B clk31_data clo dhi dlo match20A \

match20B match21A match21B reada3_0 reada3_1 reada3_2 reada3_3 \

reada3_4 reada3_5 reada3_6 reada3_7 readb3_0 readb3_1 readb3_2 \

readb3_3 readb3_4 readb3_5 readb3_6 readb3_7 wr_hi3_0 wr_hi3_1 \

wr_hi3_2 wr_hi3_3 wr_hi3_4 wr_hi3_5 wr_hi3_6 wr_hi3_7 wr_lo3_0 \

wr_lo3_1 wr_lo3_2 wr_lo3_3 wr_lo3_4 wr_lo3_5 wr_lo3_6 wr_lo3_7 \

inh_substrate

I6 (rbitb_hi_0 rbitb_hi_1 rbitb_hi_2 rbitb_hi_3 rbitb_hi_4 rbitb_hi_5 \














168

clk30_B clk31_B match20B match21B wrtbitline2_hi_0 \











wrtbitline2_lo_15 inh_substrate) bportcomplete

I0 (rbita_hi_0 rbita_hi_1 rbita_hi_2 rbita_hi_3 rbita_hi_4 rbita_hi_5 \












iworda_0 iworda_1 iworda_2 iworda_3 iworda_4 iworda_5 iworda_6 \

iworda_7 iwordb_0 iwordb_1 iwordb_2 iwordb_3 iwordb_4 iwordb_5 \

iwordb_6 iwordb_7 net68_0 net68_1 net68_2 net68_3 net68_4 net68_5 \

net68_6 net68_7 wrtbitline2_hi_0 wrtbitline2_hi_1 wrtbitline2_hi_2 \










wrtbitline2_lo_14 wrtbitline2_lo_15 wword_hi_0 wword_hi_1 \

wword_hi_2 wword_hi_3 wword_hi_4 wword_hi_5 wword_hi_6 wword_hi_7 \

wword_lo_0 wword_lo_1 wword_lo_2 wword_lo_3 wword_lo_4 wword_lo_5 \

wword_lo_6 wword_lo_7 inh_substrate) memcell_8word16bit

169

I4 (iworda_0 iworda_1 iworda_2 iworda_3 iworda_4 iworda_5 iworda_6 \

iworda_7 iwordb_0 iwordb_1 iwordb_2 iwordb_3 iwordb_4 iwordb_5 \

iwordb_6 iwordb_7 reada3_0 reada3_1 reada3_2 reada3_3 reada3_4 \

reada3_5 reada3_6 reada3_7 readb3_0 readb3_1 readb3_2 readb3_3 \

readb3_4 readb3_5 readb3_6 readb3_7 wr_hi3_0 wr_hi3_1 wr_hi3_2 \

wr_hi3_3 wr_hi3_4 wr_hi3_5 wr_hi3_6 wr_hi3_7 wr_lo3_0 wr_lo3_1 \

wr_lo3_2 wr_lo3_3 wr_lo3_4 wr_lo3_5 wr_lo3_6 wr_lo3_7 wword_hi_0 \

wword_hi_1 wword_hi_2 wword_hi_3 wword_hi_4 wword_hi_5 wword_hi_6 \

wword_hi_7 wword_lo_0 wword_lo_1 wword_lo_2 wword_lo_3 wword_lo_4 \

wword_lo_5 wword_lo_6 wword_lo_7 inh_substrate) \

worddrv_8word_16bit

I1 (net68_0 net68_1 net68_2 net68_3 net68_4 net68_5 net68_6 net68_7 \

inh_substrate) tword_8word16bit

I5 (ahi alo aportout2_hi_0 aportout2_hi_1 aportout2_hi_2 \








aportout2_lo_15 bhi rbita_hi_0 rbita_hi_1 rbita_hi_2 rbita_hi_3 \



rbita_hi_15 rbita_lo_0 rbita_lo_1 rbita_lo_2 rbita_lo_3 rbita_lo_4 \


rbita_lo_11 rbita_lo_12 rbita_lo_13 rbita_lo_14 rbita_lo_15 blo \

chi clk30_A clk30_data clk31_A clk31_data clo dhi dlo match20A \

match21A wrtbitline2_hi_0 wrtbitline2_hi_1 wrtbitline2_hi_2 \










wrtbitline2_lo_14 wrtbitline2_lo_15 inh_substrate) \

aportcomplete_mod

ends sec_pipe_complete_16mod

170



// Cell name: regfile_8x32_finalmod2_fix


subckt regfile_8x32_finalmod2_fix address_ahi_2 address_ahi_1 \

address_ahi_0 address_alo_2 address_alo_1 address_alo_0 \

address_bhi_2 address_bhi_1 address_bhi_0 address_blo_2 \

address_blo_1 address_blo_0 address_whi_2 address_whi_1 \

address_whi_0 address_wlo_2 address_wlo_1 address_wlo_0 \

aport_out_hi_0 aport_out_hi_13 aport_out_hi_14 aport_out_hi_15 \

aport_out_lo_0 aport_out_lo_13 aport_out_lo_14 aport_out_lo_15 \

bport_out_hi_0 bport_out_hi_13 bport_out_hi_14 bport_out_hi_15 \

bport_out_lo_0 bport_out_lo_13 bport_out_lo_14 bport_out_lo_15 \

clk30 clk31 h20 h21 l20 l21 m20 m21 match20A match20B match21A \

match21B wen20 wen21 inh_substrate

I13 (address_ahi_0 address_ahi_1 address_ahi_2 address_alo_0 \

address_alo_1 address_alo_2 address_bhi_0 address_bhi_1 \

address_bhi_2 address_blo_0 address_blo_1 address_blo_2 \

address_whi_0 address_whi_1 address_whi_2 address_wlo_0 \

address_wlo_1 address_wlo_2 clk30_adda clk30_addb clk30_addw \

clk30_match clk30_match clk31_adda clk31_addb clk31_addw \

clk31_match clk31_match match21A match21B match20A match20B \

reada3_0 reada3_1 reada3_2 reada3_3 reada3_4 reada3_5 reada3_6 \

reada3_7 readb3_0 readb3_1 readb3_2 readb3_3 readb3_4 readb3_5 \

readb3_6 readb3_7 wrhi_3_0 wrhi_3_1 wrhi_3_2 wrhi_3_3 wrhi_3_4 \

wrhi_3_5 wrhi_3_6 wrhi_3_7 wrlo_3_0 wrlo_3_1 wrlo_3_2 wrlo_3_3 \

wrlo_3_4 wrlo_3_5 wrlo_3_6 wrlo_3_7 wen20 wen21 inh_substrate) \

address_cct_fix

I1 (h21 h20 aport_out_hi_15 aport_out_hi_14 aport_out_hi_13 \




aport_out_hi_0 aport_out_lo_15 aport_out_lo_14 aport_out_lo_13 \




aport_out_lo_0 m21 m20 bport_out_hi_15 bport_out_hi_14 \




171

bport_out_hi_1 bport_out_hi_0 bport_out_lo_15 bport_out_lo_14 \




bport_out_lo_1 bport_out_lo_0 l21 clk30_right clk30_right \

clk30_right clk31_right clk31_right clk31_right l20 m21 m20 \

match20A match20B match21A match21B reada3_0 reada3_1 reada3_2 \

reada3_3 reada3_4 reada3_5 reada3_6 reada3_7 readb3_0 readb3_1 \

readb3_2 readb3_3 readb3_4 readb3_5 readb3_6 readb3_7 wrhi_3_0 \

wrhi_3_1 wrhi_3_2 wrhi_3_3 wrhi_3_4 wrhi_3_5 wrhi_3_6 wrhi_3_7 \

wrlo_3_0 wrlo_3_1 wrlo_3_2 wrlo_3_3 wrlo_3_4 wrlo_3_5 wrlo_3_6 \

wrlo_3_7 inh_substrate) sec_pipe_complete_16mod

I0 (h21 h20 aport_out_hi_16 aport_out_hi_17 aport_out_hi_18 \








aport_out_lo_31 m21 m20 bport_out_hi_16 bport_out_hi_17 \




bport_out_hi_30 bport_out_hi_31 bport_out_lo_16 bport_out_lo_17 \




bport_out_lo_30 bport_out_lo_31 l21 clk30_left clk30_left \

clk30_left clk31_left clk31_left clk31_left l20 h21 h20 match20A \

match20B match21A match21B reada3_0 reada3_1 reada3_2 reada3_3 \

reada3_4 reada3_5 reada3_6 reada3_7 readb3_0 readb3_1 readb3_2 \

readb3_3 readb3_4 readb3_5 readb3_6 readb3_7 wrhi_3_0 wrhi_3_1 \

wrhi_3_2 wrhi_3_3 wrhi_3_4 wrhi_3_5 wrhi_3_6 wrhi_3_7 wrlo_3_0 \

wrlo_3_1 wrlo_3_2 wrlo_3_3 wrlo_3_4 wrlo_3_5 wrlo_3_6 wrlo_3_7 \

inh_substrate) sec_pipe_complete_16mod

I15 (net060 clk30_right clk31_right net055 net053 inh_substrate) \

buf_fet_L3_4x_L3in

I16 (net060 net055 net053 clk30_match clk31_match inh_substrate) \

buf_fet_L3_4x_L3in

I17 (net060 net055 net053 clk30_addb clk31_addb inh_substrate) \

172

buf_fet_L3_4x_L3in

I18 (net058 net030 net028 clk30_addw clk31_addw inh_substrate) \

buf_fet_L3_4x_L3in

I19 (net059 net030 net028 clk30_adda clk31_adda inh_substrate) \

buf_fet_L3_4x_L3in

I20 (net059 clk30_left clk31_left net030 net028 inh_substrate) \

buf_fet_L3_4x_L3in

I23 (net057 clk30 clk31 clk30_left clk31_left inh_substrate) \

buf_fet_L3_4x_L3in

I24 (net057 clk30 clk31 clk30_right clk31_right inh_substrate) \

buf_fet_L3_4x_L3in





ends regfile_8x32_finalmod2_fix





subckt ef_fet_L23_4x Vref i10 i11 z20 z21 z30 z31 inh_substrate








Q0 (z20 z20 z30 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q1 (z21 z21 z31 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

173



pbm2=320.0n



pbm2=320.0n

ends ef_fet_L23_4x















pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q2 (Vcc! i10 net051 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q3 (Vcc! i11 net048 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends ef_fet_L3_1x


174


// Cell name: divby2


subckt divby2 Vref c30 c31 z10 z11 inh_substrate

I4 (Vref c31 c30 z11 z10 net18 net16 inh_substrate) \


I5 (Vref c30 c31 net18 net16 z10 z11 inh_substrate) \


ends divby2



// Cell name: divby16_L23


subckt divby16_L23 clkin_30 clkin_31 divby16_20 divby16_21 divby16_30 \

divby16_31 inh_substrate

I15 (Vref net49 net50 divby16_20 divby16_21 divby16_30 divby16_31 \

inh_substrate) ef_fet_L23_4x


I12 (Vref net56 net55 divby2_30 divby2_31 inh_substrate) ef_fet_L3_1x



I11 (Vref divby8_30 divby8_31 net49 net50 inh_substrate) divby2

I8 (Vref clkin_30 clkin_31 net56 net55 inh_substrate) divby2



ends divby16_L23



// Cell name: and2_fet_L1_1x


subckt and2_fet_L1_1x Vref a10 a11 b20 b21 z10 z11 inh_substrate









175



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n

ends and2_fet_L1_1x














Q0 (z11 i10 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n

Q1 (z10 i11 net18 inh_substrate) npn mult=(1) enl=640.0n enw=200.0n \


pbm2=320.0n



176

pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends buf_fet_L1_1x







I2 (Vref i10 i11 net40 net39 inh_substrate) buf_fet_L1_1x

ends buf_fet_L2_2x



// Cell name: wen_synced_v2


subckt wen_synced_v2 clk20_div16 clk21_div16 wren20 wren21 wren20_8 \

wren21_8 inh_substrate


I24 (net9 wren20 wren21 net10 net11 inh_substrate) buf_fet_L1_1x_L2in

I23 (net9 net10 net11 clk20_div16 clk21_div16 net18 net17 \


I21 (net9 net18 net17 wren20_8 wren21_8 inh_substrate) buf_fet_L2_2x

ends wen_synced_v2



// Cell name: padreceiver_4x_v2c


subckt padreceiver_4x_v2c Pad o20 o21 o30 o31 inh_substrate

I7 (Vref net102 net99 net59 net60 inh_substrate) buf_fet_L1_1x

C0 (Pad net63 inh_substrate) mim c=3.8656p l=48.0u w=80.0u bp=2 m=1 \

est=0 nlev=7 setind=-2 dtemp=0






177






RPPC8 (Vcc! Pad inh_substrate) opppcres r=49.98 w=10u l=1.74u m=1 \










RN1 (Vcc! net102 inh_substrate) opppcres r=249.21 w=3.0u l=2.66u m=1 \








pbm2=320.0n

Q31 (o31 o31 net069 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

Q30 (o21 o21 o31 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



178

pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q22 (net109 net109 Vee! inh_substrate) npn mult=(1) enl=2.56u \


pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q17 (net115 net115 Vee! inh_substrate) npn mult=(1) enl=2.56u \


pbm1=420.0n pbm2=320.0n

Q26 (Pad Pad Vcc! inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q27 (Vee! Vee! Pad inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n

ends padreceiver_4x_v2c



// Cell name: pad_10_power_CPU


subckt pad_10_power_CPU S_1 S_2 inh_groundplane inh_substrate










179


I39 (S_2 inh_groundplane inh_substrate) bondpad area=1.1881e-08 \

perim=0.000436 grnd=-1 rect=1 nlev=7 dtemp=0

I38 (Vee! inh_groundplane inh_substrate) bondpad area=1.1881e-08 \


I37 (Vcc! inh_groundplane inh_substrate) bondpad area=1.1881e-08 \
















ends pad_10_power_CPU



// Cell name: padreceiver_4x


subckt padreceiver_4x Pad o20 o21 o30 o31 inh_substrate














180










Q25 (Vcc! Vcc! Pad inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q0 (Pad Pad net42 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n

Q2 (Vcc! Vcc! net51 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



181

pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm2=320.0n

ends padreceiver_4x
















pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n


182


pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm1=420.0n pbm2=320.0n




// Cell name: esd


subckt esd Pad inh_substrate




pbm2=320.0n



pbm2=320.0n

ends esd



// Cell name: paddriver


subckt paddriver Vref i10 i11 pad inh_substrate





pbm2=320.0n



pbm1=420.0n pbm2=320.0n


183


pbm2=320.0n



pbm2=320.0n

Q12 (Vcc! Vcc! net060 inh_substrate) npn mult=(1) enl=5.12u enw=200.0n \


pbm2=320.0n



pbm2=320.0n



pbm2=320.0n



pbm1=420.0n pbm2=320.0n



pbm2=320.0n

Q13 (Vee! Vee! net054 inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q8 (pad net15 net25 inh_substrate) npn mult=(1) enl=5.12u enw=200.0n \


pbm2=320.0n

Q27 (net054 net054 pad inh_substrate) npn mult=(1) enl=2.56u \


pbm1=420.0n pbm2=320.0n

Q10 (pad pad Vcc! inh_substrate) npn mult=(1) enl=2.56u enw=200.0n \


pbm2=320.0n

Q11 (Vcc! Vcc! pad inh_substrate) npn mult=(1) enl=5.12u enw=200.0n \


pbm2=320.0n







184




ends paddriver



// Cell name: pad_10


subckt pad_10 S_1 S_2 S_3 S_4 S_5 S_6 inh_groundplane inh_substrate































ends pad_10

185



// Cell name: ring_n_padsv4


subckt ring_n_padsv4 clk_sel clksel30 clksel31 ctr_stop ctrstop20 \

ctrstop21 ext_clk extclk20 extclk21 scope_out scopeout30 \

scopeout31 sel_a sel_b sel_c sel_d sela20 sela21 selb30 selb31 \

selc20 selc21 seld30 seld31 sync_out syncout30 syncout31 \

vco_ctrl_a vco_ctrl_b wr_en wren20 wren21 inh_groundplane \

inh_substrate

I4 (ext_clk extclk20 extclk21 net129 net128 inh_substrate) \

padreceiver_4x_v2c

I27 (Vcc! Vcc! inh_groundplane inh_substrate) pad_10_power_CPU

I7 (wr_en wren20 wren21 net144 net143 inh_substrate) padreceiver_4x

I6 (ctr_stop ctrstop20 ctrstop21 net139 net138 inh_substrate) \

padreceiver_4x

I5 (clk_sel net136 net135 clksel30 clksel31 inh_substrate) \

padreceiver_4x

I8 (sel_a sela20 sela21 net124 net123 inh_substrate) padreceiver_4x

I9 (sel_b net121 net120 selb30 selb31 inh_substrate) padreceiver_4x

I10 (sel_c selc20 selc21 net114 net113 inh_substrate) padreceiver_4x

I11 (sel_d net111 net110 seld30 seld31 inh_substrate) padreceiver_4x


I21 (net102 syncout30 syncout31 net100 net99 inh_substrate) \

buf_fet_L1_1x_L3in

I20 (net106 scopeout30 scopeout31 net104 net103 inh_substrate) \

buf_fet_L1_1x_L3in

I18 (vco_ctrl_a inh_substrate) esd

I19 (vco_ctrl_b inh_substrate) esd



I12 (net106 net104 net103 scope_out inh_substrate) paddriver

I23 (net102 net100 net99 sync_out inh_substrate) paddriver

I0 (vco_ctrl_a vco_ctrl_b ext_clk clk_sel ctr_stop wr_en \

inh_groundplane inh_substrate) pad_10

I1 (sel_a sel_b scope_out sync_out sel_c sel_d inh_groundplane \

inh_substrate) pad_10

ends ring_n_padsv4


186

// Library name: regfil7hp

// Cell name: Power_3p4V


subckt Power_3p4V Vcc Vee

VtotalI (Vcc! Vcc) vsource dc=0 mag=0 type=dc

V5 (Vee! Vee) vsource dc=0 mag=0 type=dc

V7 (Vcc! Vee!) vsource dc=3.4 mag=0 type=dc

V6 (Vcc! 0) vsource dc=0 mag=0 type=dc

ends Power_3p4V


// Library name: regfil7hpv4_7Mtest

// Cell name: regfilchip_sim4j_16GHz


I22 (net098 net099 net0100 clk30_before_dist clk31_before_dist sub!) \

buf_fet_L3_4x

I18 (net098 clk30_before_dist clk31_before_dist clk30_regfile \

clk31_regfile sub!) buf_fet_L3_4x_L3in

I19 (net098 clk30_before_dist clk31_before_dist clk30_counters_before \

clk31_counters_before sub!) buf_fet_L3_4x_L3in

I34 (net098 clk30_counters_before clk31_counters_before clk30_counters \

clk31_counters sub!) buf_fet_L3_4x_L3in

I17 (net098 net0107 net0108 net099 net0100 sub!) buf_fet_L1_2x

I14 (net0112 net0121 net0122 extclk20 extclk21 clksel30 clksel31 net0107 \

net0108 sub!) mux2_fet_L1_L2in_1x

I15 (net0112 sub!) static_0p9V

I20 (net098 sub!) static_0p9V

I5 (vcoconta net0119 net0118 net0116 net0115 net0121 net0122 net0117 \

net0120 sub!) _sub2

I2 (clk30_counters clk31_counters ctrstop20 ctrstop21 clo chi blo bhi alo \

ahi wren20_8 wren21_8 sub!) counter_3bit_data

I1 (clk30_counters clk31_counters ctrstop20 ctrstop21 address_blo_0 \

address_bhi_0 address_blo_1 address_bhi_1 address_blo_2 \

address_bhi_2 sub!) counter_3bit_address

I3 (clk30_counters clk31_counters ctrstop20 ctrstop21 address_alo_0 \

address_ahi_0 address_alo_1 address_ahi_1 address_alo_2 \

address_ahi_2 sub!) counter_3bit_address

I16 (clk30_counters clk31_counters wren20_8 wren21_8 address_wlo_0 \

address_whi_0 address_wlo_1 address_whi_1 address_wlo_2 \

address_whi_2 sub!) counter_3bit_address

I10 (aport_out_lo_15 aport_out_hi_15 aport_out_lo_14 aport_out_hi_14 \

187

aport_out_lo_13 aport_out_hi_13 aport_out_lo_0 aport_out_hi_0 \

sela20 sela21 selb30 selb31 muxb20 muxb21 sub!) mux_outv2

I11 (bport_out_lo_15 bport_out_hi_15 bport_out_lo_14 bport_out_hi_14 \

bport_out_lo_13 bport_out_hi_13 bport_out_lo_0 bport_out_hi_0 \

sela20 sela21 selb30 selb31 muxc20 muxc21 sub!) mux_outv2

I12 (address_wlo_0 address_whi_0 address_wlo_1 address_whi_1 address_wlo_2 \

address_whi_2 match20B match21B sela20 sela21 selb30 selb31 muxd20 \

muxd21 sub!) mux_outv2

I9 (address_alo_0 address_ahi_0 address_alo_1 address_ahi_1 address_alo_2 \

address_ahi_2 match20A match21A sela20 sela21 selb30 selb31 muxa20 \

muxa21 sub!) mux_outv2

I13 (muxa20 muxa21 muxb20 muxb21 muxc20 muxc21 muxd20 muxd21 selc20 selc21 \

seld30 seld31 scopeout30 scopeout31 sub!) mux_out

I8 (address_ahi_2 address_ahi_1 address_ahi_0 address_alo_2 address_alo_1 \

address_alo_0 address_bhi_2 address_bhi_1 address_bhi_0 \

address_blo_2 address_blo_1 address_blo_0 address_whi_2 \

address_whi_1 address_whi_0 address_wlo_2 address_wlo_1 \

address_wlo_0 aport_out_hi_0 aport_out_hi_13 aport_out_hi_14 \


aport_out_lo_15 bport_out_hi_0 bport_out_hi_13 bport_out_hi_14 \

bport_out_hi_15 bport_out_lo_0 bport_out_lo_13 bport_out_lo_14 \

bport_out_lo_15 clk30_regfile clk31_regfile alo ahi clo chi blo \

bhi match20A match20B match21A match21B wren20_8 wren21_8 sub!) \

regfile_8x32_finalmod2_fix

I6 (clk30_before_dist clk31_before_dist clk20_div16 clk21_div16 syncout30 \

syncout31 sub!) divby16_L23

I26 (clk20_div16 clk21_div16 wren20 wren21 wren20_8 wren21_8 sub!) \

wen_synced_v2

I0 (clksel_pad clksel30 clksel31 ctrstop_pad ctrstop20 ctrstop21 \

extclk_pad extclk20 extclk21 scopeout_pad scopeout30 scopeout31 \

sela_pad selb_pad selc_pad seld_pad sela20 sela21 selb30 selb31 \

selc20 selc21 seld30 seld31 syncout_pad syncout30 syncout31 \

vcoconta vcocontb wren_pad wren20 wren21 vdd! sub!) ring_n_padsv4

V4 (Vcc! extclk_pad) vsource type=sine ampl=400m freq=16G

V9 (Vcc! wren_pad) vsource type=pulse val0=400m val1=-400.0m period=10n \

delay=1.0n rise=2p fall=2p width=1.4n

V3 (Vcc! ctrstop_pad) vsource type=pulse val0=400.0m val1=-400.0m \

period=4n delay=500.0p rise=2p fall=2p width=3n

V2 (Vcc! clksel_pad) vsource type=pulse val0=400.0m val1=-400m period=10n \

delay=500.0p rise=2p fall=2p width=9.5n

V5 (Vcc! sela_pad) vsource dc=400.0m type=dc

188

V6 (Vcc! selb_pad) vsource dc=400.0m type=dc

V0 (Vcc! vcoconta) vsource dc=1.05 type=dc

V1 (Vcc! vcocontb) vsource dc=1.05 type=dc

V7 (Vcc! selc_pad) vsource dc=400.0m type=dc

V8 (Vcc! seld_pad) vsource dc=400.0m type=dc

I7 (net047 net046) Power_3p4V

Documents

A Three-Port Pipelined Register File Implemented Using s ...ecse.rpi.edu/frisc/theses/ErdoganThesis/A Three-Port Pipelined Register File... · A Three-Port Pipelined Register File