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3.3 CMOS Logic 1. CMOS Logic Levels
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Logic levels for typical CMOS Logic circuits.
Logic 1 (HIGH)
Logic 0 (LOW)
UndefinedLogic level
5.0V
3.5V
1.5V
0.0V
3.3 CMOS Logic 2. MOS Transistors A MOS transistor can be modeled as a 3-terminal device that acts like a voltage controlled resistance.
VIN
In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “off”) or very low (and the transistor is “on”) .
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3.3 CMOS Logic n-channel MOS (NMOS)
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Increase Vgs→decrease Rds
Normally, Vgs≥ 0
• Vgs=0 → Rds 106 () → I 10-6 (A) 0
gate
drain
sourceVgs
+
-
drain
gate
sourceVgs
+
-
•Vgs Vgs(th) → Rds 10 () << RL →VRds 0
3.3 CMOS Logic p-channel MOS (PMOS)
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Decrease Vgs→decrease Rds
Normally, Vgs 0
• Vgs=0 → Rds ≥ 106 ()
• Vgs Vgs(th) → Rds 10 ()
gatedrain
sourceVgs+
-
draingate
sourceVgs+
-
Switch Model
3.3 CMOS Logic3. Basic CMOS Inverter Circuit
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VIN Q1 Q2 VOUT
0.0(L) off on 5.0(H)
VDD=+5.0V
VIN
VOUT
Q2 (PMOS)
Q1 (NMOS)
VDD=+5.0V
VIN=L VOUT=H
VDD=+5.0V
VIN=H VOUT=L
5.0(H) on off 0.0(L)
3.3 CMOS Logic CMOS inverter logical operation
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A
VDD=+5.0V
ZQ2 (PMOS)
Q1 (NMOS)
On when Vin is low.
On when Vin is high.
A Z
01
10
Truth table for
CMOS inverter
AZ
A
VDD
Z
B
Q1
Q2
Q3
Q4
3.3 CMOS Logic
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4. CMOS NAND GatesA B Q1 Q2 Q3 Q4 Z
LLHH
LHLH
offoffonon
ononoffoff
offonoffon
onoffonoff
HHHL
BAZ
A B Z
0011
0101
1110
A=L
VDD
B=L
Z=H
VDD
A=L
B=H
Z=H
VDD
A=H
B=L
Z=H
VDD
A=H
B=H
Z=L
AB
Z
3.3 CMOS Logic
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5. CMOS NOR GatesA B Q1 Q2 Q3 Q4 Z
LLHH
LHLH
offoffonon
ononoffoff
offonoffon
onoffonoff
HLLL
BAZ A B Z
0011
0101
1000
B
A
VDD
ZQ4
Q2
Q1 Q3
AB
Z
3.3 CMOS Logic
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6. Fan-In In principle, you could design a CMOS NAND or NOR gate with a large number of inputs. A 3-input CMOS NAND gate is showed in the figure.
A
VDD
Z
B
Q1
Q2
Q3
Q4Q6
C Q5
Why couldn't a CMOS gate has large number of inputs?
3.3 CMOS Logic
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Fan-In
The number of inputs that a gate can have in a particular logic family is called the logic family’s fan-in. The fan-in of CMOS gates is typically 4 for NOR gates and 6 for NAND gates. Why is the fan-in of CMOS gates for NOR gates less than the ones for NAND gates?
A n-channel transistor has low “on” resistance than a p-channel transistor. As a result, a k-input NAND gate is generally faster than a k-input NOR gate.
3.3 CMOS Logic
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Fan-In As the number of inputs is increased, designers of CMOS gate circuits may compensate by increasing the size of the series transistors to reduce their resistance and the corresponding switching delay.I2I3I4
I1
OUTI6I7I8
I5
I2I3I4
I1
I6I7I8
I5OUT
3.3 CMOS Logic 7. Noninverting Gates (P93) AND Gate
OR Gate
8. CMOS AND-OR-INVERT Gate (P94)
9.CMOS OR-AND-INVERT Gate (P95)
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3.3 CMOS Logic10. CMOS Steady-State Electrical Behavior
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1.5
3.5
5.0
1.5 3.5 5.0
Vout
Vin
HIGH
undefined
LOW
LOW undefined HIGH
Typical input-output transfer characteristic of a CMOS
inverter
VOLmax: The maximum output voltage in the LOW state. VOLmax=ground+0.1V
3.3 CMOS Logic Logic Levels and Noise Margins
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0.7Vcc
0.3Vcc
0
Vcc
ABNORMAL
HIGH
LOW
VOHmin
VIHmin
VILmax
VOLmax
High-stateDC noise margin
Low-state DC noise margin
VOHmin: The minimum output voltage in the HIGH state. VOHmin=VCC–0.1V
DC noise margin: is a measure of how much noise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input.
HIGH-state DC noise margin: VOHmin -VIHmin
LOW-state DC noise margin: VILmax -VOLmax
3.3 CMOS Logic VIHmin: The minimum input voltage guarante
ed to be recognized as a HIGH. VIHmin=0.7VCC
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VILmax: The maximum input voltage guaranteed to be recognized as a LOW.
VILmax=0.3VCC
Regardless of the voltage applied to the input of a CMOS device, only the leakage current of the transistors connected to input. This is in sharp contrast to bipolar logic circuits like TTL oe ECL, whose inputs consume significant current (and power) in one or both states.
3.3 CMOS Logic IIH: The maximum current that flows into the input in the HIGH state.
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IIL: The maximum current that flows into the input in the LOW state.
3.3 CMOS Logic Circuit Behavior with Resistive Loads
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Resistive Loads: (P102).
IOHmax: The maximum current that the output can sink in the HIGH state while still maintaining an output voltage no less than VOHmin.
IOLmax: The maximum current that the output can sink in the LOW state while still maintaining an output voltage no greater than VOLmax.
Overall Fanout : is the minimum of the HIGH-state and LOW-state fanouts.
3.3 CMOS Logic Fanout : The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications.
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(load)I
(drive)IN
IL
OLOL
(load)I
(drive)IN
IH
OHOH
DC Fanout : the output in a constant state (HIGH or LOW).
3.3 CMOS Logic
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Transition Time : The amount of time that output of a logic circuit takes to change from one state to another.
11. CMOS Dynamic Electrical Behavior
tr tf
tr tf
VIHminVILmax
(a) ideal case
(b) approximation
(C) actual case
3.3 CMOS Logic Rise time(tr) : the amount of time an out
put voltage takes to pass through the “undefined” region from LOW to HIGH.
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Fall time(tf) : the amount of time an output voltage takes to pass through the “undefined” region from HIGH to LOW. The rise and fall times of a CMOS output depend mainly on two factors, the “on” transistor resistance and the load capacitance.
3.3 CMOS Logic Propagation Delay : the amount of time that it takes for a change in the input signal to produce a change in the output signal.
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tpHL tpLH
Propagation delays for a CMOS inverter
tpHL: The time between an input change and the corresponding output change when the output is changing from HIGH to LOW.
tpLH: The time between an input change and the corresponding output change when the output is changing from LOW to HIGH.
Static power dissipation: The power consumption of a CMOS circuit whose output is not changing.
3.3 CMOS Logic
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tpHL tpLH
50% VIH
50% VOH
Propagation delays for a CMOS inverter measured at midpoints of transitions
Power Consumption
PT: The circuit’s internal power dissipation due to output transitions. CPD: The power-dissipation capacitance. f : The transition frequency of the output signal.
Dynamic power dissipation: The power consumption of a CMOS circuit whose output is changing. It’s significant.
3.3 CMOS Logic
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Most CMOS circuits have very low quiescent power dissipation. This is what makes them so attractive for laptop computers and other low-power application.
fVCP CCPDT 2
3.3 CMOS Logic
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PL: the total amount of power dissipated by charging and discharging CL. CL: capacitive load on the output.
fVCP CCLL 2
The total dynamic power dissipation PD of a CMOS circuit is the sum of PT and PL.
LTD PPP fVCC CCLPD 2)( Based on this formula, dynamic power dissipation is often called CV2f power.
(2) A slightly overloaded circuit will fail. Loading an output beyond its rated fanout will make the output voltage(VOL) increase beyond VOLmax in the LOW state, and the output voltage(VOH) fall bellow VOHmin in the HIGH state, and propagation delay to the output increase beyond specification, and out rise and fall times increase beyond specification, and the operating temperature of the device increase.
3.3 CMOS Logic
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Notice (1) The output voltage will move away from the power-supply rail with nonideal inputs.
An unused AND or NAND input can be tied to logic 1.
3.3 CMOS Logic (3) An unused inputs can be tied to another.
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AB
F
C
AB
FC
+5V1k
pull-up resisto
r pull-down
resistor
An unused OR or NOR input can be tied to logic 0.
AB
F
C1k
3.3 CMOS Logic A pull-up or pull-down resistor is usually used. The resistor value is typically in the range 1-10k. Such a single resistor can serve multiple unused inputs. It is also possible to tie unused inputs directly to the appropriate power-supply rail.
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Unused CMOS inputs should never be left unconnected (or floating). Why?
3.3 CMOS Logic
(4) Systems that use CMOS circuits require decoupling capacitors between VCC and ground.
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(5) ESD(Electro-Static Discharge) may damage the insulation between an input transistor’s gate and source and drain, causing a short-circuit between the device’s input and output.
3.3 CMOS Logic
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How can you create a 2-input multiplexer using transmission gates? (P123)
12. Transmission Gates
EN_L
EN
A B
EN_L=0
EN=1
A B
EN_L=1
EN=0
A B
3.3 CMOS Logic
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13. Schmitt-Trigger Inputs
Voltage of hysteresis =VT+-VT-
VOUT
VIN
VT- VT+
2.1 2.9 5.0
5.0
EN A B C D Q1 Q2 OUT L L H H L off off Hi-Z L H H H L off off Hi-Z H L L H H on off L H H L L L off on H
3.3 CMOS Logic
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14. Three-State OutputsVCC
OUT
C
DAB
EN
EN
A OUT
VCC
OUT
C
DA
EN
VCC
OUT
C
DA
EN
VCC
OUT
C
DA
EN
3.3 CMOS Logic
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15. Open-Drain Outputs
B
VCC
ZQ2
Q1
A
A B Q1 Q2 Z L L off off open L H off on open H L on off open H H on on L
AB
Z
RPAB Z
VP
RL
Pull-up
resistor
3.3 CMOS Logic
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Pull-up resistor calculation
AB
Z=VOHmin
VPRP
ILHIOHmin
RL
LHOH
OHpp II
VVR
min
minmax
LLOL
OLpp II
VVR
max
maxmin
Open-drain gates can be useful in driving light-emitting diodes (LEDs) and other devices; performing wired logic; and driving multisource buses.
A
B
Z=VOHmin
VPRP
ILLIOLmax RL
3.3 CMOS Logic
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16. CMOS Logic Families The first commercially successful CMOS family was 4000-series CMOS. 74 FAM nn
prefixAlphabetic
family mnemonic
Numeric function
designator
3.3 CMOS Logic
HC: High-speed CMOS HCT: High-speed CMOS, TTL compatible VHC: Very High-speed CMOS VHCT: Very High-speed CMOS, TTL compatible
Electrical characteristics of the HC, HCT, VHC, and VHCT are different. They are summarized on page 137-144 in the text-book.
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