220 PracticeProblems 8 MultiCycleDP Sol

CS220Spring2015PracticeProblems#8Solutions

Problem1:Assumingthefollowingtimingsforthecomponentsofthedatapath.Allothercomponentshavenodelay.

Data/InstructionMemoryRead:200ps DataMemoryWrite:100ps RegisterFileRead:100ps RegisterFileWrite:50ps

Adders:80ps ALUs:200ps LogicalShifter/SignExtension:30ps Multiplexorsandothergates:10ps

a. Calculatethedelayforeachclockcycleofthemulti‐cycledatapathfinitestatemachine(eachstageofeachinstruction,i.e.eachbubble).Seeattachedpages

b. Whatistheminimumclockcycleperiodatwhichthemulti‐cycledatapathcanoperateproperly?270psWhatisthelengthofeachinstructiontypeinps(R‐type,lw,sw,beq,j)?

lw270*5=1350ps sw/r‐type270*4=1080ps beq/j270*3=810ps

Problem2:MIPSExecutionExaminethefollowingMIPSprogramP.

add $t0, $s4, $s3 and $t2, $t0, $s1 add $t1, $t1, $t1 add $t2, $t2, $t2 lw $t3, OPTION beq $s0, $t3, PARSE_WRITE_SP_LE and $t0, $t1, 0xff and $t1, $t1, 0xff00 or $t1, $t1, $t0 and $t0, $t2, 0xff and $t2, $t2, 0xff00 or $t2, $t2, $t0 PARSE_WRITE_SP_LE: sw $t1, 0($a1) lw $v0, WRITE_FILE sw $t2, 0($a1)

a. Inthemulticycledatapath,inwhichclockcycleisthelw $t3, OPTION instructionfetched?17thcycleb. Inthemulticycledatapath,howmanycyclesdoesittakeProgramPtoexecute,assumingthebranchisnot

taken?61clockcyclesc. Whichvalues(eg.MEM[$s0],branchaddress,Instruction[15:0],etc)arestoredintheA,B,ALUOut,andMDR

registersduringtheexecutioncycleofthefollowinginstruction:sw $t1, 0($a1)A: Reg[rs] = Reg[$a1] B: Reg[rt] = Reg[$t1] ALUOut:Reg[rs]+Instr[15:0]=Reg[$a1]+0MDR:Valuereadfrommemory(sinceMemRd=0,itisthevaluelasttimereadfromthememory),whichistheswinstructionitself.

Problem3:Multi‐cycledatapathInclasswecoveredtheMIPSmulti‐cycleimplementationalsowhichoperatesforthesamebasicsubsetofMIPSinstructionsasinthesingle‐cyclebasicimplementation.InthisproblemyouwillintroducefunctionalityforadditionalMIPSinstructions.UsetheMulti‐cyclehandoutpostedonPIAZZAtospecifyyourchanges.Inallcases,trytofindasolutionthatminimizesthenumberofclockcyclesrequiredforthenewinstruction.Additionalfunctionalunitscanbeadded(adder,ALU,SignExtension,Registers,etc),butonlywhenabsolutelynecessary.Explicitlystatehowmanycyclesittakestoexecutethenewinstructioninyourmodifiedfinitestatemachine.ModifythedatapathandthefinitestatemachinetoimplementthefollowinginstructionsINDEPENDANTLY:

a. Implement'addi'instruction Reg[rt]←Reg[rs]+immed[15:0];

#registerrsisaddedtoimmediatevalueintheinstructionandstoredinrt

b. Implement'jal'instruction.Reg[31]←PC+4#$raregisterstoresthereturnaddressPC←PC+4[31:28],(Instruction[25:0]<<2)

#PCisthetop4bitsofthePC+4valueconcatenatedwiththelowest26bitsofthejumpaddress#shiftedtheleftby2bits

c. Implementanew'wai'instruction.Theinstruction,wai rt,standsfor"whereami"andputstheinstructionaddressintoaregisterspecifiedbythertfield.(Immediateformat)

Reg[rt]←PC#$raregisterstoresthereturnaddress

d. Implement‘bne’if(Reg[rs]!=Reg[rt])PC←PC+4+Instruction[15:0]<<2

e. Implement‘beqi’(Assumethersfieldisa5‐bit2’scomplementvalue)

if(Reg[rt]==2’scomplementvalueinrsfield)PC←PC+4+Instruction[15:0]<<2

f. Implement‘bgtz’(Assumethertregisterissetto$0)

if(Reg[rs]>=0)PC←PC+4+Instruction[15:0]<<2

g. Implementanew'incbeq'instruction.Theinstruction,incbeq rs, rt, label,standsfor"incrementandbranchonequal".Incrementalwaysoccurs!

if(Reg[rs]==Reg[rt])PC←PC+4+Instruction[15:0]<<2Reg[rs]←Reg[rs]+4#theincrementalwaysoccurs

h. Implementanew'sneg'instruction.Theinstruction,sneg rs,standsfor"setonnegative”.(Immediate

format)if(Reg[rs]<0)Reg[rt]=1,elseReg[rt]←0

i. Implementanew‘lwdec’instructon.Theinstructionlwdec rs, offset(rt),loadsavalueand

decrementsthersvaluebyonememoryword.Reg[rt]←Mem[Reg[rs]+sign‐extendedoffset]Reg[rs]←Reg[rs]–4

j. Implementanew‘swr’instruction.Theinstructionswr rd, rt(rs),usesaregistervaluefortheoffsetwhencalculatingthememoryaddresstostoredatato.

Mem[Reg[rs]+Reg[rt]]=Reg[rd]

k. Implementanew‘slti’instruction.Theinstructionsetsslti rs, rt, immediatesetsthersregistertotheimmediatevalueifthevalueinregisterrsislessthanregisterrt.

if(Reg[rs]<Reg[rt])Reg[rs]←2’scomplementimmediatevalue

Problem4:Showhowthejumpregisterinstruction'jr'canbeimplementedtothemulti‐cycledatapathbysimplymakingchangestothefinitestatemachine.(Hint:$0=$zero=0)rt field of the instruction should be register $0, which always holds the value 0.

Problem5:CalculatethedelayinthedatapathaftertheadditionofALLinstructionsinProblem3.Assumethesamedelays.Whatistheminimumclockcycleperiodatwhichthisdesigncanoperateproperly?Theanswerwilldependonhowyouimplementedeachinstruction

Problem6:Considerchangestotheoriginalmulti‐cycledatapaththatalterstheregisterfilesothatithasonlyonereadport.Describeanychangesthatwillneedtobemadetothedatapathinordertosupportthismodification.Usethedatapathdiagramtoillustratethechanges.Modifythefinitestatemachinetoindicatehowtheinstructionswillworkgivenyournewdatapath.YouwillneedtoaddcontrollinestoWriteregistersAandBandamultiplexer(withacontrolline)toselectbetweentheRsandRtfieldsoftheinstruction.

State1ismodifiedwithselectRsandWriteAasserted.Anewstatehastobeaddedbeforestates6and8toselectRtandWriteB.Afterthenewstatecontrolbranchestoeitherstate6orstate8basedupontheop‐code.OtherstatesarenotaffectedasonR‐Formatandbranchinstructionuseinputfromtworegisters.Additionally,State2mustbemodifiedtoadditionallyreadtheRtregisterandstorethecontentsinB.While,lwdoesnotrequiretoreadRt,thestoreworddoes.BymakingthemodificationtoState2,wheretheRegisterfileisnotbeingused,wedonot

increasethenumberofclockcyclesrequiredforaswinstruction.ControlsignalstoselectRtandWriteBmustbespecified.

Problem7:Considereliminatingthetwoshiftleftby2unitsinthemulticycledatapath.Insteadoftheseunits,theALUwillbeusedforshiftingthevaluesinstead.Whatimpactdoesthishaveontheoriginal5instructions(lw,sw,R‐type,beq,j)?Iftheshiftleftby2iseliminated,thenanytimethishappenswillrequirethattheALUisused.First,sincetheDecodestageaddstheimmediatevalueshiftedleftby2tocalculatethebranchaddress,nowastageinbetweentheFetchandDecodestageswouldneedtobeaddedtodotheshiftingofthesignextendedvalue.ThevaluewouldbeinALUOutandtheinput3ofALUSrcBwouldneedtomodifiedtobethevaluedfromtheALUOutregister.ThesecondShiftleftunitisusedinstage9fortheJumpinstruction.Ifthiswasremoved,thedatapathwouldneedtogothroughtheALUandthePCSourcemuxcouldeliminateinput2,andusethevalueoutoftheALUinstead.Problem8:Inthesinglecycledatapathcontrolunitfortheoriginal5instructions(lw,sw,R‐type,beq,j),theMemtoRegcontrolsignalcanbeeliminatedandtheMemReadorALUSrccontrolsignalscanbeusedtocontrolthemultiplexorinstead.Thisreducesthenumberofcontrolsignalsrequired(lesslogicgatestoimplement).

a. Whichothersignalsinthesinglecycledatapathcanbeeliminatedandreplacedbyanotherexistingcontrolsignal,ortheinverse(NOT)ofthesignal.

RegDstandALUOp1RegDst&MemRead’Branch&AluOp0

b. Arethereanysignalsinthemulti‐cycledatapath(basic5instructionsonly)whichcanbeeliminatedand

replaced?

Yes,MemtoRegisonlyusedinStage4&7.ItcanbereplacedwithRegDst’(whichisalsoonlyusedinStage4&7)