View
227
Download
2
Category
Tags:
Preview:
Citation preview
1
EENG 2710 Chapter 6
Introduction to Sequential Logic
2
Chapter 6 Homework
Work on your project
3
Sequential Circuit
• A digital circuit whose output depends not only on the present combination of input, but also on the history of the circuit.
4
Sequential Circuit Elements
• Two basic types:– Latch– Flip-flop
• The difference is the condition under which the stored bit changes.
5
SR Latch• The LATCH is a sequential circuit with two
inputs (SET and RESET).• SET – an input that makes the device store a
logic 1.• RESET – an input that makes the device store a
logic 0.
6
SR Latch
• Two complementary outputs
• Outputs are always in opposite logic states.
7
Active HIGH or LOW Inputs
• Latches can have either active HIGH or active LOW inputs.
• The output of the LATCH, regardless of the input active level, is still defined as:
1 0, :RESET
0 , 1 :SET
8
Active HIGH or LOW Inputs
9
NAND Latch Function Table
RESET1001
1
1
0
1
1
No Change1
SET00
Forbidden10
Function1 t1t QQRS
tt QQ
10
NAND Latch Reset to Set Transition
11
NAND Latch Reset to Set Transition
12
NAND Latch Set to Reset Transition
13
NAND Latch Reset to Set Transition
14
NOR Latch Function Table
15
NOR Latch Reset to Set Transition
16
NOR Latch Reset to Set Transition
17
NOR Latch Set to Reset Transition
18
NOR Latch Set to Reset Transition
19
Switch Bounce
• The condition where the closure of a switch contact results in a mechanical bounce before the final contact is made.
• In logic circuits, switch bounce causes several pulses when a switch is closed.– Can cause circuit to behave unpredictably.
20
Switch Bounce
21
Switch Debounce Circuit
1 1, RS
22
Gated SR Latch
• The time when a latch is allowed to change state is regulated.• Change of state is regulated by a control signal called ENABLE.• Circuit is a NAND latch controlled by steering gates.
23
Latch ENABLE Input
EN S R Qt+1 Function
1 0 0 Qt No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 1 1 Forbidden
0 X X Qt Inhibited
24
Gated D or Transparent Latch
• A latch whose output follows its data input when its ENABLE input is active.
• When ENABLE is inactive, the latch stores the data that was present when ENABLE was last active.
25
Gated D Latch Function Table
26
Flip-Flop Definition
• A gated latch with a clock input.• The sequential circuit output changes when its CLOCK
input detects an edge.• Edge-sensitive instead of level-sensitive.• Positive edge: The transition from logic ‘0’ to logic ‘1’• Negative edge: The transition from logic ‘1’ to logic ‘0’• Symbol is a triangle on the CLK (clock) input of a flip-
flop.
27
Positive Edge-Triggered D Flip-Flop
28
Edge Detector
• A circuit that converts that active-edge of a CLOCK input into a brief active-level pulse.
• Created using gate propagation delays.• Can be positive or negative edge.• The inverter in a below has 3 to 10ns propagation delay
29
Operation of Positive Edge D Flip-flop
VHDL – D Latch
d_latch_vhdl.vhd
-- D latch with active-HIGH level-sensitive enable
ENTITY d_latch_vhdl IS
PORT(
d, ena : IN BIT;
q : OUT BIT);
END d_latch_vhdl;
30
VHDL – D Latch
ARCHITECTURE a OF d_latch_vhdl IS
BEGIN
PROCESS ( d, ena)
BEGIN
IF ( ena = ‘1’) THEN
q <= d;
END IF;
END PROCESS;
END a; 31
32
JK Flip-Flop
• Two inputs with no illegal input states.• With J and K both HIGH, the flip-flop toggles between
opposite logic states with each applied clock pulse.
33
Negative Edge-Triggered JK Flip-Flop
34
Toggle Action
35
Toggle Applications• Used to divide an input frequency in half.
• By cascading toggling flip-flops, a counter is created.
36
Synchronous And Asynchronous Circuits
• Synchronous circuits have sequential elements whose outputs change at the same time.
• Asynchronous circuits have sequential elements whose outputs change at different times.
37
Synchronous and Asynchronous Inputs
• Synchronous inputs of a flip-flop only affect the output on the active clock edge.
• Asynchronous inputs of a flip-flop change the output immediately.
• Asynchronous inputs override synchronous inputs.
38
3-Bit Synchronous Circuits
39
Flip-Flop Asynchronous Inputs
• Preset:– An asynchronous set function, usually
designated as
• Clear:– An asynchronous reset function, usually
designated as
• Both Preset and Clear usually have LOW input active levels.
PRE
CLR
40
Flip-Flop Asynchronous Inputs
41
3-Bit Synchronous Circuits With Asynchronous Reset
• An asynchronous input used to set a sequential circuit to a known initial state.
• Usually a RESET tied to the inputs of all flip-flops.• When activated, the output of the sequential circuit goes LOW.
CLR
42
Disadvantages of Asynchronous Circuits
• Difficult to analyze operations.
• Intermediate states that are not part of the desired design may be generated.
43
JK Flip-Flop Asynchronous Inputs Function Table
CLR
44
Unused Preset and Clear Inputs
• Disable by connecting to a logic HIGH (for active-LOW inputs).
• In Quartus II the asynchronous inputs of all flip-flop primitives are set to a default level of HIGH.
45
T (Toggle) Flip-Flop
• Output toggles on each applied clock pulse when a synchronous input is active.
• Synchronous input is designated as ‘T’.
T Flip-Flop Function Table
46
InhibitedQtX↓
InhibitedQtX1
InhibitedQtX0
Toggle1↑
No change0↑
FunctionQt+1TCLK
InhibitedQtX↓
InhibitedQtX1
InhibitedQtX0
Toggle1↑
No change0↑
FunctionQt+1TCLK
tQ
tQ
47
D Flip-Flop Configured for Toggle Function
Recommended