1. 2 Logic Circuits Sequential Circuits Combinational Circuits Consists of logic gates whose outputs...

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Logic CircuitsLogic Circuits

Sequential Sequential CircuitsCircuits

Combinational Combinational CircuitsCircuits

•Consists of logic gates whose outputs are determined from the current combination of inputs.

•Performs an operation that can be specified by a set of Boolean functions.

•Employ storage elements in addition to logic gates.

•Outputs are a function of the inputs and the state of the storage elements.

•Output depend on present value of input + past input.

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Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements

Latches Flip-flops

Sequential circuit analysis State tables State diagrams

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A Sequential circuit contains:Storage elements:

Latches or Flip-Flops Combinatorial Logic:

Implements a multiple-output switching function

Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State,

are signals from storage elements. The remaining outputs, Next State are

inputs to storage elements.

CombinationalLogic

Storage Elements

Inputs Outputs

StateNextState

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Sequential LogicOutput function

Outputs = g(Inputs, State)Next state function

Next State = f(Inputs, State)

Combina-tionalLogicStorage

Elements

Inputs Outputs

State

NextState

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Depends on the times at which: storage elements observe their inputs, and storage elements change their state

Synchronous Behavior defined from knowledge of its signals at discrete

instances of time Storage elements observe inputs and can change state

only in relation to a timing signal (clock pulses from a clock) Asynchronous

Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change

If clock just regarded as another input, all circuits are asynchronous!

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Storage elements Maintain a binary state (0 or 1) indefinitely as

long as power is delivered to the circuit Switch states (01 or 10) when directed by

an input signal Most basic storage element Used mainly to construct Flip-Flops Asynchronous storage circuit Types of latches:

SR LatchesS`R` LatchesD Latches

X = X

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Cross-coupling twoNOR gates gives theS – R Latch:

S (set)

R (reset)Q

Q

S R Q Q’ COMMENTS

0 0 ? ? Undefined state

1 0 1 0 Set

0 0 1 0 After S=1,R=0

0 1 0 1 Reset

0 0 0 1 After S=0,R=1

1 1 0 0 forbidden

0 0 ? ? Undefined state

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“Cross-Coupling” two NAND gates gives the S -R Latch:

QS (set)

R (reset) Q

S R Q Q’ COMMENTS

1 1 ? ? Undefined state

1 0 0 1 set

1 1 0 1 After S=1,R=0

0 1 1 0 reset

1 1 1 0 After S=0,R=1

0 0 1 1 forbidden

1 1 ? ? Undefined state

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Adding two NANDgates to the basicS - R NAND latchgives the clockedS – R latch:

Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.

C means “control” or “clock”.

S

R

Q

C

Q

1

1

S`

R`

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Adding an inverterto the S-R Latch,gives the D Latch:

Note that there areno “indeterminate”states! Q D Q(t+1) Comment

0 0 0 No change

0 1 1 Set Q

1 0 0 Clear Q

1 1 1 No Change

The graphic symbol for aD Latch is:

C

D Q

Q

DQ

C

Q

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C

D Q

QR

Q

QR

S Q

Q

S

SR S’R’ D

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Chapter 5: Sequential Circuits

5.4: Flip-Flops

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The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Other flip-flops

- JK flip-flop

- T flip-flop

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In a sequential circuit, paths may exist through combinational logic:From one storage element to anotherFrom a storage element back to the same storage

element The combinational logic between a latch output

and a latch input may be as simple as an interconnect

For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1

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Consider the following circuit:

Suppose that initially Y = 0.

As long as C = 1, the value of Y continues to change! The changes are based on the delay present on the

loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock pulse

ClockY

C

D Q

Q

Y

Clock

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A solution to the latch timing problem is to break the closed path from Y to Y within the storage element

The commonly-used, path-breaking solutions replace the clocked D-latch with:a master-slave flip-flopan edge-triggered flip-flop

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Consists of two clockedD latches in serieswith the clock on the second latch inverted

The input is observedby the first latch with C = 1

The output is changed by the second latch with C = 0 The path from input to output is broken by the

difference in clocking values (C = 1 and C = 0). The behavior demonstrated by the example with D

driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur.

C

D QCC

D QD

Master Slave

Y

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