© Digital Integrated Circuits 2nd Inverter Impact of Interconnect Interconnection Fundamental...

Impact of InterconnectImpact of Interconnect

Interconnection Fundamental limitation of Digital

Technology at all scales Classes of parasitics:

– Capacitive– Resistive– Inductive (Impact usually package/board level)

Interconnect Impact on ChipInterconnect Impact on Chip

10 100 1,000 10,000 100,000

Length (u)

Pentium Pro (R)

Pentium(R) II

Pentium (MMX)

Pentium (R)

Pentium (R) II

Nature of InterconnectNature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

INTERCONNECTINTERCONNECTCapacitanceCapacitance

Capacitance of Wire InterconnectCapacitance of Wire Interconnect

VDD VDD

Vin Vout

M4Cdb2

Fanout

Interconnect

VoutVin

CLSimplified

Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Dielectric

Substrate

Electrical-field lines

Current flow

LLCwire SSS

PermittivityPermittivity

Fringing CapacitanceFringing Capacitance

W - H/2H

Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])

Interwire CapacitanceInterwire Capacitance

fringing parallel

Impact of Interwire CapacitanceImpact of Interwire Capacitance

(from [Bakoglu89])

Wiring Capacitances (0.5 Wiring Capacitances (0.5 m CMOS)m CMOS)

Layer N+ P+ Poly Poly2 M1 M2 M3

Sub 420 730 87 -- 32 16 10 aF/m2

Ndif 2450 aF/m2

Pdif 2360 aF/m2

Poly 860 57 16 9 aF/m2

Poly2 52 aF/m2

M1 31 13 aF/m2

M2 32 aF/m2

Sub(fr) 310 250 76 59 39 aF/m

Poly(fr) 61 38 28 aF/m

M1(fr) 51 33 aF/m

M2(fr) 52 aF/m

INTERCONNECTINTERCONNECTResistanceResistance

Wire Resistance Wire Resistance

R = H W

Sheet ResistanceRo

Interconnect Resistance Interconnect Resistance

Polycide Gate MOSFETPolycide Gate MOSFET

PolySilicon

Silicide

Silicides: WSi 2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

Sheet ResistanceSheet Resistance

Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric

InterconnectInterconnectModelingModeling

The Lumped ModelThe Lumped Model

Driver

VinClumpe d

RdriverVout

The Lumped RC-ModelThe Lumped RC-ModelThe Elmore DelayThe Elmore Delay

The Ellmore DelayThe Ellmore DelayRC ChainRC Chain

Wire ModelWire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

The Distributed RC-lineThe Distributed RC-line

Step-response of RC wire as a Step-response of RC wire as a function of time and spacefunction of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

time (nsec)

x= L/10

x = L/4

x = L/2

RC-ModelsRC-Models

Driving an RC-lineDriving an RC-line

Rs Vo ut(rw,cw,L)

Design Rules of ThumbDesign Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> tpgate/0.38rc rc delays should only be considered when the

rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC when not met, the change in the signal is slower

than the propagation delay of the wire

Homework 4Homework 41. For the AMIS 0.5um technology, create an equivalent RC/Elmore SUE model

using the Mosis parametric test results (amis05.txt from web site). This model should include the effective gate capacitance, source and drain parasitic junction capacitances and equivalent resistance for NMOS and PMOS, L=0.5um as a function of W in um. Use this model to estimate the sizes of the transistors in the ring oscillator test for the standard and wide case from the given performance data. (Do this carefully, this is a useful model!!)

2. Rabaey Chap. 4 on-line problems: 1, 4, 7, 12

© Digital Integrated Circuits 2nd Inverter Impact of Interconnect Interconnection Fundamental...

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