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© Digital Integrated Circuits2nd Devices
DeviceDevice
Dr. Shiyan HuOffice: EERC 518shiyan@mtu.edu
Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
EE4271EE4271VLSI DesignVLSI Design
© Digital Integrated Circuits2nd Devices
Goal of this chapterGoal of this chapter
Present intuitive understanding of device operation
Introduction of basic device equations
© Digital Integrated Circuits2nd Devices
MOS Transistor Types and SymbolsMOS Transistor Types and SymbolsD
S
G
G
S
D
NMOS
PMOS
© Digital Integrated Circuits2nd Devices4
Circuit Under DesignCircuit Under Design
VDD VDD
VinVout
M1
M2
M3
M4
Vout2
© Digital Integrated Circuits2nd Devices
Circuit on the ChipCircuit on the ChipA transistor
© Digital Integrated Circuits2nd Devices
The MOS (Metal-Oxide-Semiconductor) The MOS (Metal-Oxide-Semiconductor) TransistorTransistor
Polysilicon Aluminum
© Digital Integrated Circuits2nd Devices
Simple View of A TransistorSimple View of A Transistor
VGS VT
RonS D
A Switch!
|VGS|
An MOS Transistor
© Digital Integrated Circuits2nd Devices
Silicon BasicsSilicon Basics Transistors are built on a silicon substrate Silicon forms crystal lattice with bonds to
four neighbors
© Digital Integrated Circuits2nd Devices
Doped SiliconDoped Silicon Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity
extra electrons (doped Borons) – n-type missing electrons (doped Arsenic/Phosphorus)
more holes) – p-type
n-type p-type
© Digital Integrated Circuits2nd Devices
NMOS TransistorNMOS Transistor
Diffusion
© Digital Integrated Circuits2nd Devices
NMOS - IINMOS - II Refer to gate, source, drain and bulk
voltages as Vg,Vs,Vd,Vb, respectively. Vab=Va-Vb Device is symmetric. Drain and source are
distinguished electrically, i.e., Vd>Vs. P regions have acceptor (Boron)
impurities, i.e., many holes. N regions have donor
(Arsenic/Phosphorus) impurities, i.e., many electrons.
N+ and P+ are heavily doped N and P regions, respectively.
© Digital Integrated Circuits2nd Devices
NMOS - IIINMOS - III Gate oxide are insulators, usually, silicon
dioxide. Gate voltage modulates current between
drain and source, how?
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Enhancement NMOSEnhancement NMOS
© Digital Integrated Circuits2nd Devices
Enhancement NMOS - IIEnhancement NMOS - II Does not conduct when Vgs=0, except that
there is leakage current. When Vgs is sufficiently large, electrons
are induced in the channel, i.e., the device conducts. This Vgs is called threshold voltage.
© Digital Integrated Circuits2nd Devices
Enhancement NMOS IIIEnhancement NMOS III
Positively Charged
Negatively Charged
© Digital Integrated Circuits2nd Devices
Enhancement NMOS - IVEnhancement NMOS - IV When Vgs is large enough, the upper part
of the channel changes to N-type due to enhancement of electrons in it. This is referred to as inversion, and the channel is called n-channel.
The voltage at which inversion occurs is called the Threshold Voltage (Vt).
A p-depletion layer have more holes than p-substrate since its electrons have been pushed into the inversion layer.
Does not conduct when Vgs<Vt (Cut-off).
© Digital Integrated Circuits2nd Devices
Enhancement NMOS VEnhancement NMOS V
© Digital Integrated Circuits2nd Devices
Enhancement NMOS - VIEnhancement NMOS - VI When Vgs>Vt, the inversion layer (n
channel) becomes thicker. The horizontal electrical field due to Vds
moves electrons from the source to the drain through the channel.
If Vds=0, the channel is formed but not conduct.
© Digital Integrated Circuits2nd Devices
Case when Vds=0Case when Vds=0
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Linear RegionLinear Region
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Linear Region - IILinear Region - II When Vgs>Vt and Vgd>Vt, the inversion
layer increases in thickness and conduction increases.
The reason is that there are non-zero inversion layer at both source and drain (our previous analysis works for both Vgs and Vgd).This is called linear region.
Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e., Vds<=Vgs-Vt
Vds>0 Ids depends on Vg, Vgs, Vds and Vt.
© Digital Integrated Circuits2nd Devices
Saturation RegionSaturation Region
© Digital Integrated Circuits2nd Devices
Saturation Region - IISaturation Region - II When Vgs>Vt and Vgd<Vt, we have non-
zero inversion layer at source but zero inversion layer at drain.
Inversion layer is said to be pinched off. This is called the saturation region.
Vgd<Vt means that Vgs-Vds<Vt, i.e., Vds>Vgs-Vt.
Electrons leaves the channel and moves to drain terminal through depletion region.
© Digital Integrated Circuits2nd Devices
Saturation Region - IIISaturation Region - III In saturation region, the voltage difference
over the channel remains at Vgs-Vt. This is because if Vds=Vgs-Vt, the inversion layer is barely pinched off at the drain (since then Vgd=Vt). If Vds>Vgs-Vt, the channel is pinched off somewhere between the drain and source ends. Thus, the voltage applied across the channel is Vgs-Vt.
As a result, Ids depends on Vgs in this region, so we cannot keep raising Vds to get better conduction.
© Digital Integrated Circuits2nd Devices
SummarySummary Three regions of conduction
Cut-off: 0<Vgs<Vt Linear: 0<Vds<Vgs-Vt Saturation: 0<Vgs-Vt<Vds
Vt depends on gate and insulator materials, thickness of insulators and so forth – process dependant factors, and Vsb and temperature – operational factors.
© Digital Integrated Circuits2nd Devices
Analysis (for linear region)Analysis (for linear region)
n+n+
p-substrate
D
SG
B
VGS
xL
V(x) +–
VDS
ID
MOS transistor and its bias conditions
© Digital Integrated Circuits2nd Devices
Analysis - IIAnalysis - II Denote by V(x) the voltage at a point x
along the channel. The gate-to-point voltage is Vgs-V(x). Since it needs to be > Vt for every point along the channel, the charge per unit cross section area at x is
Cox is the capacitance per unit, which is
where is a constant called the permittivity of the gate oxide and tox is the thickness of gate oxide.
© Digital Integrated Circuits2nd Devices
Analysis - IIIAnalysis - III Gate width W, so the total charge is QW. I=QW/t=QWv, v being velocity of carrier. Given surface mobility of electrons,
which depends on process, an empirical formula for v is
We have Integrate x from 0 to L, we have
For saturation region, replace Vds by Vgs-Vt, we have . It does not depend on Vds.
1
W1
QI
© Digital Integrated Circuits2nd Devices
Effective Channel Length/WidthEffective Channel Length/Width
is due to lateral diffusion of the source and drain junctions under the gate
© Digital Integrated Circuits2nd Devices
Summary - IISummary - II
Three regions of conduction Cut-off: 0<Vgs<Vt, I=0 Linear: 0<Vds<Vgs-Vt,
Saturation: 0<Vgs-Vt<Vds
© Digital Integrated Circuits2nd Devices
PMOSPMOS
© Digital Integrated Circuits2nd Devices
PMOS - IIPMOS - II Dual of NMOS Three regions of conduction
Cut-off: 0>Vgs>Vt Linear: 0>Vds>Vgs-Vt Saturation: 0>Vgs-Vt>Vds
Current computation is the same as NMOS except that the polarities of all voltages and currents are reversed.
Mobility in PMOS is usually half of the mobility in NMOS due to process technology.
© Digital Integrated Circuits2nd Devices
I-V characteristics (different Vt)I-V characteristics (different Vt)
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I-V Characteristics III-V Characteristics II
© Digital Integrated Circuits2nd Devices
Short Channel EffectsShort Channel Effects The discussion is true for long channel. The depletion layer/electron move under
the gate is assumed to be caused entirely by vertical field, i.e.,
Near source and drain, there is also depleted region due to horizontal electrical field (Vd,Vs). Thus, the region below gate is already partially depleted.
Device actually conducts with smaller Vt. If the channel is very short, effect is
significant, which make the device hard to control.
In practice, L>= Lmin.
© Digital Integrated Circuits2nd Devices
Short Channel Effect - IIShort Channel Effect - II
© Digital Integrated Circuits2nd Devices
Sub-threshold conduction (Leakage)Sub-threshold conduction (Leakage)
Vgs<Vt, cut-off and I=0. Not true. In practice, for Vgs<Vt,
I is exponentially dependent on Vgs. Id0 and n are experimentally determined, k is Boltzmann’s constant and T is temperature.
Source of standby power consumption in portable devices.
Some extremely low-power circuits use sub-threshold conduction, e.g., digital watch.
© Digital Integrated Circuits2nd Devices
Transistor Equivalent ResistanceTransistor Equivalent Resistance In linear region, R=V/I, so
In saturation region, the voltage applied across the channel is Vgs-Vt. Thus,
Roughly speaking, channel resistance inversely depends on W since
© Digital Integrated Circuits2nd Devices
Transistor Resistance - IITransistor Resistance - II Larger gate width (larger gate area) ->
smaller resistance -> device runs faster This means that power/area increases with
delay decreases. A lot of power-delay tradeoff like this.
© Digital Integrated Circuits2nd Devices
Transistor CapacitanceTransistor Capacitance
DS
G
B
CGDCGS
CSB CDBCGB
Gate Capacitance = Channel Capacitance + Overlap Capacitance
© Digital Integrated Circuits2nd Devices
Overlap CapacitanceOverlap Capacitance
tox
n+ n+
Cross section
L
Gate oxide
xd xd
L d
Polysilicon gate
Top view
Source
n+
Drain
n+W
Overlap capacitance=2Cox Xd W
© Digital Integrated Circuits2nd Devices
Channel CapacitanceChannel Capacitance
S D
G
CGCS D
G
CGCS D
G
CGC
Cut-off Resistive Saturation
Larger gate width -> Larger capacitance
© Digital Integrated Circuits2nd Devices
Measuring the Gate CapMeasuring the Gate Cap
2 1.52 12 0.5 0
3
4
5
6
7
8
9
103 102 16
2
VGS (V)
VGS
Gate
Ca
paci
tan
ce (
F)
0.5 1 1.5 22 2
I
i=CdV/dt, so C=idt/dV
© Digital Integrated Circuits2nd Devices
In Standard Cell LibraryIn Standard Cell Library A gate type has multiple gate sizes (widths) Larger gate width means larger gate capacitance and
smaller driving resistance. Thus, for a gate type, we have a variety of transistors
with different capacitance and resistance tradeoff. Larger width means larger capacitance and thus
larger power due to charging and uncharging the capacitance.
Usually, larger width transistor has smaller delay.
© Digital Integrated Circuits2nd Devices
Technology ScalingTechnology Scaling Devices scale to smaller dimensions with advancing technology. A scaling factor S describes the ratio of dimension between the
old technology and the new technology. In practice, S=1.2-1.5.
© Digital Integrated Circuits2nd Devices
Technology Scaling - IITechnology Scaling - II In practice, it is not feasible to scale voltage since different ICs in
the system may have different Vdd. This may require extremely complex additional circuits. We can only allow very few different levels of Vdd.
In technology scaling, we often have fixed voltage scaling model. W,L,tox scales down by 1/S Vdd, Vt unchanged Area scales down by 1/S2
Cox scales up by S due to tox Gate capacitance = CoxWL scales down by 1/S scales up by S
Linear and saturation region current scales up by S Current density scales up by S3
P=Vdd*I, power density scales up by S3
Power consumption is a major design issue
© Digital Integrated Circuits2nd Devices
SummarySummary NMOS
Cut-Off, Linear and Saturation Regions How to compute I sub-threshold conduction
PMOS is the dual device of NMOS I-V characteristics of MOS transistors
Resistance Capacitance
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