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chiportal documents
Technology
Cost Effective centralized adpative routing for networks on chip
Technology
Contemporary Design of High ADC
Technology
Living with "Moore" & Designing the Ultimate SoC
Technology
Software Parallelisation & Platform Generation for Heterogeneous Multicore Architectures
Technology
Designing at 2x nanometers Some New Problems Appear & Some Old Ones Remain
Technology
Challenges in mixed signal
Technology
Scheduler performance in manycore architecture
Business
TRACK A: High Performance Integrated Power Management Platforms for LED lighting Control & Other Applications
Technology
TRACK F: FPGA Prototypes and Emulators – a Symbiotic Approach/ Ilan Harel
Technology
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
Technology
TRACK D: A breakthrough in logic design drastically improving performances from 65/55nm and below/ Ilan sever
Business
Mentor graphics minimizing customer returns - new
Technology
TRACK H: Formal metric driven verification/ Raik Brinkmann
Technology
Evm Test Impairements
Technology
TRACK C: A new method for automatic generation of DRC and LVS runsets/ Dr. Elena Ravve
Technology
TRACK F: OpenCL for ALTERA FPGAs, Accelerating performance and design productivity/ Liad Weinberger
Technology
TRACK G: Adaptive IP Delivers Higher Performance / Higher Reliability Systems/ Uniqufy
Documents
TRACK H: On-the-fly design exploration framework for simulation/ lior Altman
Business
TRACK E: Introduction to Analog Ultra Low Power (AULP) design/ Tuvia Liran
Technology
TRACK D: Challenges of Giant Silicons in Advanced Process Technology Node/ Sorel Horovitz
Technology
TRACK B: The new standard for Computer On Modules (COM) based on ARM architecture/ Dov Shalev
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