Xtw01t2v012011 sys tech

IBM Systems & Technology Group Education & Sales Enablement © 2010 IBM Corporation

Systems Technologies

XTW01 Topic 2


Course Objectives

Upon completion of this module you will be familiar with:

>The buses found in System x servers

>The memory technologies used in System x servers

>The processors employed in System x servers

>The disk technologies used in System x servers

>The network technologies used in System x servers.


Agenda

>* System Buses *

>Memory

>Processors

>Disk Subsystems

>Networking


System Buses - Introduction

>What is a Bus?

>A little history

>Constraints on bus design

>PCI

>PCI Express

> Interconnects

>Scalable Memory Interconnects


Agenda

>System Buses

>* Memory *

>Processors

>Disk Subsystems

>Networking


Memory - Introduction

>How it all works

>DIMM Architecture

>Processor point of view

>RAS

>Population “Rules”

>Flash


Agenda

>System Buses

>Memory

>* Processors *

>Disk Subsystems

>Networking


Processors - Introduction

>What’s in the box?


99

Intel® Celeron® G1100 Series Processor

Processors - Intel Celeron G (1 of 2)

>Two Dies One Substrate

CPU Die 32nm lithography

- Two Cores

- 256K L2 Cache per Core

- Shared 2MB L3 Cache

- QuickPath Interconnect toGPU Die

GPU Die 45nm lithography

- 2 Channel DDR3 Memory Controller

2 UDIMMs per channel

NO ECC Support *

- Video

- PCI Express x16 lanes

- DMI x4 to ChipSet



- Two Cores





- 2 Channel DDR3 Memory Controller


NO ECC Support *

- Video


- DMI x4 to ChipSet

* ECC functionality when paired with 3240 PCH* ECC functionality when paired with 3240 PCH


Processors - Intel Celeron G (2 of 2)


> Intel® Virtualization Technology (VT-x)

> Intel® 64

> Idle States

>Enhanced Intel SpeedStep® Technology

>Execute Disable Bit



> Intel® 64

> Idle States




1111

Intel® Pentium® G6900 Series Processor

Processors - Intel Pentium G (1 of 2)



- Two Cores





- 2 Channel DDR3 Memory Controller 1066 MT/s


NO ECC support *

- Video


- DMI x4 to ChipSet



- Two Cores





- 2 Channel DDR3 Memory Controller 1066 MT/s


NO ECC support *

- Video


- DMI x4 to ChipSet



Processors - Intel Pentium G (2 of 2)



> Intel® 64

> Idle States





> Intel® 64

> Idle States




1313

Intel® Core i3 500 Series Processor

Processors - Intel Core i3 (1 of 2)



- Two Cores





- 2 Channel DDR3 Memory Controller1333 MT/s


No ECC support*

- Video


- DMI x4 to ChipSet



- Two Cores





- 2 Channel DDR3 Memory Controller1333 MT/s


No ECC support*

- Video


- DMI x4 to ChipSet



Processors - Intel Core i3 (2 of 2)


> Intel® Hyper-Threading Technology


> Intel® 64

> Idle States






> Intel® 64

> Idle States




1515

Intel® Xeon® 3400 Series Processor

Processors - Intel Xeon 3000 Series (1 of 2)

>45nm lithography

>Four Cores

>256K L2 Cache per Core

>Shared 8MB L3 Cache

>2 Channel DDR3 Memory Controller

3 RDIMMs or 2 UDIMMsper channel

ECC support

>PCI Express x16 lanes

>DMI x4 to ChipSet

>45nm lithography

>Four Cores

>256K L2 Cache per Core

>Shared 8MB L3 Cache

>2 Channel DDR3 Memory Controller

3 RDIMMs or 2 UDIMMsper channel

ECC support

>PCI Express x16 lanes

>DMI x4 to ChipSet


Processors - Intel Xeon 3000 Series (2 of 2)


> Intel® Turbo Boost Technology



> Intel® Virtualization Technology for Directed I/O (VT-d)

> Intel® Trusted Execution Technology

> Intel® 64

> Idle States


> Intel® Demand Based Switching



> Intel® Turbo Boost Technology



> Intel® Virtualization Technology for Directed I/O (VT-d)

> Intel® Trusted Execution Technology

> Intel® 64

> Idle States


> Intel® Demand Based Switching



>5500 Nehalem-EP Microarchitecture 45nm

>5500 Dual or Quad Core Processor on die

>5600 Westmere-EP Microarchitecture 32nm

>5600 Quad or Six Core Processor on die

> Integrated three channel DDR3 memory controller

800 / 1066 / 1333 MT/s

> Intel QuickPath Technology

> Intel Turbo Boost Technology

> Intel Hyper-Threading Technology

> Intel Intelligent Power Technology

>Three cache levels: 32 KB of L1 data cache per core

32 KB of L1 instruction cache per core

256 KB L2 cache per core

5500 Shared 4 or 8MB L3 cache

5600 Shared 12MB L3 cache

Processors - Intel Xeon 5000 Series


Processors - AMD Opteron 6100 SeriesAMD Opteron 6100 Series Key Features: >Eight or twelve cores / 2 - 45nm dies / 1 substrate>Speeds to 2.8GHz>New Socket (G34) 1974 pins / lands>Balanced SmartCache

64KB ECC protected L1 data cache per core 64KB parity protected L1 Instruction cache per core 512KB ECC protected L2 cache per core 2 - 6MB ECC protected L3 cache shared between cores

> Integrated memory controller Four memory channels Supports DDR3 ECC SDRAM at speeds up to 1333 MT/s (667 MHz) Supports up to 12 RDIMMS / 8 UDIMMS Supports Memory Sparing

>Four 6.4 GT/s HyperTransport 3.1 links HT Assist

>AMD Virtualization™ (AMD-V™)>AMD-P Suite>C1E Power State>AMD Cool Speed technology>Advanced Platform Management Link (APML)>AMD CoolCore™>AMD Smart Fetch> Independent Dynamic Core>Dual Dynamic Power Management™ (DDPM™)>AMD PowerCap Manager


Processors - Intel Xeon 6500 / 7500 Series

1919

>Nehalem EX 45nm architecture

>Four, Six or Eight Core Processors on die

>Two Integrated memory controllers

Two SMI ports

up to 1066 MT/s

> Intel QuickPath Technology

4 links

4.8, 5.86, or 6.4GT/s

> Intel Turbo Boost Technology

> Intel Hyper-Threading Technology

> Intel Intelligent Power Technology

>Three cache levels: 32 KB of L1 data cache per core

32 KB of L1 instruction cache per core

256 KB L2 cache per core

Shared 12, 18, or 24MB L3 cache


Agenda

>System Buses

>Memory

>Processors

>* Disk Subsystems *

>Networking


Disk Subsystems - Introduction

>SATA

>SAS

>RAID


Agenda

>System Buses

>Memory

>Processors

>Disk Subsystems

>* Networking *


Networking - Introduction

>Content under development


Summary

>Having completed this course module you should:

Have a firm understanding of the various system buses and interconnects and the role they play in server architecture.

Have a clear understanding of memory architecture, the reasoning for and need to follow certain population rules when adding memory.

Be familiar with the various processors offered with IBM System x Servers. Understand the disk subsystems used in servers today.


Glossary (1 of 3)

>AMD American Micro Devices>ASIC Application Specific Integrated Circuit>AT Advanced Technology>ATA Advanced Technology Attachment>BA Bank Address>BIOS Basic Input and Output>BL Bit Line>CAD Command Address Data>CAS Column Address Strobe>CKE Clock Enable>CL CAS Latency>CPU Central Processing Unit>CS Chip Select>DDR Double Data Rate>DIMM Dual Inline Memory Module>DMA Direct Memory Access>DQ Data Q>DQM Data Q Mask>DRAM Dynamic Random Access Memory>ECC Error Correcting Code>Ex5 Enhanced System X Architecture 5>EXA Enhanced System X Architecture>HBA Host Bus Adapter >HI-Z High Impedance


Glossary (2 of 3)

> I/O Input / Output> I2C Inter Integrated Circuit bus> IBM International Business Machines> LPC Low Pin Count> LUN Logical Unit Number> MAX5 Memory > MCA Micro Channel Architecture> MITS Micro Instrumentation and Telemetry Systems> MTBF Mean Time Between Failure> NAND Not AND> NEAT New Enhanced AT> NOR Not OR> NOT> PC Personal Computer> PCB Printed Circuit Board> PCI Peripheral Component Interconnect> PCI-X Peripheral Component Interconnect Extended> PHY Physical> PS/2 Personal System 2> QPI Quick Path Interconnect> RAID Redundant Array of Inexpensive Disks> RAM Random Access Memory> RAS Row Address Strobe> RDIMM Registered Dual Inline Memory Module


Glossary (3 of 3)

> RPM Revolutions Per Minute> SAS Serial Attached SCSI> SATA Serial Advanced Technology Attachment> SCSI Small Computer Systems Interface> SDRAM Synchronous Dynamic Random Access Memory> SEMP Storage Enclosure Management Processor> SEP Storage Enclosure Processor > SMB Scalable Memory Buffer> SMBus Systems Management Bus> SMI Symmetrical Memory Interface> SMP Symmetrical Multi Processor> SMP Serial Management Protocol> SPD Serial Presence Detect> SSP SAS Management Protocol> STP Serial ATA Tunneling Protocol> UDIMM Unbuffered Dual Inline Memory Module> UEFI Unified Extensible Firmware Interface> VLSI Very Large Scale Integration> WL Word Line> XOR Exclusive OR


End of Presentation