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SSRLabs Energy- and Instruction-Efficient HPC August 2013 © 2013 Scalable Systems Research Labs, Inc. Axel Kloth, President & CEO

SSRLabs Podcast: Energy- and Instruction-Efficient HPC

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  • SSRLabsEnergy- and Instruction-Efficient HPC

    August 2013 2013 Scalable Systems Research Labs, Inc.

    Axel Kloth, President & CEO

  • August 2013SSRLabs Overview

    2

    The Big Data Challenge

    Achieve accuracy and speed goals

    Solve the (power = heat) problem

  • August 2013 SSRLabs Overview 3

    Efficiency is the Benchmark

  • August 2013SSRLabs Overview

    4

    The Big Data Solution

    Achieve accuracy and speed goals

    Solve (power = heat) problem

    De-couple system management and transaction or numerically intensive

    operations CPU and Coprocessor/Accelerator Approach

  • August 2013SSRLabs Overview

    5

    SSRLabs

    z Addresses Big Data challenge using coprocessors and APIs to optimize performance and efficiency of both high-transaction count and numerically intensive applications

    z Developing a novel MPP architecture that is easier to program and takes less energy to execute tasks than traditional processors

  • August 2013SSRLabs Overview

    6

    pScale Product Attributes

    z Instruction- and energy-efficient neural network and floating-point coprocessors

    z Concurrent improvements in per-core performance, number of cores and efficient intra-core communications with reduced latency for better system performance

    z Platform agnostic

  • August 2013SSRLabs Overview

    7

    pScale Coprocessor Schematic

  • Coprocessor Implementation

    August 2013 SSRLabs Overview 8

    z pScale Floating-Point or Neural Net Coprocessor

    z Massively Parallel Processor with 64-bit cores

    z HMC DRAM

  • System Implementation

    August 2013 SSRLabs Overview 9

  • August 2013SSRLabs Overview

    10

    Development Status

    z Core IP and ASIC building blocks in-house for pScale coprocessor design

    z Raising A Round financing for product design/ engineering

    z Will market coprocessors/cards and license building blocks/IP for secondary revenue stream

  • August 2103SSRLabs Overview

    11

    Summary

    z Hyperscale and micro server markets share common performance vs. efficiency challengesz $2B annual market opportunity for SSRLabs

    z Design approach confirmed by Technology Advisory Board brings simplicity to MPP deployment

    z Current disruption in server CPU choice validates market readiness to change

  • August 2013 SSRLabs Overview 12

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