New Development New Development in in

Nitride Storage DevicesNitride Storage Devices

Rich Liu

Emerging Central LabMacronix International Co., Ltd.

NBitNBit / NROM and Beyond/ NROM and Beyond

Despite the challenges that come with the use of BTBT HH for erasing, NBit/NROM has been successful in delivering 2-bit/cell high density parts.

Even 4-bit/cell high density parts are feasible.

However, this success is only the beginning.

Beyond conventional NBit/NROM:PHINES – high programming/erase speed for both code and data FlashP-poly device – (almost) infinite enduranceP-poly device with CHISEL – high programming/erase speed

Introduction to Introduction to NBitNBit / NROM Device (1):/ NROM Device (1):Program and EraseProgram and Erase

Source = 0 V Drain= +5 VP-sub=0 V

n+n+

OX

OX

SIN

Gate = +10 V

N+-poly

Channel Hot Electron (CHE) Injection

Source = 0 V Drain = +5 VP-sub=0 V

n+n+

OX

OX

SIN

Gate = - 5 V

N+-poly

Band-To-Band Tunneling Induced Hot-Hole Injection (BTBTHH)

Programming Method Erasing Method

Deep depletion

Introduction to Introduction to NBitNBit / NROM Device (2): / NROM Device (2): ReadRead

Source=0 V

Drain=1.6 V

P-sub=0 Vn+n+

OX

OX

SIN

Gate= +3 V

N+-poly

Reverse Read Method

Y position (um)0.00 0.05 0.10 0.15 0.20 0.25 0.30

Sur

face

pot

entia

l, -ϕ

s (V

)-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

VD=0VD=0.4VD=0.8VD=1.2VD=1.6VD=2.0

Drain side

VG=1, NA=5E17, Le=600 A, Nt=6E12

Vbi+VD

-2ψB

Depletion region extends due to the drain voltage

The local potential barrier induced by the injected electrons can be shielded by the drain voltage (DIBL). Reverse read is a local DIBL effect.

Challenges (1):Challenges (1):The Mismatch of Electron and Hole InjectionsThe Mismatch of Electron and Hole Injections

GateGate

P-sub

n+n+OX

OX

SIN

N+-poly

P-sub

n+n+OX

OX

SIN

N+-poly

After P/E Cycling

Electron and hole accumulation

Injection Point Mismatch

Challenges (2):Challenges (2):Retention Properties after CyclingRetention Properties after Cycling

Model A Model B

P-sub

n+n+OX

OX

SIN

Gate

N+-poly

Hole Lateral movement during baking

P-sub

n+n+OX

OX

SIN

Gate

N+-poly

Hole-assisted electron de-trapping

Excess hole traps cause retention challenges!

Challenges (3):Challenges (3):HardHard--toto--Erase and OverErase and Over--EraseErase

Hard-to-Erase Over-EraseGate Gate

P-sub

n+n+OX

OX

SIN

N+-poly

P-sub

n+n+OX

OX

SIN

N+-poly

For a short channel device, the excess hole traps may lower the Vt below the EV level.

A small amount of electrons accumulate above the channel center, unreachable by the BTBT hot-hole erase.

Engineering SolutionsEngineering Solutions

Profiles of electrons and holes do not match: Improve interface propertiesParts qualified

Data retention loss due to hole-mismatch or hole-assisted tunneling:

Improve interface propertiesParts qualified

Hard-to-erase and over-erase:Clever algorithms and circuit designsParts qualified

New Solutions to Nitride Storage Device ChallengesNew Solutions to Nitride Storage Device ChallengesProfiles of electrons and holes do not match:

Find a less localized way to erase.Fowler-Nordheim (-FN) erase.

Data retention loss due to hole-mismatch or hole-assisted tunneling:

Find a way that does not use hole for erase, orFind a way to eliminate excess holes

Fowler-Nordheim (-FN) erase.

Hard-to-erase and over-erase:Find a way to eliminate electrons from channel center;Find a way to neutralize holes from channel edge.

Fowler-Nordheim (-FN) erase.

However, there is a problem!-FN erase is too slow (~ 1 sec).

Under –FN, dynamic balance is reached between gate injection (J2) and electron de-trapping (J1)

balance point determines the final Vt.

Poly work function determines the final Vt p-poly device.

-FN dynamics

Source=0V Drain=0VP-sub=0V

n+n+OX

OX

SIN

Gate= -21 V

Gate injection

Electron de-trapping

J2

J1

Time (sec)10-6 10-5 10-4 10-3 10-2 10-1 100 101

V t (V

)

01234567

VG= -18 VVG= -19 VVG= -20 V

VG= -18 VVG= -19 VVG= -20 V

N+ gate

P+ gate

The Concept of The Concept of ––FN Erase: Dynamic BalanceFN Erase: Dynamic Balance

-FN reset time (sec)10-6 10-5 10-4 10-3 10-2 10-1 100 101

V t (V)

1

2

3

4

5

6VG=-20V

No matter what is the initial Vt, after –FN RESET the final Vt is always the dynamic balance point –self-converging Vt.

SelfSelf--Converging Characteristics of Converging Characteristics of ––FN FN

How How ––FN Eliminates Excess ChargesFN Eliminates Excess Charges

Source=0V Drain=0VP-sub=0V

n+n+OX

OX

SIN

Gate= - 21 VGate injection

Electron de-trapping

-FN dynamics

J2

J1

Source=0V Drain=0VP-sub=0V

n+n+OX

OX

SIN

Gate= - 21 V

-FN erase after CHE or Hot-hole injection

CHE injected electrons

Hole traps

The RESET/ERASE state Vt is the dynamic balance of the gate injection (J2) and electron de-trapping (J1).

Erase – Excess electrons by CHE are expelled out of nitride by –FN operation and the device can be restored to the erased state.

Anneal – Excess holes in the nitride after P/E cycling are compensated by the gate injected electrons.

No matter what is the initial state, the final state is the RESET state Vt.

Use PUse P––FN to Improve Endurance and RetentionFN to Improve Endurance and RetentionUse –FN periodically to

improve reliability (P-FN)

Period ~ 1,000 P/E cycles

Device operates in high Vt state

Use p+ poly lowers the Vt

Fresh device

-FN reset, Vt = RV

CHE Program, Vt > PV

BTBT- HH Erase, Vt < EV

Conditionsvalid for –FN

reset

-FN reset, Vt = RV

NO

Yes

Biases Prog. Erase Reset

-3V -10V

10V

10V

10V

5V

VS 0V 0V 1.6V

0V

Read

VG 10V 4.2V

VD 5V 0V

VB 0V 0V

PP––FN Improves Endurance and Retention GreatlyFN Improves Endurance and Retention Greatly

P/E cycles100 101 102 103 104 105 106

V t (V

)

3.5

4.0

4.5

5.0

5.5

Program Bit-1, read Bit-1Program Bit-1, read Bit-2Program Bit-2, read Bit-1Program Bit-2, read Bit-2Erase Bit-1

PV=5.2V

EV=3.7V

P/E Cycles

100 101 102 103 104 105 106 107

V t (V

)

3.0

3.5

4.0

4.5

5.0

5.5

6.0Programm stateErase state

PV

EV

Fixed P/E pulses

Adjustable P/E pulses

1 bit/cell performanceUp to 10M cyclesVt window 1.1V after 10M cycles

2 bits/cell performanceUp to 1M, Vt window 0.9V 400mV 2nd bit effect after 1M cycles.

Highest endurance Highest endurance cycle ever reported !!!cycle ever reported !!!

Soft Soft ––FN Erase: A Path to Higher PerformanceFN Erase: A Path to Higher Performance-FN erase is slow

Takes ~ 1 second.Can only be used periodically.

There is another way:Hard sector erase (by BTBT HH) firstSoft –FN erase for a short time (50ms)For the entire sector

Soft erase eliminates hard-to-erase electrons/holesCHISEL can be used for programmingCHISEL is more efficient than CHE

High programming speed > 2MB/s.

(CHISEL = Channel Induced Secondary Electron)

The Soft Erase MethodThe Soft Erase MethodErase Start (N=0)

Hot-Hole Erase

Sector Verify?

Soft Erase 50 msec -FNVG= -21 V, VD/VS/VB=0 V

Erase Done

N=N+1

Pass Pre-EV level

EV level

The algorithm of this “soft erase”method resembles that for the “soft program”technique in floating gate devices.

Implementation in circuits is straight forward.

Key = do not brutal force = be smart.

Use BTBT HH to do most of the erase work.

Use –FN only for repairing the damage.

CHISEL ProgrammingCHISEL Programming

CHISEL faster programming speed with lower power consumption (body effect decreases the channel current)

Increased programming throughput

The second bit effect is slightly larger than CHE injection.

Programming Time (usec)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Del

ta V

T of

1st

bit

(V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VG=11, VD=4.8, Vb=0

VG=11, Vd=4.8, Vb=-1

VG=11, Vd=4.8, Vb=-2

VG=11, Vd=4.8, Vb=-3

VG=11, Vd=4.3, Vb=-3

Delta VT (1st Bit)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Del

ta V

T (2

nd B

it)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

VG=11, Vd=4.8, Vb=0VG=11, Vd=4.8, Vb=-1VG=11, Vd=4.8, Vb=-2VG=11, Vd=4.8, Vb=-3VG=11, Vd=4.3, Vb=-3

P/E Cycling of CHISEL Programmed CellsP/E Cycling of CHISEL Programmed Cells

P/E Cycle Numbers100 101 102 103 104 105

VT

(V)

3.5

4.0

4.5

5.0

5.5

Program 1st Bit, read 1st bitProgram 1st Bit, read 2nd bitProgram 2nd Bit, read 1st bitProgram 2nd Bit, read 2nd bitErase, read 1st bitErase, read 2nd bit

Program 1st bit condition:VG/VD/VS/VB=11.5/5/0/-2.5, 0.1 us

Hot-hole Erase:VG/VD/VS/VB= -1.8/6/0/0, 1 msVG/VD/VS/VB= -1.8/0/6/0, 1 msSoft Erase:VG= -21 V, 50 msec

Program 2nd bit condition:VG/VD/VS/VB=11.5/0/5.5/-2.5, 0.1 us

P/E Cycle Number100 101 102 103 104

V T (V

)

3.43.63.84.04.24.44.64.85.05.25.45.65.86.0

Program 1st bit, read 1st bitProgram1st bit, read 2nd bitProgram 2nd bit, read 1st bitProgram 2nd bit, read 2nd bitErase, read 1st bitErase, read 2nd bit

CHISEL Programming:1st bit: VG/VD/VS/VB=11.5/5/0/-2.5, 0.1 us2nd bit: VG/VD/VS/VB=11.5/0/5.5/-2.5, 0.1 us

Hot-Hole Erase:1st bit: VG/VD/VS/VB= -1.8/6/0/0, 1 ms2nd bit: VG/VD/VS/VB= -1.8/0/6/0, 1 ms

With 50 msec soft erase after hot-hole erase Without soft erase after hot-hole erase

Only one-shot program and one-shot erase were used during P/E cycles without any P/E verify and stepping algorithm.

CHISEL programming without soft erase has severe erase degradation (hard-to-erase) in less than 100 cycles.

Soft erase greatly reduces the hard-to-erase. CHISEL must be used with soft erase.

Mixed Mode Flash MemoryMixed Mode Flash Memory

NAND Flash:

FN program, FN erase – requires small current

Can program large sector simultaneously

High program speed

Suitable for data.

No random access – unsuitable for code.X

NOR Flash:CHE program, FN erase – requires large current

Slow programming – not suitable for data

Random access – suitable for code.X

Mixed mode NROM

High speed

Random Access

PHINESPHINES

Channel FN RESET

+ FN

BTBTHH program

(2-bits/cell)

+ FN

Channel FN RESET

(Erase)

PHINES (Program by Hole Injection Nitride Electron Storage) FN reset, BTBTHH program, FN erase – all small current

Fast programming – suitable for data.

Random access – suitable for code.

Two-bits/cell – high density.No hard-to-erase, no over-erase – good endurance.

Combines the benefits of NAND & NOR.

SummarySummaryNBit/NROM is a low-cost, high-density, 2-bit/cell technology.Using engineering solutions, NBit/NROM delivers its promises.

Beyond NBit/NROMPHINES shows promise for mixed mode Flash (both code and data).

–FN and P-poly devices are also promising:Use –FN periodically (1,000 P/E cycles) gives excellent endurance and data retention.Soft erase (a short –FN) after the sector erase also worksUsing soft-erase, we can improve the programming speed – both code and data Flash.

NBit/NROM’s success is only the beginning.

NBitNBit / NROM Scalability (I)/ NROM Scalability (I)Left and right bits merge

Charge distribution is ~ 20-30 nmDoes this imply scaling is impossible below 60nm?However, this is not the issue

Information is still retrievable even after the left and right bits start to merge.

Scalable to < 40 nm (corresponding to < 30nm technology node).

Reverse read – long channel device

Reverse read – Short channel device

NBitNBit / NROM Scalability (II)/ NROM Scalability (II)Second-bit effect

Incomplete local DIBL shieldingVt (left) shifts up when right bit is programmed Causes Vt window lossMore severe for short channel device

Vt (Right bit)

Vt (L

eft b

it)

Shorter channel

Vt (Right bit)

Vt (L

eft b

it)

Higher Vd

Scaling below 30 nmIncrease read drain voltage SOI device Double gate structure

NBitNBit / NROM Scalability (III)/ NROM Scalability (III)Scaling below 30nm

Separated nitride device1

Use side wall process to fabricate two separated SiNstripes Charges are stored in SiN only

Separated SiN device

1. Y.K. Lee, et al. (KAIST, Korea), IEEE Electron Device Letters, May 2004

(30nm device demonstrated) Charge trapping inseparated SiN device