1. FPGAOpen vSwitch , SDN Japan 2012/12/7

2. Open vSwitchDIY 5000FPGA 1000BASE-T NIC Ooading CPU+SWHW Cut-through forwarding 2Open vSwitch 3. OpenFlow NetFPGA 1G10G4 10GOpenFlow Broadcom API Indigo rmwarePica8 OpenWRT Open vSwitch HW OFTest 4. (1) Linux+Open vSwitch (OVS)HW HWOVSOoad (NIC) HWLinux+OVS StatisticsFlow-mod Packet-In Packet-OutSW(NIC)SW(NIC) dataFPGA NICTrac plane 5. (2) Linux+OVSCPU+MMU, memory, etc. FPGA OpenFlow SwitchCPU+SWHW Ethernet Openow controllerOpenow controller Host (CPU) Switch SwitchSwitch Switch SW SWCPU+SW CPU+SWhardware hardwarehardware hardware 6. OF networkOF switch1OF switch2 1G x3 1G x3OF switch x2 FPGAFPGALinux + OVSx2 (datapath)(datapath) OF controller100M1G 1G 1GOVS: Open vSwitch L2 switchOF: OpenFlow 7. (3) Cut-through forwarding && Pipeline processing OpenFlow , VoIPVM 8. Running code! MAC IP Core 10/100Base-* NetFPGA-1G (1000BASE-T 4) Verilog HDL+/ MacVerilog (iverilog,gtkwave) NetFPGA code: https://github.com/sora/ovs-hw 9. HW (NetFPGA-1G) 10. 1: 2: bonding Switch controllerRaspberry Pi $35ARM11 SoC(100 Mbps x1 ) OpenFlow controllerTCP RaspberryPiOoad 11. Linux+Open vSwitch (Raspberry Pi) 12. 1: Open vSwitchin_port=0, actions=output:1in_port=1, actions=output:0RFC2544 MeasureI/F: Port0 I/F: Port1 Open vSwitch I/F: Port0 I/F: Port1(vlan101)(vlan102) DUT(ovs-hw)eth0:vlan101eth0:vlan102I/F: Port3 I/F: Port2eth0:vlan103(vlan104)(vlan103)eth0:vlan104 13. 1: FPGA+PCIe Lattice ECP3 versa kitNetFPGA-1G Node.jswebsocketweb Code:https://github.com/Murailab-arch/magukara/FPGAdev boardHost PC Ethernet Browser DUTng PCI Ethernetp piExpress a Musernode.jsregistersmmap websocket 14. 15. 16. : PPS 3000L2PPS 1,520,000 1,400,000 1,200,000 1,000,000 PPS800,000600,000400,000L2SW && ovs-hw200,0000 0 400800 1200 1600 Frame size 17. : 3000L2 16,000 14,000 12,000L2SWLatency (ns) 10,0008000600040002000 ovs-hw 00 200 400 600 800 1000 1200 1400 1600Frame size 18. 2BondingOpenWRT802.1qIperf 19. PC1 PC2 Dest MAC addressoutputFPGA 1 FPGA 2 FPGA Ooad (RPi) PC1-Server1 PC1-SErver1 + PC2-Server2Server1 Server2 20. PC1PC1,21000 900thruoghput (Mbps) 800 700 600 500 400 300 200 FPGA 100 00 10 2030 40 5065 time 21. Next step: "FPGA hub" FPGA++ 152 (1) FPGA (XC6SLX45T) 5,000 yen RJ45 x8 PHY chip x8 SRAM (QDRII) 4 MB 1,500 yen Hub (SATA 3Gbps x4) 22. Open vSwitch HW Open vSwitchHW+ Flow tablestatistics , Openow OVS (ofproto_class) OpenFlowOVS 23. Q and Acode:ovs-hw, https://sora.github.com/ovs-hw/magukara,https://github.com/Murailab-arch/magukara/Simulation on your Mac:1. brew install icarus-verilog gtkwave2. git clone http://github.com/sora/ovs-hw3. cd ovs-hw; make test 24. 25. https://github.com/sora/ovs-hw/tree/master/doc/block_diagram 26. 10G DIY Xilinx Kintex7 connectivity kit, NetFPGA-10G : 1000BASE-T (10G-*R) PHYFPGA SERDESPCS/PMA FPGA 10 GbE PHY XGMII(125MHz, 8 bit -> 156.25MHz, 64 bit) 27. Flow table, statistics Flow table () TCAM (BlockRAM) + Hash (SRAM) FPGAtuple Flow table Statistics HP DevoFlow 28. Linux+OVS Ethernet type +802.1Q device driver()VLAN ID FPGA decap+Forward (physical ports)