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An Introduction to SOI Applications:Low Power to Smart Power
Mariam Sadaka
Goal & Agenda
Goal• Provide an introduction to the different applications addressed by SOI technology
and explain how SOI substrates enable Ultra-low power to high power applications
Agenda• Introduction• FDSOI for Digital Applications• High Resistivity SOI for RF Applications• SOI for Emerging Si-Based Photonics Applications• SOI for Smart Power Applications
2
IoT_ a Wide-Ranging Ecosystem
Everyday physical objects connected to the Internet, capable of identifying themselves and communicating data to other objects on the network…for smarter tomorrow
Number of mobile subscribers exploding, 95.5% world’s population in 2014…expected 9.3B by 2019*
3
Source: https://www.linkedin.com/pulse/20141113154816-4663617-you-are-invited-to-our-next-meetup-the-business-value-of-the-internet-of-things
*The International Telecommunication Union & Ericsson (2014)
Growing Applications/Opportunities
4
Big DataNetworking
IoT Automotive Consumer Multimedia
OutstandingPerformance
Longer battery life
$$$$
Optimized cost
High reliability
Intensified Challenges
Enabled by SOI technologies
….more integration, small form factor and fast time to market…
5
SOI Substrate Technologies
» Mature HVM processes that uses standard semiconductor equipment/processes «
Source: Soitec
Bonded SOISmart Cut
6
Wide Range of SOI Products
Top Silicon
Base Silicon
Buried Oxide
Soitec RF SOI
Soitec PD-SOI
Mobile and multimedia
communications
Mobile and multimedia
communications
Application processorsApplication processors
Game and entertainment
systems
Game and entertainment
systems
Smart power devices
(automotive, etc.)
Smart power devices
(automotive, etc.)
Photonics/Image sensors
applications
Photonics/Image sensors
applications
SOI for Digital Low Power ApplicationsMariam Sadaka, Bich-Yen Nguyen
FDSOI for Digital Applications
• Industry Challenge• Value Proposition• Engineered Substrates• Applications
8
Technology Migration History
9
Copper
Source : IBM
Low-k
Stress Tech
ULK
HK/MG
Scaling Innovation Material Innovation Structure
Innovation
130nm
Classical scaling hits the Tox scaling limit
Planar transistors on Bulk-Si hit the gate length
scaling limit
90nm 65nm 45nm 32/28nm 20nm Sub-20nm
FinFETFD-SOI
10
S DG
Bulk Si
Buried OXS DG
S DGEvolution
Minimum Design Disruption
Max scalability
Bulk SiBuried oxide
UTBB: Ultra thin body and box
Conventional Planar Bulk Transistor
Planar Single-or double Gate UTBB
Vertical Multiple-Gate (Bulk or SOI)
Revolution
The Fully Depleted Era
New paradigm :Electrostatic Scaling (Si Geometry)
SCE Behavior controlled by doping
Ultra-Thin Body & Box (UTBB) FDSOI Transistor
11
SOI substrate with Buried Oxide (Box)Extremely thin SOI+ Ultra-Thin BOX
Si Bulk Substrate
S DG
FDSOI transistor
Ultra-Thin Top Silicon Layer
Ultra-Thin Buried Oxide
Base Silicon
UTBB FDSOI Substrate
SOI substrate provides Fully Depleted structure
Ultra-Thin Body & BOX (UTBB) FDSOI: Transistor Advantages
12
UTBB FDOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SC immunity (SS, DIBL)• No History Effect
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body
Body BiasingCourtesy of STM
Knobs to control Perf/Power: Gate bias Back Bias
28 FDSOI vs. 28LP Process
13
• FD-SOI has less number of process steps and similar BEOL• Minimal change in process steps vs 28nm bulk• Simpler process helps offset the higher SOI substrate cost
Process steps
ST- Kirk Ouellette, Tokyo SOI Consortium workshop- Jan ‘15
14
Poly Biasing: modulating the gate length (Lg) in order to optimize the static power consumption or achieve higher speed at a given leakage target
– Lg= 25nm, TSi = 8.5nm– SS < 80mV/Dec; DIBL is less than 100mV/V much lower than Bulk for scaled Lg
Wider Static Power/Performance coverage by gate CD Biasing
Lg=25nmSS=75mV/Dec
Poly Biasing Advantage
Lg=25nmSS=75mV/Dec
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
-1 -0.5 0 0.5 1 1.5 2
Gate Voltage (V)
Drai
n C
urre
nt (A
/µm
)
SOI L=W=25nm
SOI L=25nm W=10µm
VD=1VnMOS
Courtesy of STM Barral-CEA Leti-IEDM 2007
8.5nm Lg=25nmSS=75mV/Dec
Back Biasing Advantage
15
Body biasing more efficient with UTBB FDSOI due to Ultra-Thin Box inhibiting parasitic effects
Wider range of back biasing
Higher body factor vs. bulk
Can be static or modulated dynamically
Courtesy of STM
BOX
Source
Drain
*Applying a voltage to the substrate
Body Biasing: Applying a voltage to the substrate (or body) Shifting/modulating VT to either gain in performance or reduction in power consumption
D. Jacquet, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, (2014)
Back Biasing: Wider Voltage Biasing Range for Ultimate Speed/ Power Control
BULK-300mV< Vbb< 300mV
UTBB-FDSOI-3V<Vbb< 3V
☻Limited & inefficient knob– Degrades w scaling– RBB limited by GIDL– FBB limited by SD junction leakage
& Latch-up @ high T
☺Box inhibits parasitic effects more efficient & wider
range of back biasing
Forward Back Bias (FBB) Performance boost
Reverse Back Bias (RBB) Leakage reduction
FBB/LVT
RBB/HVT
FBB benefit maximized @ low Vdd
RBB dramatic leakage power reduction
D. Jacquet, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, (2014)
16
17
Efficient knob for Performance & power optimization Compensate process fluctuations, improves yield No degradation with scaling & No area penalty vs bulk
VT Modulation
5 sources of VT modulation for UTBB: Gate Stack, Poly Biasing, Well type, Counter Doping, Body Biasing
LVT
RVT/SRAM
SLVT
Std Well / L= 24nm
Flip Well / L= 24nm
LVT + Counter doping
Ieff
Ioff
RBB
FBB
»LVT«
»RVT«
P. Flatresse, et. al. ISSCC 2013
Back Biasing: Performance Boost/Energy Efficiency
18
P. Flatresse, et. al. Leti Day June 2015
AVS : Adaptive Voltage ScalingABB: Adaptive Body Biasing
Tuning both VDD and FBB Provides better power gain at same performance
Lower dynamic power Slightly higher leakage than without FBB
More efficient than tuning the voltage
Performance boost @ same power
Improved power consumption @ same Freq
10/5/2015 19
• N/PMOS: VT modulation of 200mV for 10nm BOX
• No degradation of Ion-Ioff trade-off with back-bias up to ±2V
• Process compensation reduces margins taken @ design
• FBB used to accelerate Slow parts
ST- Kirk Ouellette, Tokyo SOI Consortium workshop- Jan ‘15
Q. Liu, ST, VLSI 2010Leti- VLSI 2010
Back Biasing: Process Compensation & No Degradation
Wider Power/Performance Coverage with UTBB FDSOI
20
Speed
Leak
age
Two knobs to control perf/leakage Gate CD-biasing (Physical) Body-biasing (Electrical)HHVTVT
RRVTVT
LVTLVT
sLVTsLVT
RVT+PB
LVT+PB
LVT+PB+FBB
RVT+PB’
RVT+PB”
RVT+PB”+RBB
LVT+PB’
LVT+PB’+FBB
28HKMG28HKMG
28FD-SOI
PB : Poly BiasFBB : Forward body biasRBB : Reverse body bias
UTBB FDSOI Enables Simpler AMS/RF Integration
• Improved Performance ‒ Higher speed in all analog blocks, higher gain
• Efficient Short Devices‒ Improved mismatch (AvT), higher Gm, fT
• Very large VT tuning range (BB)– Higher power efficiency, design margin, new designs,
smaller (*)
• Improved Noise & noise variability– Lower parasitic capacitance for high speed designs
• Improved passives– Enable LNA & VCO w improved noise figure
• Planar process, simpler design
21
High analog gain @ low L
Low Vt mismatch
low noise variability
Improved noise
*J. Lechevalier et. al, ISSCC 2015*A. Larie et. al, ISSCC2015*Le Tual et. al.,ICCSS 2014
Courtesy, A. Cathelin, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, STMicroelectronics
FDSOI Provides Best SER (Soft Error Rate)
22
• Bulk CMOS susceptibility to SER increases w scaling
• SER is as important to IC reliability
• Most redundancy schemes no longer work
FDSOI is intrinsically more resilient to SER‒ Box suppresses charge sharing‒ SOI ultra-small sensitive volume‒ No latch-up
Simpler design; less error correction & redundancy
Neu
tron
-SER
in F
T/M
b
Experimental Failure-in-Time (FIT) test data
28nm FD
-SOI
FDSOI >100x
lower SER than bulk
ST, Roche IEDM’13IRPS’14
NSREC’14
2nd gen RSD + cSiGe
UTBB FDSOI Scalability: Boosters Roadmap
23
*Enabled by SOI Substrate Engineering
ElectrostaticsSOI/ Box Thickness
External Resistance (Rext)Raised Source Drains (RSD)
Mobility BoostChannel Material
28nm 12/25nm Raised S/D Epi Unstrained
14/22nm 12/20nm PMOS: ISD SiGeB RSD epi PMOS: Strained SiGe channel
10nm 12/15nm PMOS: ISD SiGeB RSD epi- 2nd GenNMOS: ISD SiCP RSD epi
PMOS: Strained SiGe channelNMOS: Strained Si Channel
Substrate engineering enable electrostatics improvement and channel mobility enhancement
C1 - Restricted 24
Scalability possible down to Lg~10nm
SCE control improved with thinner TSi & TBox
CMOS integration w dual channel & thin box demonstrated down to 10nm
SOI Substrate Role in Technology Scalability; TSOI, TBOX & High Mobility Channels
What is the reference5nm
0
2
4
6
8
10
2 6 10 14 18 22LG (nm)
Re
qu
ire
d T
SO
I(n
m)
TSOI (thick BOX=145nm)
TSOI (UTBOX case)
DIBL=100mV/V
NanoWire
TBOX= 25nm25nm
10nm
7.5nm
TBOX= 145nm
K. Cheng et. al, IEDM 2012, A. Khalifizoor et. al. -IBM-VLSI 2012, Leti, Weber et. al, IEDM2005, Qing et. al., ST, IEDM 2014
Courtesy of CEA/Leti
Ioff of 100/1nA/μmNFET Ieff 495/300μA/μmPFET Ieff 495/260μA/μm
SGOI PFETSSOI NFET
• NMOS perf enhanced by bi-axial tensile strain
• PMOS perf enhaced by c-SiGe by local Ge condensation
Role of SOI Substrates in Enabling UTBB FDSOI Devices
25
Ultra-Thin Buried Oxide
Base Silicon
Ultra-Thin Top Silicon Layer S DG
UTBB FDSOI transistorUTBB FDSOI wafer
Requirements of device structure defined by Ultra-thin SOI & Box:
‒ SOI thickness & roughness critical for device electrostatic control & for ensuring low transistor VT variability
‒ Box thickness enables back biasing, and box uniformity affects efficiency of VT tuning through back biasing
‒ Excellent W2W & WiW uniformity necessary
Differential Reflective Microscopy (DRM)
WtWEllipso
WiWEllipso
Min / Max
µm-110-6 10-2 1
DRMRange
AFMRms
Box
Handle wafer
SOI=
+
+
101 10210-2
10-1
100
101
102
103
Frequency [Hz]
Pow
er [R
MS
2 / H
z]
Roughness (local thickness variation)
Deferential Reflective Microscopy (DRM): Bridges the gap btw ellipsometry & AFM
FDSOI Uniformity: Lowest VT Variability
26
Record & reproducible low VT variability= 1.25mV.m @ Lg=25nmImproved device matching; important to SRAM/Analog circuits
Gate Length (nm)
A vt(m
V.m
)
B.Doris et al., FD-Workshop at SFO, 2012
Cheng et. Al. IBM IEDM 2009
±2.6A, 2mm EE- 721 pts F5X inspection
Smart CutTM Provides Excellent W2W and WiW Uniformity
27
FDSOIPDSOI
88.6 µm
66.6
µm
W2W SOI thickness Uniformity (Å)
W2W BOX thickness Uniformity (Å)
SOI 120 ± 5Å
BOX 250 ± 10Å
12nm
Handle
SOI (12nm)
Box (25nm)
Si
Wafer
Stack
Micro
Local
41 pts ellipsometer measurement (3mm EE)
Benefit at Transistor and SoC Level
UTBB FDSOI
Good Electrostatics, Low mismatch
Back Biasing/VT Modulation
Low manufacturing risk
DEV
ICE
Dynamic power/leakage trade-off
Perf Boost/ Power Eff
Widest operating range with single process
Less Leakage
Better Reliability (SER)
Power Efficiency
Simpler /new Designs
High SpeedSoC
(Bld
g Bl
ocks
) Digital Memory AMS/RF
28
UTBB FDSOI- A Hybrid Solution
Device TypeDevice Type UTBB UTBB FDFD--SOISOI BULK BULK
Logic
SRAM
Capacitance, Varactor
Drift MOS (OTP)
Digital I/O
Analog MOS
RF MOS
Resistors (Poly) (Active)
Diodes (antenna)
ESD Devices (FET) (FET, diode, SCR)
Vertical Bipolar
FDSOIFDSOI
BoxBoxSiSi
Bulk Bulk
29
Courtesy of ST
28nm UTBB FDSOI vs BULK for Digital Application
30
P. Flatresse, et. al. ST- ISSCC 2013
Higher benefit at lower Vdd
LDPC 6T-SRAM (FBB 1V) functional down to 0.4V Wide operating range 6MHz/0.35V to 525MHz/1.5V
for same design Outstanding efficiency at every level
UTBB FDSOI for Power Efficient SRAM
31
Clear SNM modulation from back bias
SRAM remains functional down to VDD=0.4V
VBB
Q. Liu, et. al. VLSI Symposium 2011
Vmin gain thanks to better mismatch for FDSOI devices (No BB)
Low Vmin thanks to back bias w unique single-well design
G. Cesana, FDSOICE Workshop, Jun 22-23, 2015
FBB Tuned 450MHz Inverter Based Low-Pass Filter in 28nm UTBB FD-SOI
• 450MHz low-pass Gm-C filter w supply regulator-free operation– New robust design opportunities– Tuned by back-gate instead of supply voltage‒ Energy efficient‒ Low voltage‒ Competitive linearity
• Constant system-level behavior with very good analog features (Fc, linearity, noise) over VDD=0.7 to 1V
32
J. Lechevalierat al, ISSCC2015
UTBB FDSOI Value Proposition at the Application Level
33
Infrastructure Networking IoT
Automotive Consumer
WearablesSony Next Gen GNSS
Chip on FD-SOI
1mW
GPS chip, CXD5600GF
x10
10mW
K. Nakano, SOI Workshop, Tokyo 2015
G. Cesana,FDSOICEWorkshop, Jun’15
• Perf/Power efficiency• Adapt power consumption to workload• Efficient memory
ST- Kirk Ouellette, Tokyo SOI Consortium workshop- Jan ‘15
• Low cost• Efficient RF/analog integration• Ultra-low voltage operation
• Low leakage in high temp environment• High reliability• Efficient memory
• Optimized leakage in idle mode• Optimized MS/RF integration• Energy efficient SoC
~70% lower power
On-Chip : RF, logic & SRAMVDD 0.6V vs 1.1V
Power limit ADAS Video Analytics system
Dual A9 Energy Efficiency
D.Jacquet et al., VLSI Symposium 2013
Take Away
34
UTBB FDSOI serves many applications, thanks to its great high performance/low power/low cost and integration benefits
SOI substrates with controlled thin SOI and Box thickness enable UTBB FDSOI devices
– Low transistor mismatch to enable low voltage operation
– Ability to modulate VT for efficient power and performance trade-offs
Engineered SOI substrates provide a scaling path for UTBB FDSOI based on using high mobility channel materials
SOI Value for RF ApplicationsMariam Sadaka, Eric Desbonnets
Increasing Demand for Mobile Data Traffic
0
9
18
2013 2014 2015 2016 2017 2018
Exabytes per MonthMobile Data Traffic
61% CAGR 2013-2018
Mobile File Sharing (2,9%)
Mobile M2M (5,7%)
Mobile Audio (10,6%)
Mobile Web/Data (11,7%)
Mobile Video (69,1%)
Source: Cisco VNI Mobile, February 2014
CAGR - 61%
36
More Mobile Devices: Smart phones growth ~8% CAGR, 2014-2020 (IBS *)
More Mobile Users: WW subscriptions > world population in 2014 & over 65% to covert to LTE in 2019 (Ericsson**)
More Multimedia Applications: Data traffic continues to grow @ 61% CAGR, 2013-2018 (Cisco***)
*IBS May 2015**Ericsson Mobility Report, June 2014***Cisco VNI Mobile, February 2014
Advanced Networks with Higher Complexity
data traffic bandwidth better network perf.
3G, 4G are now adopted, next step will be LTE Advanced, then 5G
Advanced network standards require mobile devices to support:
– More bands (not 12 but 23)– Higher frequency bands (700 MHz to 3.5 GHz)– Multi User -Multiple Input Multiple Output (MU-MIMO)– Carrier Aggregation (CA)
Exploding number of switches in FEM
‒ ~6 for 2G to ~30 for today’s 4G LTE standard
Higher complexity Need for FEM integration
37
C. Didier & E. Desbonnets, White paper, Soitec, 2015
2G
3G
LTE
MODE
M +
TRAN
SCEI
VER
AntennaSwich Module
2G
2G
Rx
Power Amplifier
MODEM
+
TRANSCEIVER
AntennaSwich Module
Single Mode/Band Power Amplifier
3G
2G
3G
2G
3G
Rx
MODEM
+
TRANSCEIVER
Supply Modulator
AntennaSwap switch
AntennaSwich Module
FilterBank
PA Modeswitch
Power Amplifier
3GLTE
2G
3GLTE
2G
TxHighBand
TxLowBand
MIPI
Rx High Band
Rxdiversity
Diplexer
Coupler
Rx diversitySwich
AntennaTuner
Rx LowBand
Front-End-Module (FEM): interface between antenna and RF transceiver (Includes: power amplifiers, switches, low-
noise amplifiers, control circuitry, and passive elements)
Higher Linearity for Faster Mobile Throughput
3GPP Bandwidth DL / UL (bit/s)
LTE rel 8 1.4-20 MHz 150M (2x2) / 50M
LTE rel 10-12 1-3 x 20 MHz 1.6G (4x4) / 0.8G (2x2)
Extensive use of Carrier Aggregation & MIMO
Network Linearity (IIP3 in dBm)
2G 55
3G 65
4G LTE 72
4G LTE + CA Up to 90Source: Intel Mobile, L. Schumacher, Nov. 2012
>10X
38
10k
100k
1M
10M
100M1G
Bit/s
1G
2G
3G
LTE & LTE-A
Faster mobile throughput Stringent FEM linearity spec
Advanced Cellular Standards Drive Device Requirements
+ FET linearity improves with CMOS scaling
‒ Contribution of substrate nonlinearity dominates the overall switch performance
• Si bulk substrates not best suited due to high electrical conductivity and high-frequency losses
• High resistivity substrates needed to enable higher linearity & desired integration
Low insertion loss (must be able to handle high-power signals)
Low cross-talk (high isolation) High linearity
Date 39
Circuit performance vs. substrate non-linearity
IC linearity IC linearity
Substrate RF Substrate RF performanceperformance
Transition from Substrate to IC main
non linearity contributor
Substrate limited
IC limited
Target substrate
RFSOI: Silicon On Insulator for RF applications
Process Figure Of Merit RF-SOI GaAs SoS Bulk MEMS
Fully CMOS compatible ++ -- + ++ =
Foundries capacity offering ++ + - ++ -
RF Performance (linearity, …) + ++ + - ++
Full FEM Integration /SoC ++ - + ++ --
Cost + = - ++ =
40
RF-SOI: best FEM development platform‒ Best cost, area, and performance for RF switches
Mainstream technology solution adopted in HVM by the majority of RF foundries‒ Improved high frequency performance of CMOS with process shrinks‒ Availability of CMOS foundry technologies on 200 or 300mm substrates
05
1015202530
GaAS BSOS RFSOI
Antenna Switch Module (SP9T ) Cost
RF-SOI: Technology of Choice for Wireless Switching Apps
41
Integration
¢
Cost efficientPerformance
Cheaper process cost
SOI Bulk GaAs
Integration on-going
16 mm² SOI
in all 4G smartphonesincluding latest iPhone 6
Switch
PA output stage
PA first stages
x2die size reduction
compared top GaAs
4G/LTE-A & beyond performance enabler
High integration of RF Front-End module
Cost effectivetechnology
What is the source/Reference?
Enabling best performance, integration and cost-efficiencyOffered by > 10 foundries, and all FEM players
RF Switch Figure Of Merit (FOM)
1. Minimize Ron*Coff
Low Ron for low Insertion Loss‒ Ron scales with channel length
Low Coff for better Signal Loss (isolation)‒ Coff scales with Si thickness
2. Withstand high voltage swings (>30V) need multiple FET stacking
‒ BV with scaling
‒ Voltage varies across FETs imbalance w stack height
‒ Stacking Coff
42
Voltage Handling as a function of stack height (stack height= number of FETs in a switch arm)
A. Joshi, Skyworks, S3S conference 2014
Lg scaling Ron
TSi scaling Coff
Optimal low Ron*Coff region Maintain low number of stacked FETs to
withstand high power
Switch Limitations and Trade-offs
43
Impact Lg reduction on 2nd & 3rd Harmonics
• Even if a FET is optimized to minimize SCE, RF considerations (harmonics) can limit channel length scaling
Trade-offs need to be considered in developing a high performance switches
• Shorter Lg high levels of non-linearity•Thinner Si increases Ron & offsets Coff reduction benefit
Effect of Si thickness reduction on Ron &Coff
A. Joshi, Skyworks, S3S conference 2014
Back-end Interconnect Limitation
Cu lower resistivity (vs. Al) enables use of thinner metal layers Coff
Low K interlayer dielectric Coff
Cu and/or Low-K improve Ron*Coff, but increases wafer cost
Hybrid solutions that use Cu only for critical layers are being considered
44
A. Joshi, Skyworks, S3S conference 2014
Coff metal-to-metal capacitance
SOI Substrate Plays a Critical Role in Switch Performance
45
Smartcut™
Handle SubstrateBuried insulator
Device layerSiO2 (BOX) ~0.5-1.0um
Silicon (SOI) ~ 0.15um
High Resistivity > 1K.cm
C. Neve and J.-P. Raskin, IEEE Trans. Electron Devices, p. 924, (2012). D. Lederer and J.-P. Raskin, IEEE Trans. Electron Devices, p. 1664, (2008).
C. Neve, D. Lederer, G. Pailloncy, D. C. Kerr, J. M. Gering, T. G. McKay, M. S. Carroll and J.-P. Raskin, Proceedings of the 3rd European Microwave Integrated Circuits Conference, October 2008, Amsterdam, The NetherlandsA. Botula et al., Silicon Monolithic Integrated Circuits in RF Systems (SIRF), p.1, (2009).
F. Gianesello et. al. SOI conf., 2006
Compared to typical SOI, RFSOI handle substrate replaced with High Resistivity substrate
Improve performance: insertion loss, isolation and harmonic distortion
Enable integration of RF FEM: smaller size, better reliability, and lower system cost
For linear substrate; BOX thickness has minimal impact on loss Measured isolation Bulk vs HR SOI
Suppressing Substrate Losses & Reducing Non-linearity
46
Passivation of BOX & handle wafer interface is critical to minimize substrate nonlinearity
» Parasitic surface conduction (PSC): intrinsic layer induced under BOX due to fixed oxide charges attracting free carriers near Si/SiO2 interface «
High Resistivity SOI Substrate
High Resistivity SI BaseHigh Resistivity SI BaseTrap rich layerTrap rich layer
SiO2 (BOX)SiO2 (BOX)
Mono-crystal Top SiliconMono-crystal Top Silicon
High Resistivity SI BaseTrap rich layer
SiO2 (BOX)
Mono-crystal Top Silicon
RF-SOI
1. During Wafer Processing-High Dose Implant
Enhanced effective resistivity for very high linearity
High Resistivity SI BaseHigh Resistivity SI Base
Buried Insulating Layer SiO2 (BOX)Buried Insulating Layer SiO2 (BOX)
Mono-crystal Top SiliconMono-crystal Top Silicon
High Resistivity SI Base
Buried Insulating Layer SiO2 (BOX)
Mono-crystal Top Silicon
2. At Substrate Level-Trap-Rich Layer
PSC: Reduces substrate effective resistivity by >10X & limits linearity
Circuit StackingUltimate linearity
BOXBOX
Circuit on alternative substrate
Circuit Transfer onto RF substrate
IBM Proprietary Process: Crystal Damage Implant into Substrate Through a Trench to Suppress Substrate Losses
1. Device isolation: shallow trench isolation (STI)
2. Through-BOX substrate contact– Via etch, p-doped poly-Silicon fill + CMP to planarize to STI
3. CMOS transistor formation
4. Trench etch through STI & BOX to substrate in areas where substrate effects are to be suppressed– Heavy dose implants – Crystal damage– Trench fill by oxide & planarized
47
-1dB
High dose implant through trench is effective in suppressing substrate losses & improving linearity
Lower Insertion Loss
A. Botula et. al. SiRF 2009
M. Jaffe et. al. SiRF 2015
Effective harmonic suppression
A. Botula et. al. SiRF 2009Measured on 4mm coplanar waveguide
Adding Trap-Rich Layer to Suppress Substrate Losses
Add “Trap Rich” layer underneath Box, freezes PSC Improved substrate effective resistivity
‒ Traps originate from grain boundaries of thin Trach-Rich layer*
48
High Resistivity SI Base
Trap rich layerSiO2 (BOX)
Mono-crystal Top Silicon
Fixed Charges (Qox)~10e10cm2
Mobile & Interface trapped charges
*D. Lederer et. al.Solid-State Electronics, 47 (11), p. 1927 (2003)D. Lederer, et. al., SOI Conference, 2003, pp. 50-51D. Lederer, et. al., IEEE Electron Device Letters,.26, (11), pp. 805-807, (2005)E. Desbonnets et. al, Mocrowave J. 2015
Substrate with Trap-Rich layer (TR SOI) shows improved effective resistivity vs HR SOI‒ Both use 10 kOhm.cm handle Si substrate
~200 Ohm.cm~ 10 kOhm.cm
Measured eff : value of sub resistivity seen by the coplanar devices
Trap-Rich Layer: Efficient Solution to Recover HR Substrate Properties and Does Not Alter DC or RF Performance
49
Resistivity> 10 kΩ-cm
C. R. Neve et. al., IEEE Transactions on Electron Devices, v59, no.4, p924, 2012
Cut-off Frequency
2 channel doping: intrinsic (NiN) and std Boron (NP2N) FD SOI MOSFETs
High resistivity characteristic conserved after a full CMOS process
K. Ben Ali, et. al. SOI Conference –2012, pp. 112-113
Harmonic distortion not correlated to oxide, but due to different sub effective resistivity
Trap-rich layer underneath the BOX does not alter DC or RF behavior
1. without trap-rich
2. With trap-rich
Trap-rich layer recovers HR properties regardless of oxide layer
Trap Rich (TR SOI) vs HR SOI vs Quartz
Very low RF insertion loss (< 0.15 dB/mm @ 1 GHz) similar to quartz
Harmonics induced by the substrate are reduced with TR-SOI (-40dB) and comparable to Quartz
TR SOI reduces substrate noise (crosstalk) btw devices integrated on same chip
50
Coplanar WaveguideHarmonic generation
Fund. tone.
900MHzPin=15dBm
Coplanar waveguide set-up
HD2
500 k 1 M 10 M 50 M
-80
-70
-60
-50
-40
Noise frequency [Hz]
Noi
se a
mpl
itude
[dB
m]
HR-SOI (0 V)HR-SOI (-10 V noise pad)eSI HR-SOI (0 V)eSI HR-SOI (-10 V noise pad)
HR-Si
BOX
SourceN+ N+
DrainGate
Si
HR-Si
eSI layer
fNoise
fFund = 900 MHz
BOX
SourceN+ N+
DrainGate
Si
fNoise
fFund = 900 MHz
Insertion Loss Harmonics Noise
Trap Rich SOI
High Resistivity SOI
Lower Area/Higher Q-Factor Inductors & High Density Caps
Bulk processes: Require Patterned Ground Shield (PGS) to limit substrate losses
SOI with high-Resistivity substrates (>1KOhm.cm): – No PGS and uses the whole back end better Q factor & lower cost process– Enables 3D structures smaller area
0.82 nH
PGS
PGS: Patterned Ground Shield to limit substrate losses
HR SOI limits substrates losses enabling excellent tradeoff between area efficiency & high quality capacitors
•Q~20@5GHz in 65 nm BEOL, which is not feasible in bulk without Thick Copper option
High Resistivity Substrates Address FEM Challenges
52
High Resistive Base
Trap Rich LayerThin Buried Oxide
Mono - crystal Top Silicon
RF Losses •Improve losses by maintaining constant substrate resistivity
Linearity •Improve 2nd harmonic by >20dB, enabling devices to meet Advanced switch specs
Cross-Talk •Improved cross-talk typically 20dB @ 1GHz. Gives designers more layout freedom•Improves metal layer coupling with substrate (above an active device or not)
Hi Q Passives •Enable high perf matching networks for tuners, couplers, and active circuits (e.g. LNAs, low-noise & multi-mode multi-band PAs)
Thermal conductivity •RF performance not degraded by thin BOX. (Larieet al., ISSCC2015)
Die Size •Improve transistor matching, better stacking beyond 40V•Built in BOX isolation simplifies design rules (e.g.wide trenches) thus saving die area
Perf prediction •RF harmonic quality factor spec (HFQ) can be measured on blanket substrates and before devices are manufactured. Predict the 2nd harmonic distortion (HD2) performance of a CPW
RF-SOI Substrates: A Long History
20092011
• SoitecSmart Cut™ SOI
• UCL R&D work on HR-SOI
• Trap Rich SOI by UCL & Soitec
• HR-SOI HVM
• RFeSI™ ramp• BondedSilicon-on-Sapphire by Soitec & Peregrine
20051992
2014
• Power Amplifier on RF-SOI ramp
• RF switch demo on HR-SOI
2003
2012
• RF switch on SOI becomes industry mainstream
53
RF SOI is the technology of choice for wireless switching and is becoming popular for other functions such as PAs
Idea to market ~ 5 years3 generations sustrate in 10 years
Beyond Today’s Multi Chip Module: FEM integrationRF-SOI is the Ideal Substrate Path
MODEM
+
TRANSCEIVER
Supply Modulator
AntennaSwap switch
AntennaSwich Module
FilterBank
PA Modeswitch
Power Amplifier
3GLTE
2G
3GLTE
2G
TxHighBand
TxLowBand
MIPI
Rx High Band
Rxdiversity
Diplexer
Coupler
Rx diversitySwich
AntennaTuner
Rx LowBand
54
Beyond switch, TR-SOI opens the path to additional system integration in FEM space as well as even more complex mixed-signal SoCs
3GLTE
Switch
Antenna Tunner
Couplars, Diplexers
Power Amplifiers
Tunable FiltersRef: ST, IMEC, RFMD, Peregrine
A 130nm RFSOI with Switch, LNA, and EDNMOS Devices for Integrated FEM SoC Applications- On TR SOI
• State-of-the-art 130nm RFSOI for integrated FEM SOC:
– Antenna switches, diversity switches, antenna tuners, mixed-signal, digital functionality, standard interfaces, and power amplifiers
• High performance and low noise body tie 1.5V NMOS for LNA devices with a novel method of body contacting
• Low Ron*Coff NMOS for antenna switch
• State-of-the-art EDNMOS with fT of 38GHz and BVdss of 14V for integrated PA application
55
IV characteristics of a 10x0.2μm nFET switch transistor (Bdv~3.2V)
low 2nd and 3rd order harmonics
high fT and fMAX for high power gain, low NFminHigh quality passives are critical for good LNA and PA application
MIMInductor
3um Cu layer for high Q-inductors
R. Purakh et,. al., GF IBM, IEEE Radio Frequency Integrated Circuits Symposium, 2015
Take-Away
RF-SOI has rapidly evolved as a mainstream technology for switches enabling best performance, integration and cost-efficiency
RF industry roadmap is converging to Trap Rich RF-SOI substrates as the preferred choice due to better insertion loss, isolation and linearity
Trap Rich RF-SOI substrates meet present network standards and open the path for more FEM future integration
56
SOI Value for Photonics Applications
Mariam Sadaka, Arnaud Rigny
57
Data Centers are Transforming
58
Bandwidth
Scale
Traffic
Energy consumption increasingDistances expandingBandwidth increasing
Silicon photonics an efficient interconnect solution for future high bandwidth data centers
Transmission
Computing
Performance Improvement of Optical Transmission System with Silicon Photonics
59
Data Communication Telecommunication
High Perf, Low Vol
High Vol, Higher integration, Low Cost, Low Power
Fiber
Copper Optical
Integrated Optics (Wave guides)
Si Photonics; new era of faster, denser and more efficient
Silicon Photonics Playground
60
Si photonics address the increased data rate for short & ultra low reach by enabling integrated WDM solution for high bandwidth data rates
Si photonicsSMF/WDM
40Km
USR= ultra short reachShort reach Long reach
80Km
Wavelength division multiplexing is a technique where optical signals with different wavelengths are combined, transmitted together, and separated again
.
Transmission Speed Penetration into Data Centers
61
Total Available Market for Transceiver
Today
New data centers now need 40GbE
GbE: Transimitting Ethernet frames at a rate of a gigabit per second, as defined by the IEEE 802.3-2008 standard
Si Photonics for High Performance Computing (HPC)
Processor memory speed gap
Source: J. L. Hennessy et al Source: IBM
Perfo
rman
ce (A
rb.)
• Multi-core processors starved for data (Memory Wall)• Metal Interconnects- critical bottleneck for data transfer
• High BW optical links will be needed• Silicon photonics an efficient
interconnect solution HPC
62
Higher Cu resistivity
Source: ITRS
Advantages of Si Based Photonics
• Si wavelength (1.3-1.6um) compatible with fiber optic communication systems
• Compatible with CMOS infrastructure, i.e. lower cost
• More compact / smaller die size– Large refractive index contrast between Si (n~3.5) & SiO2 (n~1.5)
– Minimum turning radius in Si 250μm compared to 5,000μm in silica
– Optical waveguides with sharp bends
• Higher bandwidth (WDM)
• Possibility of integration with electronics
• More reliable
63
Source: Intel
Monolithic opto-electronic devices using low cost Si process
Si Photonics Optical Module-Building Blocks
• Silicon is the optical platform• High density optical interconnects made
at wafer scale• Can be integrated with other silicon chips
64
Source: Intel
Michael R. Bynum, Si Photonics, 2006
Majority of optical functions (except Laser) can be integrated on SOI wafer & connected by waveguidesIntegration enables WDM 100G in two tiny Chips
65
Transmitting and Receiving Si Photonics Signals
Hybrid InP/Si laser Ge Photodetector
TIA – Trans impedance amplifierconverts current into voltage signal
MZI modulator
Advantages of SOI Waveguides
• Waveguides operate based on concept of total internal reflection• Light is confined to Si by a top & bottom (BOX) cladding of oxide• Very small bend radius => smaller size• Waveguide size compatible with lasers• Tapering minimizes coupling loss btw glass fiber & Si waveguide• Si compatible with CMOS
3D Mode transformer
66
BOX
Rib Structure Guides optical power in Si plane
Rib edge depth= 60% of rib height H
BOX : vertical optical confinement Light confined into Si
B. Thomas Smith et. al. Kotura Inc.Lateral etch : Air = lateral optical barrier
SOI for Integration of Photonic Building Blocks
• Light Source Integration (Laser) – Main challenge due to silicon’s indirect band gap
– InP laser bonded on optical cavity in SOI
• Silicon Modulator (MZI- Mach-Zenderinterferometer design)– Incoming light split, applied voltage carrier injection
& change in refractive index changes light phase
– Adds constructively or de-constructively lightmodulation
• Silicon Photo-Detector – Converts back optical signal into an electrical signal
67
Mario J. Paniccia et. al, Intel 2007
SiGe waveguide-based photo-detector on a SOI
A.Liuetal.,Opt.Express15,660(2007) and L.Liaoetal.,Electr.Lett.43,(2007)0
WDM Enabled by Highly Uniform & Low-Loss Passive Si SiPhotonics Devices on 300mm CMOS platform
Challenge: extreme sensitivity of the device & waveguide to SOI thickness uniformity & sidewall quality- as defined by dry etch
Performance & variability improvement with advanced 300mm CMOS processes & substrate technology
68
Shankar Kumar Selvaraja1, ET. AL, imec, OFC 2014 © OSA 2014
Slot waveguide : propagation loss of 2dB/cm
SOI=220nm thickness distribution, 300mm Propagation loss 450nm spiral
waveguide
3σ ~0.12dB/cm3σ =1.65nm (0.75%) wafer range 2.5nm (1.1%)
slot waveguide
Spiral waveguide: lowest loss >50% lower than 200mm solution
Slot waveguide: propagation loss > 5x lower than 200mm solution
An important step for realizing next gen Si photonics transceivers with integrated ULP active and ULL passive devices
69
Guarantee WG propreties
Monomode, low loss
Guarantee optical confinement
Minimum thickess required
Mechanical substrate
±1% Thickness uniformityLow Defectivity
Enables: High Yield
1µm Thick BOX
Enables: Low loss propagation
High Resitivity substrate
Enables: Low loss propagationEnables: High speed modulation
Optical function Substrate requirement
Rib waveguide
Siliconoxide
Siliconoxide
Rib waveguide
Siliconoxide
Siliconoxide
Top
silic
onB
OX
Han
dle
Specificphotonics
Specificphotonics
SOI Wafer Enables Silicon Optical Devices
SOI Wafer Requirements for Si Photonics
May 2014 70
PhotonicsSOI
Optical confinementThin Si / Thick BOXTop Si~ 0.2-0.5µm
BOX>1µm
CMOS compatibleMonocrystaline siliconHigh quality crystal
Industrial compatibilitySilicon thickness uniformity
< +/-10nmUltimate uniformity
+/-1nm
CMOS Photonics Ecosystem & Market Penetration
71
• Most activity in R&D, but new interest from system side• Market penetration most likely at 100G, expected to start 2018
Serviceable Available Market for transceiver
A Broad Range of Potential Application
Data Com
Interconnect
Transceivers
ActiveCables
Sensor applicationsIn-cabinet communication
Home wiring and Consumer Applications
High BW Cabling
Interrogation engines
On Board Optical Engines
Lab on Chip
Bio/Medical and Life Sciences
Gyro, RF etc
Defense
Main application today
Jean Louis Malinge, 2014
7373
Transceiver Product Examples on SOI
Kotura transceiver technology Luxtera 100Gbps transceiver chip
Intel 50Gbps transceiverLightwire (Cisco) 50Gbps transceiver
• 17 • Communications TechnologyCommunications Technology LabLab
© 2004 Intel Corporation
TIATIA
TIATIA
DriversDrivers
CMOSCMOSCircuitryCircuitry
Vision: Integrated Photonic ChipConvergence of Communication and Computing
PhotodetectorPhotodetector
PassivePassiveAlignmentAlignment
ModulatorModulatorECLECL
FilterFilter MultipleMultipleChannelsChannels
74
Take-Away
Si Photonics is a promising low cost, high density, high bandwidth interconnect solution for future high bandwidth data transmission (Data centers Chip-level)
SOI wafers provide the optical platform enabling high density optical interconnects along with optical modules/functions and other Si electronics
May 2014 75
SOI Value of Smart Power Applications
10/5/2015
Mariam Sadaka, Arnaud Rigny
Smart City and Living
77
Power Electronics
More efficiencyMore functionality
INTEGRATION
World energy demand by region:past changes & future outlook
78
Blend of Analog, Digital and Robust Power Devices
PowerAnalog
Digital
SMART POWER
Bipolar-CMOS-DMOS (BCD) Platform for Smart Power
On-Chip integration of Bipolar for analog + CMOS for digital + DMOS for power & high voltage functions
Reduces complexity performance/cost benefits
Challenge: High & Low voltage device integration
‒ Device isolation‒ High breakdown voltage integration
79
Electric Isolation (pn-junction)
Electric Isolation (Deep Trench & pn-junction)
Dielectric Isolation (SOI)
Bulk Bulk SOI
oDeep implanto Large guard ring
o Latch-upoSurface penalty
oDeep trench for lateral isolationoPN junction for vertical isolation
o Latch-upoReduced surface penalty
oDielectric isolation (lateral & vertical)o Latch-up freeoArea saving
o Lower parasitics
• Lateral & vertical pn-junction • Add trench isolation• Vertical pn-junction
• Remove parasitic pn-junction• Improves leakage & high temp operation
Isolation Challenge
Source Gate Drain
n-doped epi layer
P- well
p+ junction
isolation
p-doped substrate
n+n+ n+
P- well
n+p+ Drift region
Source Gate Drain Source GateDrain
p+p+
Low voltage High voltageIsolation area
Parasitic pn junction
Source Gate Drain
n-doped epi layer
P-well
p+ junction
isolation
p-doped substrate
n+n+ n+
P- well
n+
p+ Drift region
Source Gate Drain Source GateDrain
p+p+
Low voltage High voltageIsolation area
Source Gate Drain
n-doped epi layer
P-well
p-doped substrate
n+n+ n+
P- welln+
p+ Drift region
Source Gate Drain Source GateDrain
p+p+
Low voltage High voltageIsolation area
Box
80
Dielectric Isolation Benefits
Source Gate Drain
n-doped epi layer P- well
p or n-doped substraten+n+ n+
P- well
n+p+ Drift region
Source Gate Drain Source Gate Drain
p+p+
Low voltage High voltageIsolation area
Box
Dielectric isolation btw high/low voltage: Reduced junction isolation area
Dielectric isolation btw n/p DMOS: Reduce crosstalk
No pnpn parasitic thyristor:No latch-up
n or p-doped flexibility
No pn junction for the p-well: Increase temp range operation
81
RESURF; an efficient way to integrate high voltage with low voltage devices
Lateral diode with a thin n-type epi layer on a low doped p-substrate provides trade-off between BV & RON
– BV: F(p-Sub doping, Epi-layer doping & thickness) – RON: F(Epi-layer doping & thickness)
Reduced electric field in drift region < critical field
82
High Breakdown Voltage Integration:RESURF Effect (Reduced Surface Field Effect)
•Breakdown Voltage: BV•On-Resistance: RON
Critical field (limit)
Extends drift region field
http://www.iue.tuwien.ac.at/phd/park/node25.html
Epi region is fully depleted before the lateral electric field reaches a critical value
5 October, 201583
Double-RESURF Effect with SOI
BV of SOI devices F(tOX, tSOI, Ldrift, Dopingdrift), no sub limitation
Most of BV is supported by Box
High BV can be achieved with thick & thinner SOI
SOI enables a “double RESURF” (Field plates)
Double-RESURF can be used to increase doping level in drift region lower RON smaller device area
Piet Wessels, NXP , SOI Conference 2007Shengdong Hu et al, 2008http://www.iue.tuwien.ac.at/phd/park/node25.html
n-channel SOI-LDMOSFET.
2um
7um
BV of 300V
Field plate
Box
1st Field Plate
SOI
2nd Field Plate
Option thick SOI
SOI >3µmUniformity <0.5µm
Option thin SOI
SOI <0.5µm
Uniformity <0.05µm
Thickness conditions to match RESURF criterias
Bre
akdo
wn
volt
age
SOI thickness
Thin SOI Thick SOI
Box= 3um
Box= 2um
SOI Benefit @ Device Level
PerformancesHigh temperatureUp to 225°C
High reliability
IntegrationDie shrink
High voltage
84
Die Shrink Benefit
• Smaller die size and ease of multi voltage
IntegrationCost effective
Small trench
isolation
Easier voltage stacking
Junction isolation: BV Area loss
Dielectric isolation: small lost area, independent of voltage
85
Example: Courtesy ATMEL
n-doped epi layer P- well
p or n-doped substrate
n+
p+
Pn-Junction Isolation area
p+p+ p+ junction
isolation
n-doped epi layer
p or n-doped substrate
P- well
n+p+Dielectric Isolation area
p+p+
1.6µmIso area~15µm width for 100VIso area~60µm width for 600V
Iso area~1.6µm @ any voltage
SOI
Bulk
Bulk
SOI
High Temperature Benefit• Junction temperature
can go up to 225°C
High temperature
No pnjunction for
p well
substrate
No pnjunction
withsubstrate
Parasitic PN junction leakage w Temp for Bulk
‒ Limits TJ up to 125°C, induce self-heating performance degradation
SOI eliminates leakage path btw S/D/sub
High temperature operation, Tj ~ 225°CImproved power dissipation, smaller/cheaper heat sink
86
Source Gate Drain
n-doped epi layerP- well
p-doped substrate
n+n+
Source Gate Drain
p+p+
Box
Atmel
TJMAX (oC) PDMAX(W)
Driver IC 125 0.6
High Temp-Driver IC
200 1.8
TJMAX= Max Junction TempTA= Ambient Temp (125oC)JA= Thermal resistance (40K/W)PDMAX= Max Power Dissipation
Higher Power Dissipation
Bulk
SOI
Improved Reliability Benefit• Simple design
High Reliability
No latch-up
ESD/EMI immunity
Reducecoss-talk
Source Gate Drain
n-doped epi layerP- well
p-doped substraten+n+
Source Gate Drain
p+p+
1. Undesirable parasitic pnpn junction, under transient spike condition
SOI: Truly free-latch-up operation
2. Parasitic pn junction, between adjacent pMOS and nMOS
SOI: no pn-junction, no cross-talk
Improved EMI/EMC=> better reliability
2
1
87
Box
Performance Benefit• Leakage, Rdson and
switching speed improvement
• Up to 600V BV
Performances
Low leakage
High switchingfrequency
LowRdson
88
Best trade-off between RON* Area & BV
Adriaan Ludikhuize et. al., 2001
Bulk
n-doped epi layer
P- well
p-doped substrate
n+n+p+p+
Remove parasitic capacitance Improve transistor switching speed
Box
Leakage Performances Comparison
Bulk
SOI
Atmel
Approach ideal
RESURF technology for high BV
Benefit for multichip packaging
Electrically isolated
Up to 600V IGBT
integrationsubstrate
Electricalisolation
withsubstrate
LDMOS w RESURF
SOI-BCDMOS Flavors
n- bodyp+
Handle substrate
Drain Gate Source
p+iso
iso
Buried oxide layern- body
p+
Handle substrate
Drain Gate Source
p+is is
Buried oxide layer
THIN SOIPartially depleted
THIN SOIFully depleted
Dielectric isolationNo SD parasitic junction
Channel parasitic junction
Dielectric isolationNo SD parasitic junctionNo channel parasitic junction
Buried oxide layer
n- bodyp+
Handle substrate
Drain Gate Source
p+
isol
atio
n
isol
atio
n
THICK SOIBulk like design
Dielectric isolation
1. SD parasitic junction2. Channel parasitic junction
89
SOI Wafer Technologies for Power ApplicationsB
SOI
Smar
t C
ut™
SOI Thickness
• Min ~ 3µm• Max ~100s µm
• Uniformity ~0.5µm
• 2 wafers to build 1 SOI
SOI Thickness
• Min ~ 0.1µm• Max ~10 µm
• Uniformity ~0.01µm
• <2 wafers to build 1 SOI
BOX Thickness• 0.4µm (40V)• 1µm (200V)• 3µm (600V)
90
Benefit at Chip Level and System Level
Thin SOIOptimum RESURF
High switching speed
Lower Rdson
No latch-up
Very smaller devices
Trench isolation
Thick SOINon optimal RESURF
Switching speed
Small Rdson
No latch-up
Small devices
Deep trench isolation
BulkNon optimal resurf
Switching speed
Small Rdson
Latch-up
Large devices
Junction isolation
DEV
ICE
System size/weight
Total BOM cost
ESD/EMI protection
Medium current
System size/weight
Total BOM cost
ESD/EMI protection
High current
System size/weight
Total BOM cost
ESD/EMI protection
High current
SYST
EM
91
SOI Smart Power Applications
92
Industrial• Ultrasound Medical
imaging• Oil drilling• Aerospace
Automotive• Transceiver CAN/LIN• Brushless motor drive• High T. gate drivers
Communication• AMOLED power supply• AC/DC Power converter
Consumer• LED drivers• 3-phase motor drivers
(white good, air conditionner)
• Plasma display drivers
IT• Desktop power supply• Power over Ethernet
SOI
SOI SO
I
SOI
SOI
SOI Power Applications: Different Drivers
93
LED Driver : Energy saving (retrofit lamp)LED = 80% efficiency + 40000h life timeEfficiency is key
PDP Driver: Large Flat panel DisplayIntegration is key
High number of voltage driverHigh voltage drive (200V) Compact system for size contraint
Power supply for mobile: Mobility & efficiencyEfficiency is key
High efficiency (green)Low Standby power consumptionSpace constraint (small size)
Power Over Ethernet Driver : IP centricinfrastructure and Voice over IPWide load range is key
Class-D amplifier : Car entertainment, infotainmentThermal behavior is key
High audio amplificationReduced power dissiptnLow distortion (soundquality)Space constraint
AMOLED Driver : Very flat display, high contrastratio, large viewing angleVoltage stacking is key
Low leakage for mobile applicationPositive and negativevoltages for reverse bias annealing
Low data perturbationHigh voltage power supplymix with low voltage data transmission DC/DC converter for wideload range
High T environnement (200°C)-Reduced Heat SinkSpace constraint (Retrofit)High reliability (40,000h)Low ext. component count (14 compared to 60)
Take-Away
SOI Substrates enable High & Low voltage integration key for Smart Power
‒ Dielectric isolation‒ Double-RESURF‒ High temperature operation ‒ Truly latch-up free operation‒ Power efficiency
Several applications enabled by SOI demonstrate high competitive solution
94
SOI Substrates Enabling Next Gen Devices & Applications
95
FDSOI- Digital
High Resistivity SOI- RF
SOI -Si based Photonics
Power SOI
SOI• Low Power• Cost effective
• High performance• Integrated solutions
• Improve reliability & global efficiency
• Greater functionality at reduced cost • Lower power per bit
Thanks to Bich-Yen Nguyen, Eric Desbonnets, Arnaud Rigny, Christophe Maleville for their feedback and support
Thank You for your attention
Date 96