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ROBDD: Canonicity of ROBDDs, If-Then-Else on ROBDDs & Equivalence of ROBDD
Presented By:Iffat AnjumRoll: RK-543
Date: 28/09/14
Contents
•Reduced Ordered Binary Decision Diagram
•Canonicity of ROBDDs•If-Then-Else on ROBDDs•Equivalence of ROBDD
Reduced Ordered Binary Decision Diagram• A BDD is Ordered (OBDD)
▫ if on all paths through the graph the variables respect a given linear order x1 < x2 < … < xn.
• An OBDD is Reduced (ROBDD) if▫ Uniqueness: no two distinct nodes u and v have the
same variable name and low- and high-successor var(u) = var(v),low(u) = low(v) & high(u) = high(v) implies u
= v;
▫ non-redundant tests: no variable node u has identical low- and high-successor, i.e.,
low(u) = high(u)
• An ROBDD can be obtained from an OBDD by repeatedly applying the following reduction rules (until none of the them can be applied anymore):
▫ Remove duplicate terminal (leaf) nodes▫ Remove duplicate non-terminal (internal) nodes▫ Remove nodes with redundant tests
ROBDD
• Two Boolean functions are equivalent iff their reduced OBDDs (ROBDD) are identical with respect to any variable ordering.
• For any Boolean function f, there is a unique (up to iso-morphism) ROBDD representing f and any other OBDD representing f contains more nodes.
• For any function f : B n →B there is exactly one ROBDD b with variables x1 < x2 < . . . < xn such that,
tb[v1/x1, . . . , vn/xn] = f (v1, . . . , vn) for all (v1, ...,vn) ∈ Bn.
Canonicity of ROBDDs
Canonicity of ROBDD• If G0 and G1 are two ROBDD representations of a Boolean
function f, then G0 and G1 are isomorphic.
• Two ROBDDs G0 and G1 are isomorphic if there is a one-to-one mapping σ from the vertexes of G0 onto the vertexes of G1.
• Suppose that v0 is a vertex of G0 and v1 = σ(v0) is the corresponding vertex in G1. Then,▫ One of the following must hold:
both v0 and v1 are terminal vertexes with
value(v0) = value(v1) both v0 and v1 are non-terminal vertexes with:
index(v0) = index(v1),
σ(low(v0)) = low(v1),
σ(high(v0)) = high(v1).
• A canonical form is obtained by applying the transformation rules until no further application is possible.
• Due to the canonicity of ROBDD different Boolean operations can be efficiently implemented.
• Possible applications can be :▫checking equivalence: verify isomorphism between
ROBDDs▫non satisfiability: verify if ROBDD has only one
terminal node, labeled by 0 ▫tautology: verify if ROBDD has only one terminal
node, labeled by 1
Canonicity of ROBDD
If-Then-Else on ROBDDs
•The If-Then-Else or ITE is a three-variable Boolean operator, defined as:
ITE(f; g; h) = f · g + f · h
•Just like:▫“if then else” in a programming language▫A mux in hardware
A very important property of the ITE operator, is that all two-argument operators can be expressed in terms of the ITE operator .
The above mentioned property gives great power to manipulate switching functions and hence are used extensively in manipulating the BDD.
If-Then-Else on ROBDDs
•In a BDD, a function is represented recursively with triples (xi; f|xi=1; f|xi=0), which are a consequence of Shannon’s decomposition theorem:
f = xi · f|xi=1 + xi · f|xi=0
•Shannon’s decomposition theorem can be shortly written as:
F = ite(x1, Fx1=1, Fx1=0)
ite(F, G,H) = (F ^ G) ( F ^ H)
If-Then-Else on ROBDDs
If-Then-Else on ROBDDs
• Each node is written as a triple: f = (v, g, h) where,
g = fv and h = fv • We read this triple as:
f = if v then g else h = ite (v, g, h) = vg +v’h
Equivalence of ROBDD
• Two Boolean functions are logically equivalent if and only if their ROBDDs (built with the same variable ordering) are isomorphic.
• Two ROBDDs are isomorphic if there exists a bijection b between their graphs such that
▫Terminals are mapped to terminals and non-terminals are mapped to non-terminals
▫For every terminal vertex v, value(v) = value(b(v)),▫For every non-terminal vertex v,
var(v) = var(b(v)), b(low(v)) = low(b(v)), and b(high(v)) = high(b(v))
Equivalence of ROBDD• The ROBDDs in Figure are isomorphic according to the given definition of isomorphism. • So the functions, of which these are the ROBDDs, are logically equivalent.
Equivalence Checking Tools• Commercial tools:
▫Chrysalis: Design Verifier▫Synopsys: Formality▫Cadence: Affirma▫Verysys: Tornado▫AHL: ChekOff-E
• Application:▫Used to prove equivalence of two sequential
circuits that have the same state variables (or at least the same state space and a known mapping between states) by verifying that they have the same next-state and output functions
▫Used in place of gate vs. RTL verification by simulation