Real time atomization of agriculture system for the modernization of indian agriculture system

Real Time Atomization of agriculture system for the modernization of Indian agriculture system

1. INTRODUCTON

1.1 INTRODUCTION TO THE PROJECT

The paper “Real time atomization of Indian agricultural system” using ARM7 and GSM’

is focused on atomizing the irrigation system and at the same time caring the crop in all aspects for social

welfare of Indian agricultural system and also to provide adequate irrigation in particular area. The set up

consists of ARM7TDMI core with dedicated embedded equipment, the processor which is a 32-bit

microprocessor; GSM serves as an important part as it is responsible for controlling the irrigation on

field and sends them to the receiver through coded signals. GSM operates through SMSes and is the link

between ARM processor and centralized unit. ARM7TDMI is an advanced version of microprocessors

and forms the heart of the system. Our project aims to implement the basic application of atomizing the

irrigation field by programming the components and building the necessary hardware. This project is

used to find the exact field condition. GSM is used to inform the user about the exact field condition.

The information is given on user request in form of SMS. GSM modem can be controlled by standard set

of AT (Attention) commands. These commands can be used to control majority of the functions of GSM

modem.

OVERVIEW OF THE TECHNOLOGIES USED1


Embedded Systems:

An embedded system can be defined as a computing device that does a specific focused job.

Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine, mobile phone

etc. are examples of embedded systems. Each of these appliances will have a processor and special

hardware to meet the specific requirement of the application along with the embedded software that is

executed by the processor for meeting that specific requirement.

The embedded software is also called “firm ware”. The desktop/laptop computer is a general

purpose computer. You can use it for a variety of applications such as playing games, word processing,

accounting, software development and soon.

In contrast, the software in the embedded systems is always fixed listed below:

Embedded systems do a very specific task, they cannot be programmed to do different things.

Embedded systems have very limited resources, particularly the memory. Generally, they do not have

secondary storage devices such as the CDROM or the floppy disk. Embedded systems have to work

against some deadlines. A specific job has to be completed within a specific time. In some embedded

systems, called real-time systems, the deadlines are stringent. Missing a deadline may cause a

catastrophe-loss of life or damage to property. Embedded systems are constrained for power. As many

embedded systems operate through a battery, the power consumption has to be very low. Some

embedded systems have to operate in extreme environmental conditions such as very high temperatures

and humidity.

Following are the advantages of Embedded Systems:

1. They are designed to do a specific task and have real time performance constraints which must be

met.

2. They allow the system hardware to be simplified so costs are reduced.

3. They are usually in the form of small computerized parts in larger devices which serve a general

purpose.

4. The program instructions for embedded systems run with limited computer hardware resources,

little memory and small or even non-existent keyboard or screen.

CHAPTER 2

2


HARDWARE IMPLEMENTATION OF THE PROJECT

This chapter briefly explains about the Hardware Implementation of the project. It discusses the

design and working of the design with the help of block diagram and circuit diagram and explanation of

circuit diagram in detail. It explains the features, timer programming, serial communication, interrupts of

LPC2148 microcontroller. It also explains the various modules used in this project.

Project Design

The implementation of the project design can be divided in two parts.

Hardware implementation

Firmware implementation

Hardware implementation deals in drawing the schematic on the plane paper according to the

application, testing the schematic design over the breadboard using the various IC’s to find if the design

meets the objective, carrying out the PCB layout of the schematic tested on breadboard, finally preparing

the board and testing the designed hardware.

The firmware part deals in programming the microcontroller so that it can control the operation

of the IC’s used in the implementation. In the present work, we have used the kicad design software for

PCB circuit design, the KEIL software development tool to write and compile the source code, which

has been written in the C language. The flash magic programmer has been used to write this compile

code into the microcontroller. The firmware implementation is explained in the next chapter.

The project design and principle are explained in this chapter using the block diagram and circuit

diagram. The block diagram discusses about the required components of the design and working

condition is explained using circuit diagram and system wiring diagram.

3


BLOCK DIAGRAM:

INTRODUCTION TO LPC2148

INTRODUCTION

The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU

with real-time emulation and embedded trace support, that combines the microcontroller with

embedded high speed flash memory ranging from 32 KB to 512 KB. A 128-bit wide memory interface

and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 %

with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for

4

MICROCONTROLLER

TemperatureSensor

WaterLevelSensor

LDRSensor

HumiditySensor

Power Supply

LCD

GSM


applications where miniaturization is a key requirement, such as access control and point-of-sale. A

blend of serial communications interfaces ranging from a USB 2.0 Full Speed device, multiple

UARTs, SPI, SSP to I2Cs, and on-chip SRAM of 8 KB up to 40 KB, make these devices very well

suited for communication gateways and protocol converters, soft modems, voice recognition and

low end imaging, providing both large buffer size and high processing power. Various 32-bit timers,

single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine

edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for

industrial control and medical systems.

Features

16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

8 to 40 KB of on-chip static RAM and 32 to 512 KB of on-chip flash program memory. 128 bit

wide interface/accelerator enables high speed 60 MHz operation.

In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1ms.

EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip

RealMonitor software and high speed tracing of instruction execution.

USB 2.0 Full Speed compliant Device Controller with 2 KB of endpoint RAM.

In addition, the LPC2146/8 provide 8 KB of on-chip RAM accessible to USB by DMA.

One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog

inputs, with puts, with conversion times as low as 2.44 bits per channel.

One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog

inputs, with conversion times as low as 2.44 bits per channel.

Single 10-bit D/A converter provides variable analog output.

Two 32-bit timers/external event counters (with four capture and four compare channels

each), PWM unit (six outputs) and watchdog.

Low power real-time clock with independent power and dedicated 32 kHz clock input.

Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus

(400 KBits/s), SPI and SSP with buffering and variable data length capabilities.

Vectored interrupt controller with configurable priorities and vector addresses.

Up to 45 of 5V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

Up to nine edge or level sensitive external interrupt pins available.

60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of

5


100 s.

On-chip integrated oscillator operates with an external crystal in range from 1 MHz to

30 MHz and with an external oscillator up to 50 MHz.

Power saving modes include Idle and Power-down.

Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.

Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out

Detect (BOD) or Real-Time Clock (RTC).

Single power supply chip with Power-On Reset (POR) and BOD circuits:

– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5V tolerant I/O

pads.

APPLICATIONS

• Industrial control

• Medical systems

• Access control

• Point-of-sale

• Communication gateway

• Embedded soft modem

• General purpose applications

Architectural overview

The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the

ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-

performance Bus (AHB) for interface to the interrupt controller, and the ARM Peripheral Bus (APB, a

compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral

functions. The LPC2141/24/6/8 configures the ARM7TDMI-S processor in little-endian byte order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM

memory space. Each AHB peripheral is allocated a 16 KB address space within the AHB address

space. LPC2141/2/4/6/8 peripheral functions (other than the interrupt controller) are connected to the

6


APB bus. The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also

allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each APB

peripheral is allocated a 16 KB address space within the APB address space.

ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on Reduced

Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are

much simpler than those of micro programmed Complex Instruction Set Computers. This simplicity

results in a high instruction throughput and impressive real-time interrupt response from a small and

cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor is being

decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known

as THUMB, which makes it ideally suited to high-volume applications with memory restrictions,

or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.

• A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density

of standard ARM code while retaining most of the ARM’s performance advantage over a traditional

16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same

32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160%

of the performance of an equivalent ARM processor connected to a 16-bit memory system.

7


On-chip flash memory system

The LPC2141/2/4/6/8 incorporates a 32 KB, 64 KB, 128 KB, 256 KB, and 512 KB Flash memory

system, respectively. This memory may be used for both code and data storage. Programming of the

Flash memory may be accomplished in several ways: over the serial built-in JTAG interface, using In

System Programming (ISP) and UART0, or by means of In Application Programming (IAP)

capabilities. The application program, using the IAP functions, may also erase and/or program the

Flash while the application is running, allowing a great degree of flexibility for data storage field

firmware upgrades, etc. When the LPC2141/2/4/6/8 on-chip bootloader is used, 32 KB, 64 KB, 128

KB, 256 KB, and 500 KB of Flash memory is available for user code.

The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write cycles and

20 years of data-retention.

On-chip Static RAM (SRAM)

On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip

SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8 provide 8/16/32 KB of

static RAM, respectively.

The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.

Word and halfword accesses to the memory ignore the alignment of the address and access the

naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word

accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and writes require data

accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0,

2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as words to originate from addresses

with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This

rule applies to both off and on-chip memory usage.

The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls

during back-to-back writes. The write-back buffer always holds the last data sent by software to the

8


SRAM. This data is only written to the SRAM when another write is requested by software (the data is

only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM

contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does

not reflect the last write operation). Any software that checks SRAM contents after reset must take this

into account. Two identical writes to a location guarantee that the data will be present after a Reset.

Alternatively, a dummy write operation before entering idle or power-down mode will similarly

guarantee that the last data written will be present in SRAM after a subsequent Reset.

Block diagram

9


1. Pins shared with GPIO.

2. LPC2148 only.

3. USB DMA controller with 8 KB of RAM accessible as general purpose RAM and/or DMA is

available in LPC2148 only.

Memory maps

The LPC2141/2/4/6/8 incorporates several distinct memory regions, shown in the following

figures. Fig. shows the overall map of the entire address space from the user program viewpoint

following reset.

10


Figures 3 through 4 and Ta ble 2 show different views of the peripheral address space. Both the AHB

and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each

peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each

peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their

size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-

bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word

and half-word registers must be accessed all at once. For example, it is not possible to read or write the

upper byte of a word register separately.

11


ANALOG TO DIGITAL CONVERSION

Introduction

An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device that converts a

continuous physical quantity (usually voltage) to a digital number that represents the quantity's

amplitude.

12


The conversion involves quantization of the input, so it necessarily introduces a small amount of

error. Instead of doing a single conversion, an ADC often performs the conversions ("samples" the input)

periodically. The result is a sequence of digital values that have converted a continuous-time and

continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.

An ADC is defined by its bandwidth (the range of frequencies it can measure) and its signal to

noise ratio (how accurately it can measure a signal relative to the noise it introduces). The actual

bandwidth of an ADC is characterized primarily by its sampling rate, and to a lesser extent by how it

handles errors such as aliasing. The dynamic range of an ADC is influenced by many factors, including

the resolution (the number of output levels it can quantize a signal to), linearity and accuracy (how well

the quantization levels match the true analog signal) and jitter (small timing errors that introduce

additional noise). The dynamic range of an ADC is often summarized in terms of its effective number of

bits (ENOB), the number of bits of each measure it returns that are on average not noise. An ideal ADC

has an ENOB equal to its resolution. ADCs are chosen to match the bandwidth and required signal to

noise ratio of the signal to be quantized. If an ADC operates at a sampling rate greater than twice the

bandwidth of the signal, then perfect reconstruction is possible given an ideal ADC and neglecting

quantization error. The presence of quantization error limits the dynamic range of even an ideal ADC,

however, if the dynamic range of the ADC exceeds that of the input signal, its effects may be neglected

resulting in an essentially perfect digital representation of the input signal.

An ADC may also provide an isolated measurement such as an electronic device that converts

an input analog voltage or current to a digital number proportional to the magnitude of the voltage or

current. However, some non-electronic or only partially electronic devices, such as rotary encoders, can

also be considered ADCs. The digital output may use different coding schemes. Typically the digital

output will be a two's complement binary number that is proportional to the input, but there are other

possibilities. An encoder, for example, might output a Gray code.

Features

10 bit successive approximation analog to digital converter (one in LPC2141/2 and two in

LPC2144/6/8).

Input multiplexing among 6 or 8 pins (ADC0 and ADC1).

Power-down mode.

13

http://en.wikipedia.org/wiki/Gray_code

http://en.wikipedia.org/wiki/Two's_complement

http://en.wikipedia.org/wiki/Rotary_encoder

http://en.wikipedia.org/wiki/Electric_current

http://en.wikipedia.org/wiki/Voltage

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Nyquist%E2%80%93Shannon_sampling_theorem

http://en.wikipedia.org/wiki/Effective_number_of_bits

http://en.wikipedia.org/wiki/Effective_number_of_bits

http://en.wikipedia.org/wiki/Jitter

http://en.wikipedia.org/wiki/Quantize

http://en.wikipedia.org/wiki/Dynamic_range

http://en.wikipedia.org/wiki/Aliasing

http://en.wikipedia.org/wiki/Sampling_rate

http://en.wikipedia.org/wiki/Digital_signal

http://en.wikipedia.org/wiki/Discrete-time

http://en.wikipedia.org/wiki/Analog_signal

http://en.wikipedia.org/wiki/Sampling_(signal_processing)

http://en.wikipedia.org/wiki/Quantization_(signal_processing)


Measurements range 0 V to VREF (typically 3 V; not to exceed VDDA voltage level).

10 bit conversion time >= 2.44 us.

Burst conversion mode for single or multiple inputs.

Optional conversion on transition on input pin or Timer Match signal.

Global Start command for both converters (LPC2144/6/8 only).

Description

Basic clocking for the A/D converters is provided by the APB clock. A programmable divider is

included in each converter, to scale this clock to the 4.5 MHz (max) clock needed by the successive

approximation process. A fully accurate conversion requires 11 of these clocks.

Pin description

Below table gives a brief summary of each of ADC related pins.

Register description

The A/D Converter registers are shown in below table.

ADC registers

14


A/D Control Register

Bit Symbol Value Description Reset value

7:0 SEL Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01.

0x01

15:8 CLKDIV The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.

0

16 BURST 1 The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed.

0

Remark: START bits must be 000 when BURST = 1 or conversions will not start.

0 Conversions are software controlled and require 11 clocks.

15


19:17 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the RESULT bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).

000

000 11 clocks / 10 bits

001 10 clocks / 9bits







20 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

21 PDN 1 The A/D converter is operational. 0

0 The A/D converter is in power-down mode.

23:22 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

A/D Global Start Register

Software can write this register to simultaneously initiate conversions on both A/D controllers. This

register is available in LPC2144/6/8 devices only.

16


A/D Status Register

The A/D Status register allows checking the status of all A/D channels simultaneously. The

DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel are mirrored in

ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found in ADSTAT.

Bit Symbol Description Reset value

0 DONE0 This bit mirrors the DONE status flag from the result register for A/D channel 0. 0








8 OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. 0








16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.

0

17


31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

A/D Interrupt Enable Register

This register allows control over which A/D channels generate an interrupt when a conversion is

complete. For example, it may be desirable to use some A/D channels to monitor sensors by

continuously performing conversions on them. The most recent results are read by the application

program whenever they are needed. In this case, an interrupt is not desirable at the end of each

conversion for some A/D channels.


0 ADINTEN0 0 Completion of a conversion on ADC channel 0 will not generate an interrupt. 0

1 Completion of a conversion on ADC channel 0 will generate an interrupt.







Bit Symbol Value Description Reset value4 ADINTEN4 0 Completion of a conversion on ADC channel 4 will not generate an interrupt. 0


5 ADINTEN5 0 Completion of a conversion on ADC channel 5 will not generate an interrupt. 01 Completion of a conversion on ADC channel 5 will generate an interrupt.



8 ADGINTEN 0 Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.

11 Only the global DONE flag in ADDR is enabled to generate an interrupt.

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

NA

A/D Data Registers

The A/D Data Register hold the result when an A/D conversion is complete, and also

include the flags that indicate when a conversion has been completed and when a conversion

overrun has occurred.

18


Operation:

Hardware-triggered conversion:

If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will

start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices

include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of

either of 2 Capture/Match pins. The pin state from the selected pad or the selected Match signal,

XORed with ADCR bit 27, is used in the edge detection logic.

Interrupts

An interrupt request is asserted to the Vectored Interrupt Controller (VIC) when the DONE

bit is 1. Software can use the Interrupt Enable bit for the A/D Converter in the VIC to control whether

this assertion results in an interrupt. DONE is negated when the ADDR is read.

Accuracy vs. digital receiver

The AD0.n function must be selected in corresponding Pin Select register (see "Pin

Connect Block" on page 58) in order to get accurate voltage readings on the monitored pin. For pin

hosting an ADC input, it is not possible to have a have a digital function selected and yet get valid

ADC readings. An inside circuit disconnects ADC hardware from the associated pin whenever a

digital function is selected on that pin.

19


Suggested ADC interface

It is suggested that RVSI is kept below 40 k ohms

GENERAL PURPOSE INPUT OUTPUT PORTSFeatures

Every physical GPIO port is accessible via either the group of registers providing an enhanced features and accelerated port access or the legacy group of register. Accelerated GPIO functions:

– GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved

– Mask registers allow treating sets of port bits as a group,leaving other bits unchanged

– All registers are byte and half-word addressable– Entire port value can be written in one instruction

Bit-level set and clear registers allow a single instruction set or clear of any number of bits in

one port Direction control of individual bits All I/O default to inputs after reset Backward compatibility with other earlier devices is maintained with legacy registers appearing at the original addresses on the APB bus

Applications:• General purpose I/O• Driving LEDs, or other indicators• Controlling off-chip devices

20


• Sensing digital inputs

PIN Description

GPIO register map (legacy APB accessible registers)

GenericName

Description Access Reset value

PORT0Address & Name

PORT1Address & Name

IOPIN GPIO Port Pin value register. The current state of the GPIO configured port pins can always be read from this register, regardless of pin direction.

IOSET GPIO Port Output Set register. This register controls the state of output pins in conjunction with the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect.

IODIR GPIO Port Direction control register. This register individually controls the direction of each port pin.

IOCLR GPIO Port Output Clear register. This register controls the state of output pins. Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect.

R/W NA 0xE002 8000IO0PIN

R/W 0x0000 0000 0xE002 8004IO0SET

R/W 0x0000 0000 0xE002 8008IO0DIR

WO 0x0000 0000 0xE002 800C IO0CLR

0xE002 8010IO1PIN

0xE002 8014IO1SET

0xE002 8018IO1DIR

0xE002 801C IO1CLR

21

Table 66. GPIO register map (local bus accessible registers - enhanced GPIO features)

GenericName

Description Access Reset value

PORT0Address & Name

PORT1Address & Name

FIODIR Fast GPIO Port Direction control register.This register individually controls the direction of each port pin.

FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to port (done via writes to FIOPIN, FIOSET, and FIOCLR, and reads of FIOPIN) alter or return only the bits loaded with zero in this register.

FIOPIN Fast Port Pin value register using FIOMASK.

The current state of digital port pins can be read from this register, regardless of pin direction or alternate function selection (as long as pin is not configured as an input to ADC). The value read is value of the physical pins masked by ANDing the inverted FIOMASK. Writing to this register affects only port bits enabled by ZEROES in FIOMASK.

FIOSET Fast Port Output Set register using FIOMASK. This register controls the state of output pins. Writing 1s produces highs at the corresponding port pins. Writing 0s has no effect. Reading this register returns the current contents of the port output register. Only bits enabled by ZEROES in FIOMASK can be altered.

FIOCLR Fast Port Output Clear register using FIOMASK. This register controls the state of output pins. Writing 1s produces lows at the corresponding port pins. Writing 0s has no effect. Only bits enabled by ZEROES in FIOMASK can be altered.

R/W 0x0000 0000 0x3FFF C000FIO0DIR

R/W 0x0000 0000 0x3FFF C010FIO0MASK

R/W 0x0000 0000 0x3FFF C014FIO0PIN

R/W 0x0000 0000 0x3FFF C018FIO0SET

WO 0x0000 0000 0x3FFF C01C FIO0CLR

0x3FFF C020FIO1DIR

0x3FFF C030FIO1MASK

0x3FFF C034FIO1PIN

0x3FFF C038FIO1SET

0x3FFF C03C FIO1CLR

22

GPIO port Direction register (IODIR)

This word accessible register is used to control the direction of the pins when

they are configured as GPIO port pins. Direction bit for any pin must be set according

to the pin functionality.

Legacy registers are the IO0DIR and IO1DIR, while the enhanced GPIO

functions are supported via the FIO0DIR and FIO1DIR registers.

GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description


31:0 P0xDIR

0

Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.

Controlled pin is input.

0x0000 0000

1 Controlled pin is output.

GPIO port 1 Direction register (IO1DIR - address 0xE002 8018) bit description


31:0 P1xDIR Slow GPIO Direction control bits. Bit 0 in IO1DIR controls P1.0 ... Bit 30 inIO1DIR controls P1.30.

0x0000 0000

0 Controlled pin is input.

1 Controlled pin is output.

LPC2148 Pin connect block

FeaturesAllows individual pin configuration.

ApplicationsThe purpose of the Pin connect block is to configure the

microcontroller pins to the desired functions.

Description

The pin connect block allows selected pins of the

microcontroller to have more than one function. Configuration registers control the

multiplexers to allow connection between the pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated, and

1

prior to any related interrupt(s) being enabled. Activity of any enabled peripheral

function that is not mapped to a related pin should be considered undefined.

Selection of a single function on a port pin completely excludes all other

functions otherwise available on the same pin.

The only partial exception from the above rule of exclusion is the case of

inputs to the A/D converter. Regardless of the function that is selected for the port pin

that also hosts the A/D input, this A/D input can be read at any time and variations of

the voltage level on this pin will be reflected in the A/D readings. However, valid

analog reading(s) can be obtained if and only if the function of an analog input is

selected. Only in this case proper interface circuit is active in between the physical pin

and the A/D module. In all other cases, a part of digital logic necessary for the digital

function to be performed will be active, and will disrupt proper behavior of the A/D.

Register description

The Pin Control Module contains 2 registers as shown in table below.

Pin connect block register mapName Description Access Reset value Address

PINSEL0 Pin function select register 0.

Read/Write 0x0000 0000 0xE002 C000

PINSEL1 Pin function select register 1.

Read/Write 0x0000 0000 0xE002 C004

PINSEL2 Pin function select Read/Write 0xE002 C014register 2.

2

LPC2148 pin

Power Supply

The input to the circuit is applied from the regulated power supply. The A.C.

input i.e., 230V from the mains supply is step down by the transformer to 12V and is fed

to a rectifier. The output obtained from the rectifier is a pulsating D.C voltage. So in

order to get a pure D.C voltage, the output voltage from the rectifier is fed to a filter to

remove any A.C components present even after rectification. Now, this voltage is given

to a voltage regulator to obtain a pure constant dc voltage. The block diagram of

regulated power supply is shown in the figure 3.2

3

Fig 3.2 components of power supply

Transformer:

Usually, DC voltages are required to operate various electronic equipment and

these voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus

the A.C input available at the mains supply i.e., 230V is to be brought down to the

required voltage level. This is done by a transformer. Thus, a step down transformer is

employed to decrease the voltage to a required level.

Rectifier:

The output from the transformer is fed to the rectifier. It converts A.C. into

pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a

bridge rectifier is used because of its merits like good stability and full wave rectification.

Filter:

Capacitive filter is used in this project. It removes the ripples from the output of

rectifier and smoothens the D.C. Output received from this filter is constant until the

mains voltage and load is maintained constant. However, if either of the two is varied,

D.C. voltage received at this point changes. Therefore a regulator is applied at the output

stage.

4

Voltage regulator:

As the name itself implies, it regulates the input applied to it. A voltage regulator

is an electrical regulator designed to automatically maintain a constant voltage level. In

this project, power supply of 5V and 12V are required. In order to obtain these voltage

levels, 7805 and 7812 voltage regulators are to be used. The first number 78 represents

positive supply and the numbers 05, 12 represent the required output voltage levels.

LM 35

LM35 is a precision IC temperature sensor with its output proportional to the

temperature (in oC). The sensor circuitry is sealed and therefore it is not subjected to

oxidation and other processes. With LM35, temperature can be measured more accurately

than with a thermistor. It also possess low self heating and does not cause more than

0.1oC temperature rise in still air. The operating temperature range is from -55°C to

150°C. The output voltage varies by 10mV in response to every oC rise/fall in ambient

temperature, i.e., its scale factor is 0.01V/ oC.

Pin No Function Name1 Supply voltage; 5V (+35V to -2V) VCC2 Output voltage (+6V to -1V) Output

5

LDR:

An LDR (Light dependent resistor), as its name suggests, offers resistance in

response to the ambient light. The resistance decreases as the intensity of incident light

increases, and vice versa. In the absence of light, LDR exhibits a resistance of the order

of mega-ohms which decreases to few hundred ohms in the presence of light. It can act as

a sensor, since a varying voltage drop can be obtained in accordance with the varying

light. It is made up of Cadmium Sulphide (CdS). An LDR has a zigzag cadmium sulphide

track. It is a bilateral device, i.e., conducts in both directions in same fashion.

Humidity Sensor

Humidity sensor works on the principle of relative humidity and gives the output

in the form of voltage. This analog voltage provides the information about the percentage

6

relative humidity present in the environment. A miniature sensor consisting of a RH

sensitive material deposited on a ceramic substrate. The AC resistance (impedance) of the

sensor decreases as relative humidity increases.

The relative humidity is defined as:

The analog output of sensor is connected to ADC to get its corresponding digital

value. For calibration of digital values, the reference voltage of ADC is set to 1.5 volts.

The digital values are received at port of microcontroller.

These digital values are used to calculate percentage relative humidity of

environment. The calculated data is sent to LCD to display the percentage relative

humidity. High sensitivity and reliability in a small package - Fast response time, High

resistance to chemicals and contaminants enclosed in a moulded, cream coloured body

5mm pitch terminations.

7

Technical Specification

AC resistance value 25°C

RH % Value kΩ

30 920

40 220

50 66

60 23

70 9.6

80 4.2

90 1.9

Humidity range 30 to 90% RH

Rated voltage 1.4 V AC pk

Rated power 0.26 mW pk

Frequency range 50Hz to 1kHz

AC resistance value 25°C RH % Value kΩ

8

Accuracy ±3% RH 60% RH, 25°C

Hysteresis –3% RH 40-80% RH

Temperature dependence 0.5% RH/°C

Response time 60s

Operating temperature 0°C to +60°C

GSM Technology

9

Introduction:

Time-Division Multiple Access (TDMA)

What is TDMA?

TDMA (time division multiple access) is a technology used in digital cellular

telephone communication to divide each cellular channel into three time slots in order to

increase the amount of data that can be carried.

How it Works?

TDMA works by time-division multiplexing: sending multiple signals (each of

which has its own time slot) simultaneously on a single carrier in the form of a complex

signal, and then recovering the separate signals at the receiving end. For TDMA, the

carrier is divided into three time slots, each of which serves one subscriber. The

information is broken into tiny data packets, which are transmitted in timed bursts in the

30-megahertz range. At the receiving end, the separate information streams are

recovered. See also FDMA (frequency division multiple access) and CDMA (code-

division multiple access).

TDMA was developed in response to the basic wireless network problem:

large numbers of users and limited frequency allotments. TDMA increases network

efficiency by enabling single connections to carry multiple data channels, offering a

three-fold increase in capacity over Advanced Mobile Phone Service (AMPS) networks.

Flexible and scalable, TDMA facilitates step-by-step migration to digital operation.

TDMA can be implemented seamlessly across both 800- and 1900-MHz networks. Its

hierarchical cell structure allows service providers to increase capacity where demand is

greatest, in high-use areas.

TDMA is applied in Digital-American Mobile Phone Service, Global

System for Mobile communications, and Personal Digital Cellular (PDC). However, each

of these systems implements TDMA in a somewhat different and incompatible way.

TDMA was first specified as a standard in EIA/TIA Interim Standard 54 (IS-54). IS-136,

an evolved version of IS-54, is the United States standard for TDMA for both the cellular

10

(850 MHz) and personal communications services (1.9 GHz) spectrums. TDMA is also

used for Digital Enhanced Cordless Telecommunications.

Code Division Multiple Access (CDMA):

The term CDMA refers to any of several protocols used in so-called

second-generation (2G) and third-generation (3G) wireless communications. As the term

implies, CDMA is a form of multiplexing, which allows numerous signals to occupy a

single transmission channel, optimizing the use of available bandwidth. The technology

is used in ultra-high-frequency (UHF) cellular telephone systems in the 800-MHz and

1.9-GHz bands. CDMA employs analog-to-digital conversion (ADC) in combination

with spread spectrum technology. Audio input is first digitized into binary elements. The

frequency of the transmitted signal is then made to vary according to a defined pattern

(code), so it can be intercepted only by a receiver whose frequency response is

programmed with the same code, so it follows exactly along with the transmitter

frequency. There are trillions of possible frequency-sequencing codes; this enhances

privacy and makes cloning difficult.

The CDMA channel is nominally 1.23 MHz wide. CDMA networks use a

scheme called soft handoff, which minimizes signal breakup as a handset passes from one

cell to another. The combination of digital and spread-spectrum modes supports several

times as many signals per unit bandwidth as analog modes. CDMA is compatible with

other cellular technologies; this allows for nationwide roaming. The original CDMA

standard, also known as CDMA One and still common in cellular telephones in the U.S.,

offers a transmission speed of only up to 14.4 KBPS in its single channel form and up to

115 KBPS in an eight-channel form. CDMA2000 and wideband CDMA deliver data

many times faster

.

Global System for Mobile communication (GSM):

What is GSM?

The Global System for Mobile communication, usually called GSM,

Telecommunications Standards Institute (ETSI) to describe protocols for second

generation (2G) digital cellular networks used by mobile phones. The GSM standard was

developed as a replacement for first generation (1G) analog cellular networks, and

11

originally described a digital, circuit switched network optimized for full duplex voice

telephony. This was expanded over time to include data communications, first by circuit

switched transport, then packet data transport via GPRS (General Packet Radio Services)

and EDGE (Enhanced Data rates for GSM Evolution or EGPRS). Further improvements

were made when the 3GPP developed third generation (3G) UMTS standards followed

by fourth generation (4G)LTE Advanced standards. "GSM" is a trademark owned by the

GSM Association.GSM is a cellular network, which means that mobile phones connect to

it by searching for cells in the immediate vicinity.

The ubiquity of the GSM standard makes international roaming very

common between mobile phone operators, enabling subscribers to use their phones in

many parts of the world. GSM differs significantly from its predecessors in that both

signalling and speech channels are Digital call quality, which means that it is considered

a second generation (2G) mobile phone system. This fact has also meant that data

communication was built into the system from the 3rd Generation Partnership Project

(3GPP).

GSM is a digital mobile telephone system that is widely used in Europe

and other parts of the world. GSM uses a variation of time division multiple access (Time

Division Multiple Access) and is the most widely used of the three digital wireless

telephone technologies (TDMA, GSM, and CDMA). GSM digitizes and compresses data,

then sends it down a channel with two other streams of user data, each in its own time

slot. It operates at either the 900 MHz or 1800 MHz frequency band.

12

GSM is the de facto wireless telephone standard in Europe. GSM has over

120 million users worldwide and is available in 120 countries, according to the GSM

MOU Association. Since many GSM network operators have roaming agreements with

foreign operators, users can often continue to use their mobile phones when they travel to

other countries.

American Personal Communications (APC), a subsidiary of Sprint, is

using GSM as the technology for a broadband personal communications service (personal

communications services). The service will ultimately have more than 400 base stations

for the palm-sized handsets that are being made by Ericsson, Motorola, and Nokia. The

handsets include a phone, a text pager, and an answering machine.

GSM together with other technologies is part of an evolution of wireless mobile

telecommunication that includes High-Speed Circuit-Switched Data (High-Speed Circuit-

Switched Data), General Packet Radio System (General Packet Radio Services),

Enhanced Data GSM Environment (Enhanced Data GSM Environment), and Universal

Mobile Telecommunications Service (Universal Mobile Telecommunications System).

The Generations of Mobile Networks

The idea of cell-based mobile radio systems appeared at Bell Laboratories

in the United States in the early 1970s. However, mobile cellular systems were not

introduced for commercial use until a decade later. During the early 1980’s, analog

cellular telephone systems experienced very rapid growth in Europe, particularly in

Scandinavia and the United Kingdom. Today, cellular systems still represent one of the

fastest growing telecommunications systems. During development, numerous problems

arose as each country developed its own system, producing equipment limited to operate

only within the boundaries of respective countries, thus limiting the markets in which

services could be sold.

First-generation cellular networks, the primary focus of the communications

industry in the early 1980’s, were characterized by a few compatible systems that were

designed to provide purely local cellular solutions. It became increasingly apparent that

there would be an escalating demand for a technology that could facilitate flexible and

13

reliable mobile communications. By the early 1990’s, the lack of capacity of these

existing networks emerged as a core challenge to keeping up with market demand. The

first mobile wireless phones utilized analog transmission technologies, the dominant

analog standard being known as “AMPS”, (Advanced Mobile Phone System). Analog

standards operated on bands of spectrum with a lower frequency and greater wavelength

than subsequent standards, providing a significant signal range per cell along with a high

propensity for interference. Nonetheless, it is worth noting the continuing persistence of

analog (AMPS) technologies in North America and Latin America through the 1990’s.

Initial deployments of second-generation wireless networks occurred in Europe in

the 1980’s. These networks were based on digital, rather than analog technologies, and

were circuit-switched. Circuit-switched cellular data is still the most widely used mobile

wireless data service. Digital technology offered an appealing combination of

performance and spectral efficiency (in terms of management of scarce frequency bands),

as well as the development of features like speech security and data communications over

high quality transmissions. It is also compatible with Integrated Services Digital

Network (ISDN) technology, which was being developed for land-based

telecommunication systems throughout the world, and which would be necessary for

GSM to be successful. Moreover in the digital world, it would be possible to employ

very large-scale integrated silicon technology to make handsets more affordable.

To a certain extent, the late 1980’s and early 1990’s were characterized by the

perception that a complete migration to digital cellular would take many years, and that

digital systems would suffer from a number of technical difficulties (i.e., handset

technology). However, second-generation equipment has since proven to offer many

advantages over analog systems, including efficient use of radio-magnetic spectrum,

enhanced security, extended battery life, and data transmission capabilities. There are

four main standards for 2G networks: Time Division Multiple Access (TDMA), Global

System for Mobile Communications (GSM) and Code Division Multiple Access

(CDMA); there is also Personal Digital Cellular (PDC), which is used exclusively in

Japan. (See Figure 1.1) In the meantime, a variety of 2.5G standards (to be discussed in

Section 2.7) have been developed. ‘Going digital’ has led to the emergence of several

major 2G mobile wireless systems.

14

History of GSM:

Early European analog cellular networks consisted of a mix of technologies and

protocols that varied from country to country, meaning that phones did not necessarily

work on different networks. In addition, manufacturers had to produce different

equipment to meet various standards across the markets.

In 1982, work began to develop a European standard for digital cellular voice

telephony when the European Conference of Postal and Telecommunications

Administrations (CEPT) created the Group Special Mobile committee and provided a

permanent group of technical support personnel, based in Paris. Five years later in 1987,

15 representatives from 13 European countries signed a memorandum of understanding

in Copenhagen to develop and deploy a common cellular telephone system across

Europe, and European Union rules were passed to make GSM a mandatory standard. The

decision to develop a continental standard eventually resulted in a unified, open,

standard-based network which was larger than that in the United States. In 1989, the

Group Special Mobile committee was transferred from CEPT to the European

Telecommunications Standards Institute(ETSI).

In parallel, France and Germany signed a joint development agreement in 1984

and were joined by Italy and the UK in 1986. In 1986 the European Commission

proposed reserving the 900 MHz spectrum band for GSM.

Phase I of the GSM specifications were published in 1990. The world's first GSM

call was made by the Finnish prime minister Harri Holkeri to Kaarina Suonio (mayor in

city of Tampere) on 1 July 1991 on a network built by Telenokia and Siemens and

operated by Radiolinja. The following year in 1992, the first short messaging service

(SMS or "text message") message was sent and Vodafone UK and Telecom Finland

signed the first international roaming agreement.

Work begun in 1991 to expand the GSM standard to the 1800 MHz frequency

band and the first 1800 MHz network became operational in the UK by 1993. Also that

year, Telecom Australia became the first network operator to deploy a GSM network

outside Europe and the first practical hand-held GSM mobile phone became available.

15

In 1995, fax, data and SMS messaging services were launched commercially, the

first 1900 MHz GSM network became operational in the United States and GSM

subscribers worldwide exceeded 10 million. Also this year, the GSM Association was

formed. Pre-paid GSM SIM cards were launched in 1996 and worldwide GSM

subscribers passed 100 million in 1998.

In 2000, the first commercial GPRS services were launched and the first GPRS

compatible handsets became available for sale. In 2001 the first UMTS (W-CDMA)

network was launched and worldwide GSM subscribers exceeded 500 million. In 2002

the first multimedia messaging services (MMS) were introduced and the first GSM

network in the 800 MHz frequency band became operational. EDGE services first

became operational in a network in 2003 and the number of worldwide GSM subscribers

exceeded 1 billion in 2004.

By 2005, GSM networks accounted for more than 75% of the worldwide cellular

network market, serving 1.5 billion subscribers. In 2005, the first HSDPA capable

network also became operational. The first HSUPA network was launched in 2007 and

worldwide GSM subscribers exceeded two billion in 2008.

The GSM Association estimates that technologies defined in the GSM standard

serve 80% of the global mobile market, encompassing more than 5 billion people across

more than 212 countries and territories, making GSM the most ubiquitous of the many

standards for cellular networks.

Macau phased out their GSM network in January 2013 (except for roaming

services), making it the first region to decommission a GSM network.

Architecture of the GSM network

A GSM network is composed of several functional entities, whose functions and

interfaces are specified. Figure 1 shows the layout of a generic GSM network. The GSM

network can be divided into three broad parts. The Mobile Station is carried by the

subscriber. The Base Station Subsystem controls the radio link with the Mobile Station.

The Network Subsystem, the main part of which is the Mobile services Switching Center

(MSC), performs the switching of calls between the mobile users, and between mobile

16

and fixed network users. The MSC also handles the mobility management operations.

The Mobile Station and the Base Station Subsystem communicate across the Um

interface, also known as the air interface or radio link. The Base Station Subsystem

communicates with the Mobile services Switching Center across the A interface.

Figure . General architecture of a GSM network

Mobile Station

The mobile station (MS) consists of the mobile equipment (the terminal) and a

smart card called the Subscriber Identity Module (SIM). The SIM provides personal

mobility, so that the user can have access to subscribed services irrespective of a specific

terminal. By inserting the SIM card into another GSM terminal, the user is able to receive

calls at that terminal, make calls from that terminal, and receive other subscribed

services.

The mobile equipment is uniquely identified by the International Mobile

Equipment Identity (IMEI). The SIM card contains the International Mobile Subscriber

Identity (IMSI) used to identify the subscriber to the system, a secret key for

authentication, and other information. The IMEI and the IMSI are independent, thereby

17

allowing personal mobility. The SIM card may be protected against unauthorized use by

a password or personal identity number.

Base Station Subsystem

The Base Station Subsystem is composed of two parts, the Base Transceiver

Station (BTS) and the Base Station Controller (BSC). These communicate across the

standardized Abis interface, allowing (as in the rest of the system) operation between

components made by different suppliers.

The Base Transceiver Station houses the radio transceivers that define a cell and

handles the radio-link protocols with the Mobile Station. In a large urban area, there will

potentially be a large number of BTSs deployed, thus the requirements for a BTS are

ruggedness, reliability, portability, and minimum cost.

The Base Station Controller manages the radio resources for one or more BTSs. It

handles radio-channel setup, frequency hopping, and handovers. The BSC is the

connection between the mobile station and the Mobile service Switching Center (MSC).

Network Subsystem

The central component of the Network Subsystem is the Mobile services

Switching Center (MSC). It acts like a normal switching node of the PSTN or ISDN, and

additionally provides all the functionality needed to handle a mobile subscriber, such as

registration, authentication, location updating, handovers, and call routing to a roaming

subscriber. The MSC provides the connection to the fixed networks (such as the PSTN or

ISDN). Signaling between functional entities in the Network Subsystem uses Signaling

System Number 7 (SS7), used for trunk signaling in ISDN and widely used in current

public networks.

The Home Location Register (HLR) and Visitor Location Register (VLR),

together with the MSC, provide the call-routing and roaming capabilities of GSM. The

HLR contains all the administrative information of each subscriber registered in the

corresponding GSM network, along with the current location of the mobile. The location

of the mobile is typically in the form of the signaling address of the VLR associated with

18

the mobile station. There is logically one HLR per GSM network, although it may be

implemented as a distributed database.

The Visitor Location Register (VLR) contains selected administrative information

from the HLR, necessary for call control and provision of the subscribed services, for

each mobile currently located in the geographical area controlled by the VLR. The

geographical area controlled by the MSC corresponds to that controlled by the VLR.

Note that the MSC contains no information about particular mobile stations --- this

information is stored in the location registers.

The other two registers are used for authentication and security purposes. The

Equipment Identity Register (EIR) is a database that contains a list of all valid mobile

equipment on the network, where each mobile station is identified by its International

Mobile Equipment Identity (IMEI). An IMEI is marked as invalid if it has been reported

stolen or is not type approved. The Authentication Center (AuC) is a protected database

that stores a copy of the secret key stored in each subscriber's SIM card, which is used for

authentication and encryption over the radio channel.

GSM frequencies using around the world

In North America, GSM operates on the primary mobile communication bands

850 MHz and 1,900 MHz. In Canada, GSM-1900 is the primary band used in urban areas

with 850 as a backup, and GSM-850 being the primary rural band. In the United States,

regulatory requirements determine which area can use which band.

GSM-1900 and GSM-850 are also used in most of South and Central America,

and both Ecuador and Panama use GSM-850 exclusively (Note: Since November 2008, a

Panamanian operator has begun to offer GSM-1900 service). Venezuela and Brazil use

GSM-850 and GSM-900/1800 mixing the European and American bands. Some

countries in the Americas use GSM-900 or GSM-1800, some others use three: GSM-

850/900/1900, GSM-850/1800/1900, GSM-900/1800/1900 or GSM-850/900/1800. Soon

some countries will use GSM-850/900/1800/1900 MHz like the Dominican Republic,

Trinidad & Tobago and Venezuela.

In Brazil, the 1,900 MHz band is paired with 2,100 MHz to form the IMT-

compliant 2,100 MHz band for 3G services. The result is a mixture of usage in the

19

Americas that requires travelers to confirm that the phones they have are compatible with

the band of the networks at their destinations. Frequency compatibility problems can be

avoided through the use of multi-band (tri-band or, especially, quad-band) phones.

Africa, Europe, Middle East and Asia

In Africa, Europe, Middle East and Asia, most of the providers use 900 MHz and

1800 MHz bands. GSM-900 is most widely used. Fewer operators use DCS-1800 and

GSM-1800. A dual-band 900/1800 phone is required to be compatible with almost all

operators. At least the GSM-900 band must be supported in order to be compatible with

many operators. However, Thailand has also approved for some time now the use of the

GSM-1900 band in an attempt to alleviate network congestion.

GSM SECURITY

The security features in the GSM network can be divided into three sub parts:

subscriber identity authentication, user and signaling data confidentiality, and subscriber

identity confidentiality. The security mechanisms include secret keys, algorithms and

computed numbers.

20

Some definitions:

Authentication – any technique that enables the receiver to automatically

identify and reject messages that have been altered deliberately or by channel errors

Confidentiality – only the sender and intended receiver should be able to

understand the contents of the transmitted message.

Cipher text – plaintext is encrypted to cipher text with the help of a key

and an encryption algorithm

Key – a string of numbers or characters as input to the encryption

algorithm

The base mechanism shows where the different keys and algorithms are stored. The

secret key Ki is used to authenticate the identity of a subscriber. The key Ki is given to

the subscriber when he opens a new network account. Only the network operator knows

the key. The Ki is stored in the subscribers SIM card and the authentication center (AuC)

of the subscribers home network. The Ki is never transmitted over the network.A3 is the

algorithm used to authenticate the subscriber. Data transmitted between the MS (Mobile

Station) and the BTS (Base Transceiver Station) is encrypted by the A5 algorithm. The

A8 algorithm generates the needed ciphering key Kc used by A5.

Subscriber Identity Authentication. The procedure consists of three phases, (1) the

network must identify the subscriber, (2) needed security parameters from the home

network are asked for and (3) the actual authentication is taking place.

21

Fig.: Base of the Security System

Fig.: Subscriber identification process.

In order to identify the subscriber the MS sends the IMSI (International Mobile

Subscriber Identity) to the visited network. With the IMSI the subscriber is identified to

the system. The IMSI is up to 15 digits and comprises the following parts:

• A 3-digit Mobile Country Code (MCC). This identifies the country where the

GSM system operates. Finland has number 244.

• A 2-digit Mobile Network Code (MNC). This uniquely identifies each cellular

provider. Sonera has number 91.

• The Mobile Subscriber Identification Code (MSIC).This uniquely identifies each

customer of the provider. The length is 10 digits. So called security triplets are calculated

22

in the AuC. The triplets consist of a random number (RAND), a signed response (SRES)

and a ciphering key (Kc). The SRES is used to authenticate the subscriber and Kc is used

as input by the ciphering algorithm A5.

Fig. Calculating the security triplets.

As the visited network has received the security triplets the actual authentication

can take place (see Figure 5). If the number sent by the MS to the BTS is the same as the

one calculated by the AuC, the subscriber is authenticated.

Figure.: Authentication the subscriber

23

User and Signaling Data Confidentiality: The Ciphering key (Kc) is

used for the final encryption of the radio link. One copy of the needed Kc is stored in the

VLR and another copy is calculated in the MS by the A8 algorithm. The same Ki and

RAND numbers are used as in the authentication process. The A5 algorithm creates 114-

bit sequence. This sequence is then XORed with every 114 user data bits and the

resulting bit streams are sent over the two 57 bit parts of every GSM slot. All traffic

between the MS and the BTS is then secured.

Subscriber Identity Confidentiality: The IMSI is the primary key for

subscriber identification. However a temporary identity, TMSI (Temporary Mobile

Subscriber Identity) can be given to a subscriber for identification. After initial

registration done with the IMSI, the serving network stores the IMSI in the VLR and

generates a TMSI for the subscriber. The TMSI is then transmitted back to the MS and it

will be used for identification as long as the subscriber is registered in that specific

network.

Solutions to Current Security Issues: A corrected version of the COMP

128 has been developed; however, the cost to replace all SIM chips and include the new

algorithm is too costly to cellular phone companies. The new release of 3GSM will

include a stronger version of the COMP 128 algorithm and a new A5 algorithm

implementation. The A5/3 is expected to solve current confidentiality and integrity

problems [4]. Fixed network transmission could be fixed by simply applying some type

of encryption to any data transferred on the fixed network.

Channel structure: Depending on the kind of information transmitted (user

data and control signaling), we refer to different logical channels which are mapped

under physical channels (slots). Digital speech is sent on a logical channel named TCH,

which during the transmission can be a allocated to a certain physical channel. In a GSM

system no RF channel and no slot is dedicated to a priori to the exclusive use of anything

(any RF channel can be used for number of different uses).

Logical channels are divided into two categories:

i) Traffic Channels (TCHs)

24

ii)Control Channels .

Traffic Channels (TCHs) A traffic channel (TCH) is used to carry speech

and data traffic. Traffic channels are defined using a 26-frame multiform, or group of 26

TDMA frames. The length of a 26-frame multiform is 120 ms, which is how the length of

a burst period is defined (120 ms divided by 26 frames divided by 8 burst periods per

frame). Out of the 26 frames, 24 are used for traffic, 1 is used for the Slow Associated

Control Channel (SACCH) and 1 is currently unused. TCHs for the uplink and downlink

are separated in time by 3 burst periods, so that the mobile station does not have to

transmit and receive simultaneously, thus simplifying the electronics

TCHs carry either encoded speech or user data in both up and down

directions in a point to point communication.

There are two types of TCHs that are differentiated by their traffic rates.

They are:

i. Full Rate TCH

ii. Half Rate TCH

Full Rate TCH(Also represented as Bm)

It carries information at a gross rate of 22.82 KBPS.

Half Rate TCH

It carries information with half of full rate channels.

Control Channel

Basic structure of Control channel

1 2 3 4 . . . . . 1

0

11 . . . . . 21 26

F S x X X X X X X X F S X X X X X X X X F S X X X X X

25

Actually in the above diagram S will be at slot 1 of next frame, F is frequency

correction channel which occurs every 10th burst. The next frame to S contains

service operator’s information.

Logical Control Channel (LCC) s are of three types

They are of the following types:

•Broadcast Control Channel(BCCH)

•Common Control Channel(CCCH)

• Dedicated Control Channel(DCCH)

Broadcast Control Channel (BCCH)

The BCCH is a point-to-multipoint unidirectional control channel from the

fixed subsystem to MS that is intended to broadcast a variety of information to

MSs, including information necessary for the MS to register in the system. BCCH

has 51 bursts. BCCH is dedicated to slot1 and repeats after every 51 bursts.

Broadcast Control Channel (BCCH) continually broadcasts, on the

downlink, information including base station identity, frequency allocations, and

frequency-hopping sequences. This provides general information per BTS basis

(cell specific information) including information necessary for the MS to register

at the system. After initially accessing the mobile, the BS calculates the requires

MS power level and sets a set of power commands on these channels. Other

information sent over these channels includes country code network code, local

code, PLMN code, RF channels used within the cell where the mobile is located,

and surrounding cells, hopping sequence number, mobile RF channel number for

allocation, cell selection parameters, and RACH description. One of the

important messages on a BCCH channel is CCCH_CONF, which indicates the

organization of the CCCHs. This channel is used to down link point-to-multipoint

communication and is unidirectional; there is no corresponding uplink. The signal

strength is continuously measured by all mobiles which may seek a hand over

from its present cell and thus it is always transmitted on designated RF channel

26

using time slot 0(zero). This channel is never kept idle-either the relevant

messages are sent or a dummy burst is sent.

The BCCH includes Frequency correction channel (FCCH) which is used to

allow an MS to accurately tune to a BS. The FCCH carries information for the

frequency correction of MS downlink. It is required for the correct operation of

radio system. This is also a point-to multipoint communication. This allows an

MS to accurately tune to a BS.

-- Synchronization channel (SCH), which is used to provide TDMA frame

oriented synchronization data to a MS. When a mobile recovers both FCCH and

SCH signals, the synchronization is said to be complete. SCH repeats for every 51

frames. SCH carries information for the frame synchronization (TDMA frame

number of the MS and the identification of BTS ) .This is also required for the

correct operation of the mobile.

The Synchronization Channel contains 2 encoded parameters:

•BTS identification code (BSIC)

•Reduced TDMA frame number (RFN).

Common Control Channel (CCCH)

A CCCH is a point-to-multipoint (bi-directional control channel) channel

that is primarily intended to carry signaling information necessary for access

management functions (e.g., allocation of dedicated control channels).

The CCCH includes:

-- paging channel (PCH), which is used to search (page) the MS in the downlink

direction

-- random access channel (RACH) which is used by MS to request of an SDCCH

either as a page response from MS or call origination/ registration from the MS.

This is uplink channel and operates in point-point mode(MS to BTS).This uses

slotted ALOHA protocol. This causes a possibility of contention. If the mobiles

27

request through this channel is not answered within a specified time the MS

assumes that a collision has occurred and repeats the request. Mobile must allow a

random delay before re-initiating the request to avoid repeated collision.

-- access grant channel(AGCH) which is a downlink channel used to assign a MS

to a specific SDCCH or a TCH. AGCH operates in point-to-point mode. A

combined paging and access grant channel is designated as PAGCH.

Dedicated Control Channel (DCCH)

A DCCH is a point to point, directional control channel.

Two types of DCCHs used are:

Standalone DCCH (SDCCH) is used for system signaling during idle periods and

call setup before allocating a TCH, for example MS registration, authentication

and location updates through this channel. When a TCH is assigned to MS this

channel is released. Its data rate is one-eighth of the full rate speech channel

which is achieved by transmitting data over the channel once every eighth frame.

The channel is used for uplink and downlink and is meant for point-to-point

usage.

Associated Control Channel (ACCH) is a DCCH whose allocation is

linked to the allocation of a CCH. A FACCH or burst stealing is a DCCH

obtained by pre-emptive dynamic multiplexing on a TCH.

SACCH is data channel carrying information such as measurement reports from

the mobile of received signal strength for a serving cell as well as the adjacent

cells. This is necessary channel for the assisted over hand over function.

SACCH is also used for power regulation of MS and time alignment and is meant

for uplink and down link. It is used for point-to-point communication. SACCH

can be linked to TCH or an SDCCH. A FACCH is also associated to

TCH .FACCH works in a stealing mode. This means that if suddenly during a

speech transmission it is necessary to exchange signaling information with the

system at a rate much higher than the SACCH can handle, then 20 ms speech

(data) bursts are stolen for signaling purposes. This is the case at the case at the

28

hand over. The interruption of the speech will not be heard by the user since it

lasts only for 20 ms and cannot sense by human ears.

Data Transmission

The GSM standard also provides separate facilities for transmitting digital

data. This allows a mobile phone to act like any other computer on the Internet,

sending and receiving data via the Internet Protocol. The mobile may also be

connected to a desktop computer, laptop, or PDA, for use as a network interface

(just like a modem or Ethernet card, but using one of the GSM data protocols

described below instead of a PSTN-compatible audio channel or an Ethernet link

to transmit data). Some GSM phones can also be controlled by a standardised

Hayes AT command set through a serial cable or a wireless link (using IRDA or

Bluetooth). The AT commands can control anything from ring tones to data

compression algorithms. In addition to general Internet access, other special

services may be provided by the mobile phone operator, such as SMS.

Circuit-switched data protocols

A circuit-switched data connection reserves a certain amount of

bandwidth between two points for the life of a connection, just as a traditional

phone call allocates an audio channel of a certain quality between two phones for

the duration of the call. Two circuit-switched data protocols are defined in the

GSM standard: Circuit Switched Data (CSD) and High-Speed Circuit-Switched

Data (HSCSD). These types of connections are typically charged on a per-second

basis, regardless of the amount of data sent over the link. This is because a certain

amount of bandwidth is dedicated to the connection regardless of whether or not it

is needed. Circuit-switched connections do have the advantage of providing a

constant, guaranteed quality of service, which is useful for real-time applications

like video conferencing.

29

General Packet Radio Service (GPRS)

The General Packet Radio Service (GPRS) is a packet-switched data

transmission protocol, which was incorporated into the GSM standard in 1997. It

is backwards-compatible with systems that use pre-1997 versions of the standard.

GPRS does this by sending packets to the local mobile phone mast (BTS) on

channels not being used by circuit-switched voice calls or data connections.

Multiple GPRS users can share a single unused channel because each of them

uses it only for occasional short bursts. The advantage of packet-switched

connections is that bandwidth is only used when there is actually data to transmit.

This type of connection is thus generally billed by the kilobyte instead of by the

second, and is usually a cheaper alternative for applications that only need to send

and receive data sporadically, like instant messaging.

Short Message Service (SMS)

Short Message Service (more commonly known as text

messaging) has become the most used data application on mobile phones, with

74% of all mobile phone users worldwide already as active users of SMS, or 2.4

billion people by the end of 2007. SMS text messages may be sent by mobile

phone users to other mobile users or external services that accept SMS. The

messages are usually sent from mobile devices via the Short Message Service

Centre using the MAP protocol. The SMSC is a central routing hubs for Short

Messages. Many mobile service operators use their SMSCs as gateways to

external systems, including the Internet, incoming SMS news feeds, and other

mobile operators (often using the de facto SMPP standard for SMS exchange).

30

STRUCTURE OF TDMA SLOT WITH A FRAME:

There are five different kinds of bursts in the GSM system.

They are

• Normal Burst

• Synchronization Burst

• Frequency Correction Burst

• Access Burst

• Dummy Burst

Normal Burst

This burst is used to carry information on the TCH and on control

channels. The lowest bit number is transmitted first. The encrypted bits are 57

bits of data or (speech + 1 bit stealing flag) indicating whether the burst was

stolen for FACCH signaling or not. The reason why the training sequence is

placed in the middle is that the channel is constantly changing. By having it there,

the chances are better that the channel is not too different when it affects the

training sequence compared to when the information bits were affected. If the

training sequence is put at the beginning of the burst, the channel model that is

created might not be valid for the bits at the end of a burst there are 8 training

sequences shown at the diagram. The 26 bits equalization patterns are determined

at the time of the call setup.

Tail Bits (TB) always equal (0,0,0), which has bit location from 0 to 2 and 145 to

147 . The Guard Period are the empty spaced bits and are used to synchronize the

burst with exact accuracy and makes sure that different time slots does not

overlap during transmission.

31

Synchronization Burst

This burst is used for the time synchronization of the mobile. It contains 64 bit

synchronization sequence. The encrypted 78 bits carry information of the TDMA frame

number along with the BSIC. It is broadcast together with the correction burst. The

TDMA frame is broadcast over SCH, in order to protect the user information against

eavesdropping, which is accomplished is ciphering the information before transmitting.

The algorithm that calculates the ciphering key uses a TDMA frame number as one of the

parameters and therefore, every frame must have a frame number. By knowing the

TDMA frame number, the mobile will know what kind of logical channel is being

transmitted on the control channel TS0. BSIC is also used by the mobile to check the

identity of the BTS when making signal strength measurements (to prevent

measurements on co-channel cells).

Frequency Correction Burst

This burst is used for frequency synchronization of the mobile. It is equivalent to

an un-modulated channel with a specific frequency offset. The repetition of these bursts

is called FCCH.

Access Burst

This burst is used for random access and longer GP to protect for burst

transmission from a mobile that does not know the timing advance when it must access

the system. This allows for a distance of 35 km from base to mobile. In case the mobile is

far away from the BTS, the initial burst will arrive late since there is no timing advance

32

on the first burst. The delay must be shorter to prevent it from overlapping a burst in the

adjacent time-slot following this.

Dummy Burst

It is sent from BTS on some occasions as discussed previously which carries no

information and has the format same as the normal burst.

Conclusion for GSM

GSM has many benefits over current cellular systems. The main problem now

involves the COMP 128 algorithm problem. This problem will be solved as newer

technology gets phased in. The lack of extra encryption on the telecommunications

network doesn’t pose as a major problem because any data transfer on there will have the

same security as the current public switched telephone networks. Despite the current

problems more and more cellular companies will switch to GSM based standards. An

estimated one billion subscribers are expected by the end of 2003. As GSM slowly

moves towards 3GSM, more problems and security issues will be resolved.

LCD

LCD (Liquid Crystal Display) screen is an electronic display module and find a

wide range of applications. A 16x2 LCD display is very basic module and is very

commonly used in various devices and circuits. These modules are preferred over seven

segments and other multi segment LEDs. The reasons being: LCDs are economical;

easily programmable; have no limitation of displaying special & even custom characters

(unlike in seven segments), animations and so on.

A 16x2 LCD means it can display 16 characters per line and there are 2 such

lines. In this LCD each character is displayed in 5x7 pixel matrix. This LCD has two

registers, namely, Command and Data. The command register stores the command

instructions given to the LCD. A command is an instruction given to LCD to do a

predefined task like initializing it, clearing its screen, setting the cursor position,

controlling display etc. The data register stores the data to be displayed on the LCD. The

data is the ASCII value of the character to be displayed on the LCD.

33

34

35

Pin No Function Name

1 Ground (0V) Ground

2 Supply voltage; 5V (4.7V – 5.3V) Vcc

3 Contrast adjustment; through a variable resistor VEE

4 Selects command register when low; and data register

when high

Register Select

5 Low to write to the register; High to read from the

register

Read/write

6 Sends data to data pins when a high to low pulse is given Enable

7

8-bit data pins

DB0

8 DB1

9 DB2

10 DB3

11 DB4

12 DB5

13 DB6

14 DB7

15 Backlight VCC (5V) Led+

16 Backlight Ground (0V) Led-

Water Level Sensor

The Water Level Sensor, WLS, is used for continuous measurement of free water

in oil tanks. The sensor is integrated with a Multiple Spot Thermometer (MST). It is also

possible to add a Pt 100 spot element allowing temperature measurements at low levels.

The WLS continuously measures the interface level between water and oil, thereby

providing net inventory for the user. The standard measuring range is 500 mm.

High reliability

The WLS is designed for heavy-duty service and has no moving parts. It is

factory calibrated and requires no field tuning.

Rugged construction

The WLS is designed for difficult applications in a corrosive environment.

Immersed parts are made of acid-proof steel AISI 316, FEP, PTFE and PEEK with 30%

glass. The WLS is welded to the MST to get a hermetic design.

Typical application

The WLS is installed together with an MST to be hung from the top of the tank.

The vertical position is chosen according to the actual bottom water range. It should be

anchored to the tank bottom to ensure a fixed position in case of turbulence. The open

model is suitable for crude oil applications. The closed model is suitable for lighter fuels

such as diesel oil. For highest resolution, the HART communication option is used.

Anchor weights can be mounted in an eye bolt. It can also be mounted above the WLS. In

that case the weight is hollow and fitted on the MST.

36

37

Chapter

Firmware Implementation of the project design

The firmware programmed in LPC2148 is designed to communicate with

accelerometer and operates according to its value. Therefore, the main firmware

programmed can be divided into three parts:

1. Receive the Data from Accelerometer.

2. Analyzing the data

3. Operate the motors according to it.

In this case, we will mention about the proceeding to write program by using C

Language Program that is Keil-CARM. It is used to interpret command under Program

Text Editor of Keil(Keil uVision3). We only mention about the proceeding to configure

Option value for connection commands of interpretation program together by using Keil-

CARM through Keil uVision3. For more detailed commands and functions usage for

writing program by Keil-CARM, user can learn them by self from User’s Manual

command of Keil-CARM. We can summarize the proceeding to configure default values

of Keil uVision3 for using with Keil-CARM as follows;

1. Open program KeiluVision3 that is a program Text Editor of Keil-CARM, it is

used to write C Language Source Code program and the feature of this program is look

like in the picture below.

38

2. Configure default values to interpret commands of uVision3 and can be used with

Program Keil uVision3 and Keil-CARM. Click Project → Components, Environment,

Books… and then select default value for Compiler from the title Select ARM

Development Tools that has 3 modes; Use Keil-CARM Tools, Use GNU Tools and Use

ARM Tools. In this case, we must select “Use Keil ARM Tools”, and then we must

configure position of folder to store default values of program Keil ARM. Generally, it is

in “C:\Keil\ARM\” but if we install Keil in other folder, we must change the format of it

suitably and corresponding with truly usage as in the picture below.

39

3. Create new Project File by using command Project → New Project and then configure

or create position Folder that we want to save new Project File with preferred Project

File name. For example, if we create new Project File named DEMO1 and wants to save

it into Folder named DEMO1; we can configure position of Folder and Project File name

by self. After we configure Project File name in the blank of File Name successfully,

click Save to save new Project File as in the picture below.

40

After we configure new Project File name and save it completely, Program will

wait for user to configure MCU number that is used in the saved Project File. If using

with Board “CP-JR ARM7 USB-LPC2148”, we must configure MCU number to be

LPC2148 from Philips and then select OK as in the picture below.

Example of Using Keil uVision3 to Create Project File of Keil-CARM

After we configure MCU number successfully, in this step, program will wait for

user to confirm copy File Startup of Keil and wants to use it with MCU of Philips in new

Project File or not. Startup File is the part to configure the default value of operation for

MCU; for example, to configure Stack value and to configure value to run for Phase-

Lock-Loop before start running follow by our written program. Otherwise, our written

program must totally be added these commands into operation of MCU by self. File

Startup of Keil-ARM is Assembly Language File that is configured operation values with

41

development set of Keil, so some configurations and default values are different and it

makes Board “CP-JR ARM7 USB-LPC2148” cannot be used with File Startup instantly.

Therefore, we must modify some default value before using with program Keil-CARM.

For interpretation commands, we must modify new File Startup and must set new format

that is corresponding with the board’s need. In this case, we will recommend selecting

“No” to protect Keil uVision3 not copy File Startup of Keil-CARM to use in Project.

4. Copy File named “Startup.s” that ETT has already provided in CD-ROM and is saved

in Example named “Startup.s”, then to place it in the same position folder of new Project

File that we created completely. File “Startup.s” is a file that contains Assembly

Language Commands of ARM7 to configure the necessary default value for MCU; for

example, to configure Stack value into MCU, to configure Initial Phase-Lock-Loop, to

configure value into MAM Function and to configure position Vectors of MCU. For

using with Board “CP-JR ARM7 USB-LPC2148”, if we Add File “Startup.s” from Keil

or Copy this File from other positions, it will be effected on the operation of program in

Startup because some operations are different.

5. Configure Option value of Project File by using command Project → Option for Target

’Target 1’ and then select Tab of Target to configure value of MCU Target as follows.

Example of Using Keil uVision3 to Create Project File of Keil-CARM 5.1 Configure X-

TAL to be 12 MHz and then configure Memory internal MCU to be condition of

interpretation program of Keil-CARM as in the picture below.

42

5.2 Output: we must click default values of Create HEX File, configure format of Hex to

be HEX-386 and then select OK as in the picture below. Example of Using Keil uVision3

to Create Project File of Keil-CARM

43

6. Start writing C Language Source Code, click command File → New… and we will get

the available are to write Text File. In the first time, we must configure File name to be

“Text” follow by the Default as in the picture below.

In this step, it is typing C Language Source Code in the available area under

configurations of Keil-CARM and we can write program preferably as in the picture

below.


44

After typing C Language commands completely, we must save this File and must

configure File surname to be “.C”. In this case, we recommend to save by using as in the

picture below. Example of Using Keil uVision3 to Create Project File of Keil- command

File → Save As… and then configure File name and File surname as “.main.c” CARM.

45

After save File as “.main.c” completely, we can see color of characters in program

are changed follow by the functions such as Comment, Variable and Command. It is an

advantage of Keil uVision3 that can extract and display characters follow by their

functions, it makes user understand program and read program easily as in the picture

below.

7. Add Files into Project File, click command Project → Components, Environment,

Books…, select Tab Project Components and then select desired Add File to add into

Project File. In the first time, we must select Files of type to be “C Source files (*.c)” and

it will display Files name that is C Language Source Code. Click icon of File named

“main.c” and then select Add File named “Startup.s” into Project Files that we created.

Then we must configure new File of type to be “ASM Source files(*.s*;*.src;*.a*), it will

display File name Startup.s in the blank of File name, so click icon of File “Startup.s” and

then select Add File named “Startup.s” into Project Files that we created. Example of

Using Keil uVision3 to Create Project File of Keil-CARM

46

When we command ADD both File name “main.c” and “Startup.s” into Project

File successfully, we must select Close to end the command Add File and it will display

result of operation as in the picture below.

↓


↓


47

After command Add File both “main.c” and “Startup.s” into Project File successfully,

we can see both Files name are displayed in the blank of Tab of File.

8. Command to interpret the written program, click command Projects → Rebuild all

target files and program Keil uVision3 will command program Keil-CARM to interpret

commands instantly.

48

After we command to interpret program successfully and everything is correct

without any error (0 Error and 0 Warning), we will get Hex File that has names to be the

same as the created Project File name and we can use this Hex File to download into

MCU instantly.

Please paste u r code here

Results

Assemble the circuit on the PCB as shown in Fig 5.1. After assembling the circuit

on the PCB, check it for proper connections before switching on the power supply.

In total, the complete system (including all the hardware components and

software routines) is working as per the initial specifications and requirements of our

project. Because of the creative nature of the design, and due to lack of time, some

features could not be fine-tuned and are not working properly. So certain aspects of the

system can be modified as operational experience is gained with it. As the users work

49

with the system, they develop various new ideas for the development and enhancement of

the project.

50

CONCLUSION

The project is thus carried out using ARM7TDMI core with the help of GSM

technologies. This project finds application in domestic agricultural field. In civilian

domain, this can be used to ensure faithful irrigation of farm field, since we have the

option of finding out moisture level of soil in a particular area.

FUTURE SCOPE OF THE PROJECT

The future scope of this project is enhanced applications with the addition of the

required feature One such application is to detect the soil parameter and

suggesting the proper fertilizer and its feed time. Such

Sensors can be incorporated in the design.

In the same manner one can exactly predict the weather if the system is made to

communicate with the nearer weather station through satellite communication.

RESULTS

Implemented hardware circuit for real-time automation of Indian agricultural

system.

51