OPAL-RT RT14: MMC in RT-LAB

The 7th International Conferenceon Real-Time Simulation TechnologiesMontreal | 9-12 June, 2014

1

Wei Li, Esmaeil Ghahremani

OPAL-RT

[email protected]

[email protected]

Modular Multilevel Converter Solution in RT-LAB

RTE

[email protected]

Sebastien Dennetiere


2

Chinese MMC Project and eMEGAsim Simulator Installation

MMC Project

eMEGAsimInstalled at MMCManufacturer

CEPRI

XJ Group

Nari

CSG

Zhejiang Grid

SPERI


33

Contents

• What is Modular Multilevel Converter (MMC)

• MMC Advantages and Challenges

• OPAL-RT solutions for MMC System Verification

• Applications

• Demo: modeling MOV in MMC system

• Conclusions

August 19, 2014 OPAL-RT


4

MMC Sub-module (SM)• What is MMC: Modular Multilevel Converter

• Sub-module (SM) are two-terminal devices

• MMC Half-bridge (HB): with 2-IGBT in each SMSM output is either capacitor voltage or zero at active mode

• MMC Full-bridge (FB): with 4 IGBTs in each SMSM output is either positive or negative of capacitor voltage or zero at active mode

MMC-1P

Vcap+

-

Vab

+

-

A

B

ISM

T1

T2

T3

T4

MMC-2P


5

MMC Topology description

• MMC-HB ac-dc converter

SM1

SM2

SMk

SM1

SM2

SMk

Vdc+

Vdc-

Vt-a

IaLs

Ls

Iup-a

Ilow-a

Vup-a

Vlow-a

Iup-b

Ilow-b Ilow-c

Idc+

Idc-

Vsm1

Vsm2

Vsmk

+

+

-

-

+

-

+

-

Vsmup-a

SM1

SM2

SMk

SM1

SM2

SMk

Vt-a

IaLs

Ls

Vup-b

Vlow-b

Iup-c

SM1

SM2

SMk

SM1

SM2

SMk

Vt-a

IaLs

Ls

Vup-c

Vlow-c

Sub-module

(SM)


6

MMC Topology description

• MMC-FB STATCOM

SM1

SM2

SMk

Vn

Vt-a

Ls

Ia Ib Ic

SM1

SM2

SMk

Vt-a

Ls

SM1

SM2

SMk

Vt-a

Ls

Sub-module

(SM)


7

MMC 1P working principle• Sum of all SM capacitor

voltage in 1 arm equals two times the dc link voltage

• At any given time, only half SM output their capacitor voltage.


8

MMC Characteristics

• Arm currents are continuous

• Commutating inductors are in arms

• Capacitors in each cell (energy storage in MMC)

• SM capacitor voltage has to be balanced (on a larger time scale)

• DC-link voltage is controlled by switch states (fast)


9

MMC Advantages

• Low PWM frequency– reduced switch losses

• Low ac harmonic content – no need for a filter

• Continuous currents in MMC arm and DC link - dc link capacitor omitted

• Fast recovery from AC/DC-bus short-circuit

• Reliability - system can remain operating for a certain period even when a few SM are out of order


10

Challenges

• More complex controller and protection(design and validation)

• More challenge for Simulation

• large number of components

• large number of and I/Os

• Non-linear elements, e.g. MOV


11

OPAL-RT Solution for MMC Simulation

• MMC HB and FB models

• MMC application in HVDC or STATCOM

• MMC solutions for real time or fast simulation.

• MMC HIL and RCP (rapid control prototyping)

• Hardware IOs Copper wiring or optical fibers

• MMC example controller

• In RT-LAB or Hypersim platform

• MMC solution in CPU and FPGA


12

CPU models

• Supporting MMC-HB and MMC-FB

• Unlimited number of SM per valve

• Taking several CPU cores to calculate the models

• 1 CPU can solve 300 cell at a time step of 25 us

• Providing Vcell-cap debugging mode to help user developing their controller


13

FPGA models• Support MMC-HB (will support MMC-FB in 2014 Q3)

• For 1 FPGA VIRTEX 6 (OP7000 system)• up to 250 SM/valve * 6 valve, or 500 SM/vlve*2valve.

• VIRTEX 7 FPGA (OP7020 system)• up to 500 SM/valve * 6 valve + protocol drive + SFP *16

• Kintex-7 FPGA (OP4500 system)• up to 250 SM/valve * 6 valve + protocol drive + SFP *4

• Support multiple FPGAs.


14

FPGA models (continued)

• No CPU resources to calculate the models,

• MMC block calculates at a time step of 250 ns or 500 ns

• Pulse modulation and capacitor voltage balancing control (VBC) embedded in FPGA

• Providing Vcell-cap debugging mode to help user developing their controller

• Supporting both RT-LAB and Hypersim Platform


15

Interface between external controller & MMC models

• Analog output for Vcap and digital input for gating pulses

• SFP optical fiber with Aurora protocol

• SFP optical fiber with Gigabit Ethernet protocol


16

Simulating MMC in CPU model

Target

MMC valve control

Voltage balancing control + gating signal generation

MMC pole

control

CPU 2CPU 1

Other MMC

and Grid etc.

CPU 4 …

MMC

Grid

CPU 3


17

HIL Simulating MMC in CPU model

Target

Actual MMC valve controller

Actual MMC

pole controller

Other MMC

and Grid etc.

CPU 2 …

MMC

Grid

CPU 1

IO


18

MMC FPGA model in OP7020

MMC valve controlVoltage balancing control + gating

signal generationMMC

Se

lecto

r k1

Gating

Signals

to MMC

FPGA

Protocol drive (or IO drive)

Selector k2

Gating

Signals

from CPU

Gating signals by valve

control

SPF or IO

Reference

from CPU

Gating signals

to protocol

Target

Gating signals

from protocol

Se

lecto

r k3 Capacitor voltage

Capacitor Voltage

from Protocol

MMC & system

Measurements


19

Simulating MMC in FPGA (valve control in CPU)

MMC valve controlVoltage balancing control + gating signal generation

MMC

Se

lecto

r k1

Gating

Signals

to MMC

FPGA


Selector k2

Gating

Signals

from CPU


control

SPF or IO

Reference

from CPU

Gating signals

to protocol

Target

Gating signals

from protocol

Se

lecto


Capacitor Voltage

from Protocol

GridValve control Pole control

MMC & system

Measurements


20

Simulating MMC in FPGA (valve control in same FPGA)

Target

MMC valve controlVoltage balancing control + gating signal generation

MMC

Se

lecto

r k1

Gating

Signals

to MMC

FPGA


Selector k2

Gating

Signals

from CPU


control

SPF or IO

Reference

from CPU

Gating signals

to protocolGating signals

from protocol

Se

lecto


Capacitor Voltage

from Protocol

GridPole control

MMC & system

Measurements


21

HIL Applications of MMC in FPGA

Fiber optic

Gating

Signals

to MMCMMC valve control MMC

Sele

cto

r k1

FPGA 2

Protocol drive

Selector k2

Gating

Signals

from CPU


control

SPF

Reference

from CPU

Gating signals

to protocol

Gating signals

from protocol

Sele

cto


Capacitor Voltage

from Protocol

MMC

System.

Measurements.

GridCPU based

Target 2I/O

Copper wiring

System

measurements

Fiber optic

Gating

Signals

to MMCvalve control MMC

Sele

cto

r k1

FPGA 1

Protocol drive

Selector k2

Gating

Signals

from CPU

SPF

Reference

from CPU

Gating signals

to protocol

Gating signals

from protocol

Sele

cto

r k3

Capacitor voltage

Capacitor Voltage

from Protocol

MMC

Sys.

Meas.

Gating signals by

valve control

Pole ctrlCPU based

Target 1I/O

MMC measurements & commands


22

HIL Testing of Actual MMC Controller

Fiber optic

Gating

Signals

to MMCMMC valve control MMC

Sele

cto

r k1

FPGA

Protocol drive

Selector k2

Gating

Signals

from CPU


control

SPF

Reference

from CPU

Gating signals

to protocol

Gating signals

from protocol

Sele

cto


Capacitor Voltage

from Protocol

MMC

System.

Measurements.

GridCPU based

TargetI/O

Copper wiringSystem measurements

Actual MMC controller



23

RCP of MMC Controller in FPGA

Fiber optic

Gating

Signals

to MMCvalve control MMC

Sele

cto

r k1

FPGA

Protocol drive

Selector k2

Gating

Signals

from CPU

SPF

Reference

from CPU

Gating signals

to protocol

Gating signals

from protocol

Sele

cto

r k3

Capacitor voltage

Capacitor Voltage

from Protocol

MMC

Sys.

Meas.

Gating signals by

valve control

Pole ctrlCPU based

TargetI/O

DowngradedMMC system


Copper wiringSystem measurements


24

MMC Customer

customer sitedelivery

timeMMC model /

Hardware

cell number

/TerminalsIO/protocol projects

ABB Switzerland 2012MMC FPGA model,

MMC controller/OP7000

8*62 terminals

48 AO, 96 DI hardware-in-the-loop test controller

Alstom UK 2012MMC cpu model

/OP5600100*6

2 terminalsno fast simulation

China South Grid (CSG) China2013

MMC FPGA model/OP7020

200*63 terminals

Aurorasimulation a real 3-terminal MMC

HVDC project and validation its controller

China Electric Power Research Institute (CEPRI)

China 2013MMC FPGA

model/OP7000500*6

2 terminalsno

simulation of a 3-terminal MMC HVDC project

Nari-Relays (NR) phase 1 China 2011MMC CPU and fpga

model/OP5600+ML60550*6

2 terminals48*6 AO, 96*6 DI hardware-in-the-loop test

Nari-Relays (NR) phase 2 China 2013MMC fpga

model/OP7020250*6

5 terminalsAurora/Gigabit

simulation of a 5-terminal MMC HVDC project

XJ Group phase 1 China 2013MMC

controller/OP7020 5 terminalsIO Rapid Control Prototyping (RCP)

State Power Economic Research Institute (SPERI)

China 2013MMC

controller/OP7020 5 terminals


25

Naoao 3-terminal MMC project (1st multiterminal in the world)

ParametersSucheng station

Jinniu station

Qingao station

Transfomre connection Yn/D11 Yn/D11 Yn/D11Rated power (MVA) 240 120 63Primary voltage (kV) 110 110 110

Secondary voltage (kV) 166 166 166Primary impedance (pu)

[R1,L1][0.0025 0.06 ]

[0.0025 0.06 ]

[0.0025 0.05 ]

Secondary impedance (pu) [R2,L2]

[0.0025 0.06 ]

[0.0025 0.06 ]

[0.0025 0.05 ]

Grounding resistance (kΩ)

5 5 5

MMC capacity(MVA) 200 100 50Number of SMs in an

arm147 220 220

Number of redandant SMs

14 20 20

Rated SM voltage(kV) 2.4 1.6 1.6


26

Naoao MMC Full HIL Configuration and PerformanceTime

Step

28 us

CPU # 6

(3 for 3 MMC

1 for ac grid

1 for wind farm

1 for data acquisition and logging)

FPGA # 3 Virtex-6

IO 32*3 AO

32*3 DI

32*3 DO


27

Demo: Testing MOV in MMC


2828

MMC Model with Arrester (MOV) – Top Level



2929

MMC Model with Arrester (MOV) - Subsystem



3030

The Arrester Connected to DC-Pole



3131

Arrester Modelling with Non-Linear Shunt Resistor


The nonlinear characteristics is composed for more than 20 segments (up to 30) .


3232

MMC Model – HIL Configuration



3333

Simulation Preferences – Enable or Disable Iterations



3434

Simulation Results – No Iterations – Compare with EMTP



3535

Simulation Results – No Iterations – Compare with EMTP



3636

Simulation Results – Enable Iterations



3737

Simulation Results – Enable Iterations – Compare with EMTP



3838

Simulation Results – Enable Iterations – Compare with EMTP



39

Real-Time Performance of MMC HIL Configurations

System Target

Time

Step

25 us

CPU # 3

IO 32*2 = 64 AO

13*2 = 26 AIN

12*2 = 24 DIN


40

Summaries

ChallengesOPAL-RT

Solutions

Small time step for SM

Large number of SM

Connection to

controller with fast

rate and small latency

Accuracy on non-linear

elements, e.g. MOV

Tested reliability

OPAL-RT

solutionsothers

Minimum MMC

time step250 ns >2.5 us

Maximum

number of SM

per FPGA

3000 SM 1500

Support Multi-

FPGAyes yes

Connection to

controller

Aurora,

Gigabit EthernetAurora

Accuracy on non-

linear elementyes no


41

Thanks

Technology

OPAL-RT RT14: MMC in RT-LAB