MUHAMMAD JAWWAD RAFIQ

024

Memory Interleaving

Memory interleaving is the technique used to increase the throughput. The core idea is to split the memory system into independent banks, which can answer read or write requests independents in parallel.

4 Way interleaved Memory Low order interleaving

Usually , this is done by interleaving the address space, Consecutive cells in the address space are assigned to different memory banks. An example of four-way interleaved memory , and the mapping of consecutive data cells it is shown in previous slide.

There are two-address format for memory interleaving the address space.

Low order interleaving Low order interleaving spreads contiguous memory

location across the modules horizontally. This implies that the low order bits of the memory address are used to indentify the memory module. High order bits are the word addresses (displacement) within each module

High order interleavingHigh order interleaving uses the high order bits as the

module address and the low order bits as the word address within each module.

Where is it implemented

Memory interleaving implemented on main memory , Which is slow as compared to Cache. And Main memory having less bandwidth.

Memory bandwidth

Memory bandwidth is the rate at which data can be read and write into a memory by a processor. Memory bandwidth is usually expressed in units of bytes/sec.

Interleaved Memory organization Various organization of the physical memory are

included in this section. In order to close up the speed gap between Cache and main memory. And interleaving technique is represented allow pipelined access of the parallel memory modules.

The memory design goal (interleaving goal) is to broaden the effective memory bandwidth so that more memory words can be accessed per unit time.

The ultimate purpose is to match the memory bandwidth with the bus bandwidth and with the processor bandwidth.

Modules and addresses in Main Memory The main memory is built with multiple modules

(chips). These memory modules are connected to a bus and

other resources(Processor, I/O) are also connected. Memory module having memory addresses. Each memory module return one word per cycle. It is possible to present different addresses to different

memory modules. So the Parallel access of multiple word can be done

concurrently (one cycle). This called parallel access in term of pipelined

fashion.

Main memory is often block-accessed at consecutive addresses.

Block access is needed for fetching a sequence of instructions or for accessing a linearly ordered data structure.

Each block access may correspond to the size of a cache block.

Therefore it is desirable to design the memory to facilitate the block access of contiguous words.

The Address Space for Low–Order Interleaving

When a memory is N–way interleaved, we always find that N = 2K.  This is due to the structure of the memory address.

For K = 1, we have 2–way interleaving. For K = 2, we have 4–way interleaving. For K = 3, we have 8–way interleaving. For K = 4, we have 16–way interleaving. For each scheme, the K bits(lower bits) of the address

select the Module. structure is as follows.  Each address is a 6–bit unsigned

binary number.

a and b bits in Low order interleavinga bits are used to identify the memory module. And the higher order b bits are the word addresses(displacement) within each module.

a and b bits in High order interleavinga bits are as the module address and the low order b bits are the word address in each module.

High order interleaving cannot support block access of contiguous location . Low order interleaving support the block access in pipelined fashion .

A Main memory formed with m= 2^a memory modules.

Each containing w=2^b words of memory cells.

Low order interleaving

High order interleaving