Gcc porting

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  • 1. GCC portingUse instruction pattern describetarget ISAShiva Chenshiva0217@gmail.comMay 2013

2. Outline Compiler structure Intermediate languages in GCC Optimization pass in GCC Define instruction pattern Operand constraints Match instruction pattern Strict RTL Target defined constraints Emit assembly code Target information usage Preserve word to describe instruction pattern Example of instruction pattern Split instruction pattern Instruction attribute Peephole pattern Instruction scheduling 3. Three main intermediate languages format in GCC GENERICLanguage-independent representation generated by each frontendCommon representation for all the languages supported byGCC. GIMPLEPerform language independent and target independentoptimization RTLPerform the optimization which will notice target feature byporting code 4. Gimple optimization pass in GCC4.6.2004t.gimple006t.vcg009t.omplower010t.lower012t.eh013t.cfg017t.ssa018t.veclower019t.inline_param1020t.einline021t.early_optimizations022t.copyrename1023t.ccp1024t.forwprop1025t.ealias026t.esra027t.copyprop1028t.mergephi1029t.cddce1030t.eipa_sra031t.tailr1032t.switchconv034t.profile035t.local-pure-const1036t.fnsplit037t.release_ssa038t.inline_param2057t.copyrename2058t.cunrolli059t.ccp2060t.forwprop2062t.alias063t.retslot064t.phiprop065t.fre066t.copyprop2067t.mergephi2068t.vrp1069t.dce1070t.cselim071t.ifcombine072t.phiopt1073t.tailr2074t.ch076t.cplxlower077t.sra078t.copyrename3079t.dom1080t.phicprop1081t.dse1082t.reassoc1083t.dce2084t.forwprop3085t.phiopt2086t.objsz087t.ccp3088t.copyprop3090t.bswap091t.crited092t.pre093t.sink094t.loop095t.loopinit096t.lim1097t.copyprop4143t.optimized 5. RTL optimization pass in GCC 4.6.2004t.gimple144r.expandOther gimple pass145r.sibling147r.initvals148r.unshare149r.vregs150r.into_cfglayout151r.jump152r.subreg1153r.dfinit154r.cse1155r.fwprop1156r.cprop1158r.hoist159r.cprop2162r.ce1163r.reginfo164r.loop2165r.loop2_init166r.loop2_invariant170r.loop2_done172r.cprop3173r.cse2174r.dse1175r.fwprop2176r.auto_inc_dec177r.init-regs178r.dce179r.combine180r.ce2182r.regmove183r.outof_cfglayout184r.split1185r.subreg2188r.asmcons190r.sched1191r.ira192r.postreload194r.split2198r.pro_and_epilogue199r.dse2200r.csa201r.peephole2202r.ce3204r.cprop_hardreg205r.dce206r.bbro208r.split4209r.sched2212r.alignments215r.mach216r.barriers217r.dbr218r.split5220r.shorten221r.nothrow222r.final223r.dfinish224t.statistics 6. Why need divide optimization pass togimple pass and RTL pass? Gimple pass have more high level semanticEx: switch, array, structure, variableSome optimization is more easier to designed whenhigh level semantic still exist However, gimple pass lack of target informationEx: instruction length(size), supported ISATherefore, we need RTL optimization pass 7. Define instruction pattern All the RTL pattern must match target ISA How to tell GCC generate the RTL match ISA ?Instruction patterns Use define_expand, define_insn to describe the instructionpatterns which target support(define_insn addsi3"[(set (match_operand:SI 0 register_operand" "=r,r")(plus:SI (match_operand:SI 1 register_operand" "%r,r")(match_operand:SI 2 nonmemory_operand" r,i")))] ... ) 8. Define instruction pattern GCC already define several instruction patternname and the semantic of the pattern addsi3Add semantic with 3 SI mode operands GCC dont know the operand constraint of thetarget How to tell GCC our targets operand constraint of eachinstruction ?PredicateConstraint 9. Operand Constraints Multiple Alternative Constraints(define_insn addsi3"[(set (match_operand:SI 0 register_operand" "=r,r")(plus:SI (match_operand:SI 1 register_operand" "%r,r")(match_operand:SI 2 nonmemory_operand" r,i")))] ... )Predicate: register_operand, nonmemory_operandConstraint: r, iPredicate should contain each constraints of the operandFor operand 2 with SI moder(reg) belong to nonmemory_operandi(immediate) belong to nonmemory_operand 10. Operand Constraints GCC already have predicate to restrictoperand Why need constraint field ?Give the opportunity to change operand whileoptimization Ex:movi $r0, 4;add $r1, $r1, $r0 {addsi3}Constant propagation=> addi $r1, $1, 4 {addsi3} 11. Operand Constraints GCC use two level operand constraint group same semantic instruction together withsingle instruction pattern (addsi3) Lots of ISA designed have several assemblyinstructions with same semantic and differentoperand constraint Reduce the instruction pattern when porting 12. Operand Constraints Use instruction pattern do ISA supportchecking when GCC generate a new RTLpattern Check does the back end define the pattern bydefine_insn Check the operand type support or not bypredicate Check the operand belong to which alternativeby constraint 13. Operand Constraints Multiple Alternative Constraints(define_insn addsi3"[(set (match_operand:SI 0 register_operand" "=r,r")(plus:SI (match_operand:SI 1 register_operand" "%r,r")(match_operand:SI 2 nonmemory_operand" r,i")))] ... )First alternative constraintsmatch addSecond alternative constraintsmatch addi 14. Match instruction pattern Multiple Alternative Constraints(define_insn addsi3"[(set (match_operand:SI 0 register_operand" "=r,r")(plus:SI (match_operand:SI 1 register_operand" "%r,r")(match_operand:SI 2 nonmemory_operand" r,i")))] ... )Ex:(set (reg/f:SI 88)(plus:SI (reg:SI 87)(reg/v:SI 55))1. Parsing RTL pattern(set (op0)(plus:SI (op1)(op2)) 15. Match instruction pattern When will generate new RTL pattern ? RTL expand phase (GIMPLE to RTL) During optimizationEx:(set (reg/f:SI 47)(lshiftrt:SI (reg:SI 60)(const_int 2))(set (reg/f:SI 88)(plus:SI (reg:SI 47)(reg:SI 55))(set (reg/f:SI 88)(plus:SI (lshiftrt:SI (reg:SI 60)(const_int 2))(reg/v:SI 55))Combine phasesrli $r47, $r60, 2add $r88, $r47, $r55add_srli $r88, $r55, $r60, 2 16. Strict RTL Does the new generated RTL patternalways satisfy constraint ? GCC allow certain kind un-match constraintwhich reload could fix it later Predicate must always satisfyRTL1Not do optimization1Do optimization1RTL1RTL2ReloadReloadRTL3RTL2 not satisfy constraintRTL41. RTL3 and RTL4Satisfy constraint2. RTL4 is betterThen RTL3 17. Strict RTL Constraint could allow certain un-match beforereload, and hope reload to fix it Ex: constraint is m (memory), but current operand isconstant, GCC will allow before reload Reload phase is after register allocationIn fact, during register allocation, GCC will call reload rapidlywhile the operand not fit the constraint. After reload, the operand must satisfy one of theoperand constraint (strict RTL) 18. Strict RTL(define_insn movsi"[(set (match_operand:SI 0 register_operand" "=r,m")(match_operand:SI 1 register_operand" r,r")))] ... )(set (reg/f:SI 47)(reg:SI 60))(set (reg/f:SI 47)(reg:SI 3))AssumeAfter register allocationPseudo register r60 assigned to r3and the hardware register is exhaustedRA (set (mem:SI (plus (sp)(const))))(reg:SI 3))Reload 19. Target defined constraints Target could define their own predicate andconstraint Target defined predicate(define_predicate "index_operand"(ior (match_operand 0 "register_operand")(and (match_operand 0 const_int_operand")(match_test "(INTVAL (op) < 4096&& INTVAL (op) > -4096))"))) 20. Target defined constraints Target defined constraint(define_register_constraint "l""LO_REGS""registers r0->r7.")(define_memory_constraint "Uv""@internal In ARM/Thumb-2 state a valid VFP load/store address."(and (match_code "mem")(match_test "TARGET_32BIT&& arm_coproc_mem_operand (op, FALSE)"))) 21. Emit assembly code Multiple Alternative Constraints(define_insn addsi3"[ (set (match_operand:SI 0 register_operand" "=r,r")(plus:SI (match_operand:SI 1 register_operand" "%r,r")(match_operand:SI 2 nonmemory_operand" r,i")))]@add %0, %1, %2addi %0, %1, %2)Match First alternative constraintsmatch addOutput assembly code add $r3, $r4, $5Ex:(set (reg/f:SI 3)(plus:SI (reg:SI 4)(reg:SI 5)) 22. Target information usage When will GCC use target information get frominstruction patterns ? RTL instruction pattern generationgenerate insn-emit.c when building GCC by parsing instructionpatterns RTL instruction validation (target supported)generate insn-recog.c when building GCC by parsing instructionpatterns Emit target assembly codegenerate insn-output.c when building GCC by parsinginstruction patterns 23. Preserve word to describe instructionpatterndefine_insnnaming patterndefine_expandnaming patterndefine_insn*..RTL generationRTL validationEmit assembly GCC define several naming patterns and their semantic use togenerate RTL pattern during RTL expand phase ex: addsi3, subsi3, movsi, movhi Some target ISA which the semantic not defined in GCC namingpattern but the RTL could generate by some optimization ex: add_slli could generate by combine phase define un-naming pattern make the instruction validate define_insn *add_slli define_insn name with * prefix will identify as un-naming pattern 24. Example of instruction pattern1600 ;; These control RTL generation for conditional jump insns1601 (define_expand "cbranchsi4"1602 [(set (pc)1603 (if_then_else (match_operator 0 "ordered_comparison_operator"1604 [(match_operand:SI 1 "nonmemory_nonsymbol_operand" "")1605 (match_operand:SI 2 "nonmemory_nonsymbol_operand" "")])1606 (label_ref (match_operand 3 "" ""))1607 (pc)))]1608 ""1609 {1610 sh_expand_cbranchsi4 (operands);1611 DONE;1612 }1613 )Semantic of cbranchsi4compare operand1 and operand 2 by operator 0branch to label 3 if the compare result is truePredicate "ordered_comparison_operator including EQ,NE,LT,LTU,LE,LEU,GT,GTU,GE,GEU.Use porting function sh_expand_cbranchsi4 to generate RTL pattern 25. Example of instruction pattern1621 (define_insn "*bcondz"1622 [(set (pc)1623 (if_then_else (match_operator 0 "bcondz_operator"1624 [(match_operand:SI 1 "register_operand" "r")1625 (const_int 0)])1626 (label_ref (match_operand 2 "" ""))1627 (pc)))]1628 ""1629 {1630 switch (GET_CODE (operands[0