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Digital ElectronicsUNIT 8 DIGITAL ELECTRONICS
Structure 8.1 Introduction
Objectives
8.2 Logic Gates and Boolean Algebra 8.2.1 NOT Gate 8.2.2 OR Gate 8.2.3 AND Gate 8.2.4 Boolean Identities for OR Operation 8.2.5 Boolean Identities for AND Operation 8.2.6 Boolean Identities for NOT Operation 8.2.7 De Morgan’s Theorems
8.3 Karnaugh Maps and Combinatorial Logic Design 8.3.1 Binary Number Systems 8.3.2 Sum of Products Equations and Logic Circuits 8.3.3 Drawing Karnaugh Maps 8.3.4 Karnaugh Simplifications and Simplified Logic Circuits
8.4 Tristate Concepts 8.5 Sequential Circuits
8.5.1 Flip Flops 8.5.2 Shift Registers 8.5.3 Counters
8.6 TTL and CMOS Circuits 8.6.1 TTL Circuits 8.6.2 CMOS Circuits
8.7 Memories 8.7.1 Read Only Memory 8.7.2 Random Access Memory
8.8 Modem 8.9 Summary 8.10 Answers to SAQs
8.1 INTRODUCTION
It is difficult to imagine a world without digital computers nowadays. Computers are used in every spheres of life. We usually communicate each other with the instantaneous electronic mails (emails), all the transactions in the banks, hospitals, super markets, airlines, etc. are done with the help of digital computers. Computer is just one of the outcomes of the progress in digital electronics. It can be noted that even in large digital systems like computers, there are only few basic operations, which are repeated many times. The four most commonly used circuits in such systems are OR, AND and NOT Logic gates and FLIP-FLOP circuits. These Logic gates and circuits implement Boolean algebra, which was invented by G. Boole in mid 19th century. Hence it becomes a necessity for the today’s engineers to learn these mathematical equations for logical circuits along with the logic circuits.
Objectives After studying this unit, you should be able to
• write the symbols and truth tables for basic Logic gates; explain the Boolean identities pertaining to the basic operations of Logic gates; state the two De Morgan’s theorems,
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Electronics
• make Karnaugh maps and use them for simplifying Boolean expressions; design the basic combinatorial logic circuits,
• explain the tristate concepts,
• draw the diagrams for basic Flip Flops, explain their operation and truth tables; understand and describe the various shift registers and counters,
• be familiar with the TTL and CMOS devices and circuits,
• list the various forms of memories and explain their operations, and
• discuss the functions of Modems.
8.2 LOGIC GATES AND BOOLEAN ALGEBRA
Digital computers understand the language of 1s and 0s. This number system is also called as binary number system (bi means two). Note that the operation of digital circuits can be described in two corresponding voltage levels. The more positive level is denoted by high (H = 1) and the other is denoted by low (L = 0). And the logical operations are represented by true (T) and false (F). For instance, H = 1 = T and L = 0 = F is a positive logic whereas H = 0 = F and L = 1 = T is a negative logic.
A digital circuit having one or more input signals but only one output signal is called a gate. A gate, which implements Boolean algebraic equations, is called Logic gates. The most basic gates are NOT gate, OR gate and AND gate, we will discuss them one by one along with the Boolean identities pertaining to their logical operations.
8.2.1 NOT Gate The NOT gate has a single input and a single output and its symbol and truth table (truth table contains a table of all possible input values and their corresponding outputs values) is shown in Figure 8.1. It performs the operation of inversion, i.e. the output of a NOT gate takes a 1 (high) state iff the input takes the 0 (low) state and vice-versa. A circuit, which performs a logic negation, is called a NOT circuit or inverter since it inverts the output with respect to the input.
A Y A Y
0
1
1
0
(a) (b)
Figure 8.1 : (a) Symbol of NOT Gate, and (b) Truth Table
8.2.2 OR Gate The OR gate has two or more inputs and a single output. The symbol and truth table for a two-input OR gate is shown in Figure 8.2. The output of an OR gate is in 1 state if any of the inputs is in the 1 state.
Figure 8.2 : (a) Symbol of OR Gate, and (b) Truth Table
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Digital Electronics8.2.3 AND Gate
The AND gate has two or more inputs and a single output. The symbol and truth table for a two-input AND is shown in Figure 8.3. The output of an AND gate is in 1 state iff all inputs are in the 1 state or the output will be zero if any of the inputs is zero.
Figure 8.3 : (a) Symbol of AND Gate, and (b) Truth Table
SAQ 1 (a) A buffer gives the same output as the input. How to realize a Buffer from a
AND gate?
(b) Draw the symbol and truth table of a three-input OR gate.
(c) Draw the symbol and truth table of a three-input AND gate.
The mathematics of binary number systems (1s and 0s) also known as Boolean Algebra was invented by George Boole in 1854. This branch of mathematics has become very important with the invention of digital computers in 1946. In this section, we will discuss some of the basic Boolean laws and theorems.
8.2.4 Boolean Identities for OR Operation The OR operation in the Boolean algebra is denoted by (+). Following are the Boolean identities for the OR operation.
A + B = B + A (Commutative Law)
It implies that the input A and B of the OR gate can be interchanged without changing the output Y. It can be justified from the truth table of two-input OR gate. For A = B, it is obvious that it doesn’t matter when we interchange A and B. When A = 0 and B = 1, if we interchange A and B, then it will become the case of A = 1 and B = 0 and for both these case the output is 1. Hence it doesn’t matter to the output if we interchange A and B inputs.
A + B + C = (A + B) + C = A + (B + C) (Associative Law)
It means that the order of combining the input variables has no effect on the output variables. This can be verified from the truth table for three-input OR gate.
A + A = A
It means that any variable ORed with itself equals the variable. We can justify this Boolean identity by substituting the two possible values of A. For A = 0, 0 + 0 = 0 and for A = 1, 1 + 1 = 1 is true (refer to truth table for two-input OR gate).
A + 1 = 1
If one input of the OR gate is high the output is high no matter what is the other input. For A = 0, 0 + 1 = 1 and for A = 1, 1 + 1 = 1 is true.
A + 0 = A
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It means a Boolean variable ORed with 0 equals the variable. For A = 0, 0 + 0 = 0 and A = 1, 1 + 0 = 1 is true.
Electronics
8.2.5 Boolean Identities for AND Operation The AND operation is denoted by (.) in the Boolean algebra. Following are the Boolean identities pertaining to AND operation.
A . B = B . A (Commutative Law)
It implies that the inputs of the AND gate can be interchanged without changing the output Y which can be justified from the truth table of two-input AND gate. Note that (.) is suppressed many times and we can write the Commutative law as A B = B A.
A B C = (A B) C = A (B C) (Associative Law)
It means that the order of combining the input variables has no effect on the output variables. This can be verified from the truth table for three-input AND gate.
A A = A
It means that any variable ANDed with itself equals the variable. For A = 0, 0 . 0 = 0 and for A = 1, 1 . 1 = 1 is true (refer to truth table for two-input AND gate).
A . 1 = A
If one input of the AND gate is high the output is equal to the input. For A = 0, 0.1 = 0 and for A = 1, 1.1 = 1 is true.
A . 0 = 0
If one input of the AND gate is low the output is low irrespective of the other input. For A = 0, 0.0 = 0 and for A = 1, 1.0 = 0 is true.
A (B + C) = A B + A C (Distributive Law)
We can write down the truth tables for LHS and RHS of the Boolean equation and verify they are same.
8.2.6 Boolean Identities for NOT Operation The NOT operation of a Boolean variable A is denoted by its complement Ā. Following are the Boolean identities pertaining to NOT operation.
A = A
It implies that the double complement of a Boolean variable is the variable itself. For A = 0, Ā = 1, A = 0 and for A = 1, Ā = 0, A = 1 is true.
Ā + A = 1
It means that a variable ORed with its complement always equals 1. If A = 0, Ā = 1 and A + Ā = 1 and when A = 1, Ā = 0 and A + Ā = 1 is correct.
A Ā = 0
It means that a variable ANDed with its complement always equals 0. For two possible values of A, 0.1 = 0 when A = 0, 1.0 = 0 when A = 1 is true.
A + Ā B = A + B
Proof : A + Ā B = A (B + 1) + Ā B = A B + A + Ā B = (A + Ā) B + A = B + A = A + B
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Digital Electronics8.2.7 De Morgan’s Theorems
De Morgan’s First Theorem
It says that complement of sum equals the product of complements.
A B A B+ =
The LHS of the equation describes a NOR (NOT-OR) gate and the RHS of the equation describes an AND gate with inverted inputs and both the equations have the same truth table as shown in Figure 8.4.
Figure 8.4 : (a) NOR Logic Gate, (b) AND Gate with Inverted Inputs, and (c) Truth Tble
De Morgan’s Second Theorem
It says that complement of product equals the sum of complements.
A B A B= +
The LHS of the equation describes a NAND (NOT-AND) gate and the RHS of the equation describes an OR gate with inverted inputs and both the equations have the same truth table as shown in Figure 8.5.
Figure 8.5 : (a) NAND Logic Gate, (b) OR Gate with Inverted Inputs, and (c) Truth Table
SAQ 2 (a) Show that A + A B = A.
(b) Verify that A + B C = (A + B) (A + C).
8.3 KARNAUGH MAP AND COMBINATORIAL LOGIC DESIGN
A Karnaugh map is visual display of minterms required for a sum-of-product solution. Let us first understand what is the minterms of a sum-of-product (SOP) equation. It will be helpful to know the Binary number system and its conversion to decimal number before doing this.
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8.3.1 Binary Number System Electronics
As stated before, binary numbers are represented using 0s and 1s. Any 4-digit binary number ABCD can be converted into its decimal equivalent as follows:
A × 23 + B × 22 + C × 21 + D × 20 where Boolean variables A, B, C and D can take values either 0 or 1. For instance, 1100 and its decimal equivalent value is 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20 = 12. For reference, first 16 binary numbers and their decimal equivalents are shown in Table 8.1.
Table 8.1 : First 16 Binary Numbers and their Decimal Values
Binary Numbers Decimal Values
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
8.3.2 Sum-of-Products Equations and Logic Circuits There are four possible ways to AND two input signals that are in the complemented and un-complemented form ( A B , A B, A B , AB) also called as fundamental products. Table 8.2 lists each of the fundamental product producing high outputs.
Table 8.2 : Fundamental Products for Two Inputs
A B Fundamental Product
Minterms
0 0 A B m0
0 1 A B m1
1 0 A B m2
1 1 A B m3
For instance, A B is high when A are B are low. The fundamental products A B , A B, A B and AB are also represented by minterms m0, m1, m2 and m3, where the suffix i of mi comes from the decimal equivalent of the binary number. There lies the benefit of understanding binary numbers before we study Sum of Products (SOP) methods. For
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3 inputs A, B and C, there are 23 minterms, m0, m1, m2, m3, m4, m5, m6 and m7 as listed in Table 8.3.
Digital Electronics
Table 8.3 : Fundamental Products for Three Inputs
A B C Fundamental Products
Minterms
0 0 0 A B C m0
0 0 1 A B C m1
0 1 0 A B C m2
0 1 1 A B C m3
1 0 0 A B C m4
1 0 1 A B C m5
1 1 0 A B C m6
1 1 1 A B C m7
For example, when A = 1, B = 1, C = 0, the fundamental product results a high output for the case Y = A B C = 110 = 1.
Sum-of-Product (SOP) Equation
SOP equation is a function of Boolean variables, which states the fundamental product terms or minterms, which will give a high output for the given inputs. For instance, the output Y is a function of three Boolean variables A, B and C whose minterms are listed which will give a high outputs.
Y = F (A, B, C) = ∑ m (1, 2, 3, 4) = A B C + A B C + A B C + A B C
Let us try to find the truth table from the given SOP equation. List all the possible values of A, B and C in the order of increasing minterm index i. In the truth table, place 1s whose minterms are listed in the SOP equation and at the other places draw 0s as in Table 8.4.
Table 8.4 : Truth Table for SOP Equation
A B C Minterms Y 0 0 0 m0 0 0 0 1 m1 1 ( A B C) 0 1 0 m2 1 ( A B C ) 0 1 1 m3 1 ( A B C) 1 0 0 m4 1 (A B C ) 1 0 1 m5 0 1 1 0 m6 0 1 1 1 m7 0
ABC
ABC
ABC
ABC
Y
AB C
ABC
A BC
AB C
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Figure 8.6 : Logic Circuit for SOP Equation Electronics
The truth table for the SOP equation is shown in Table 8.4 and the corresponding logic circuit is depicted in Figure 8.6.
8.3.3 Drawing Karnaugh Maps Karnaugh map also called as K-map is the visual representation of SOP solution. To illustrate this, let us consider the following example.
Y = F (A, B) = ∑ m (1, 2, 3) = A B + A B + A B
The truth table for this SOP equation is shown in Table 8.5.
Table 8.5 : Truth Table
A B Y Minterms
0 0 0 m0
0 1 1 m1
1 0 1 m2
1 1 1 m3
Following are the steps required to produce the K-map from the truth table :
Begin by drawing Figure 8.7(a). Write down the value of suffix of minterms or the equivalent decimal numbers as shown in Figure 8.7(b).
From the truth table of Table 8.5, write down the values of Y for the corresponding minterms. The values of Y for the minterms which are there is the SOP equation is 1, for other minterms it is 0.
A
A
B B
A
A
B B
A
A
B B
(a) (b) (c)
Figure 8.7 : Steps for Construction of 2-variable K-map
Similarly, we can construct 3-variable K-maps for any SOP equation involving 3 Boolean variables. For example, let us consider the following SOP equation :
Y = F (A, B, C) = ∑ m (3, 4, 5)
whose truth table is shown in Table 8.6.
Table 8.6 : Truth Table
A B C Y Minterms
0 0 0 0 m0
0 0 1 0 m1
0 1 0 0 m2
0 1 1 1 m3
1 0 0 1 m4
1 0 1 1 m5
1 1 0 0 m6
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Digital Electronics1 1 1 0 m7
Following the same three step procedures, we can construct the K-map from the truth table as illustrated in Figure 8.8.
AB
AB
C
AB
AB
C
AB
AB
AB
AB
C C
AB
AB
AB
AB
C C
(a) (b) (c)
Figure 8.8 : Steps for Construction of 3-variable K-map
Finally, we can also construct the 4-variable K-map using the same procedure as depicted in Figure 8.9.
AB
AB
CD CD
AB
AB
CD CD CD CD CD CD
AB
AB
AB
AB
(a) (b)
Figure 8.9 : Construction of 4-variable K-maps
8.3.4 Karnaugh Simplifications and Simplified Logic Circuits Pairs
There are two possible pairs in K-maps: Horizontally adjacent 1s pair (encircled 1s in Figure 8.10(a)) and Vertically adjacent 1s pair (encircled 1s in Figure 8.10(b)). The SOP equation for the Figure 8.10(a) can be simplified as
( )Y ABC D ABC D ABC D D ABC= + = + =
This implies that as we move from the first fundamental product ( A BC D ) to the second one ( A BC D ), only one variable (D for this case) changes from complemented to un-complemented form and that variable will get eliminated since 1D D+ = is one of the Boolean identities. Similarly, for vertically adjacent 1s pairs in Figure 8.10(b), one variable (B for this case) will be eliminated. Hence a pair leads to elimination of one variable and their complements.
AB
AB
CD CD
AB
AB
CD CD CD CD CD CD
AB
AB
AB
AB
(a) (b)
Figure 8.10 : (a) Horizontally Adjacent 1s Pair; and (b) Vertically Adjacent 1s Pair in K-maps
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Quads Electronics
A quad is a group of four 1s that are horizontally or vertically adjacent. They may be end-to-end or in the form of a square. A quad leads to elimination of two variables and their complements. A quad may be visualized as two adjacent pairs as shown in Figure 8.11(a). There are three possible pairs in K-maps: Horizontally adjacent 1s quad (encircled 1s in Figure 8.11(a)), Square adjacent 1s quad (encircled 1s in Figure 8.11(b)) and Vertically adjacent 1s quad (encircled 1s in Figure 8.11(c)). Let us consider the SOP equation of Figure 8.11(b) and simplify this.
( ) ( ( ) ( )) (Y AB CD CD CD CD AB C D D C D D AB C C AB= + + + = + + + = + =)
Here the two variables C, D and their complements are getting eliminated thereby further simplifying the SOP equation and hence the logic circuits.
AB
AB
CD CD
AB
AB
CD CD CD CD CD CD
AB
AB
AB
AB
CD CD CD CD
AB
AB
AB
AB
(a) (b) (c)
Figure 8.11 : (a) Horizontally Adjacent 1s Quad, (b) Square Adjacent 1s Quad, and (c) Vertically Adjacent 1s Quad in K-maps
Octets An octet can be visualized as two adjacent quads (refer to Figure 8.12(a)), it is a group of 8 adjacent 1s and it leads to elimination of three variables and their complements. Let us consider the SOP equation for the octet of Figure 8.12(a) and simplify this.
( ) ( )Y AB CD CD CD CD AB CD CD CD CD AB AB= + + + + + + + = +
( )B A A B= + =
which leads to elimination of three variables C, D, A and their complements. Thereby from this simplification of the K-map the logic circuit for this particular SOP equation will have only one input B instead of four variables as shown in Figure 8.12(b).
CD CD CD CD
AB
AB
AB
AB (a) (b)
Figure 8.12 : (a) Rectangle Adjacent 1s Octet in K-map, and (b) Logic Circuit after K-map Simplifications
Overlapping Groups In case of overlapping groups we can use same 1 more than once in forming adjacent groups of 1s as depicted in Figure 8.13(a). The SOP equation for the case of overlapping groups of Figure 8.13(a) after doing Karnaugh simplifications is
Y B C D A= +
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Digital ElectronicsRolling the Map
Imagine you pick the K-map and roll it so that the left side touches the right side then you will realize that the two pairs in Figure 8.13(b) will form a quad. Thereby it will lead to the elimination of two variables and their complements as can be verified from the SOP equation simplification using Boolean algebra.
( ) ( ) ( ) ( )Y C D AB AB CD AB AB CD A CD A AD= + + + = + = .
Don’t Care Conditions
In some digital systems, some inputs are never supplied thereby no output is visible. We call such cases don’t care conditions and they are represented by X in the truth table as depicted in Figure 8.13(c). Whenever we see an X in the truth table while encircling the 1s in the K-map to form the largest group, we can assume Xs as 1s. After it has been included in all the groups, disregard the Xs in the truth tables by assuming them as 0s. For the case of Figure 8.13(c), the SOP equation after Karnaugh simplifications are Y = B.
AB
AB
CD CD
AB
AB
CD CD CD CD CD CD
AB
AB
AB
AB
CD CD CD CD
AB
AB
AB
AB
(a) (b) (c)
Figure 8.13 : (a) Overlapped Groups, (b) Rolling, and (b) Don’t Care Conditions of K-maps
SAQ 3 (a) What are pairs, quads and octets in K-maps? How many variables will get
eliminated for each pair, quad and octet in K-maps?
(b) Draw the simplest logic circuit for the given logic equation where d denotes the don’t care conditions :
( , , , ) (5) (10, 11, 12, 13)Y F A B C D m d= = ∑ + .
8.4 TRISTATE CONCEPTS
Usually logic gates have only two operating modes/states, either 0 or 1, i.e. purely digital (or binary). In some applications, we require another additional state, which is known as high-impedance (high-Z) state. The device with three operating modes is called as tri-state logic gates. In order to understand the tri-state concepts, let us first study how are digital logic gates realized with the help of simple switch then we will proceed with the necessary additional circuits to realize tri-state logic gates. We will consider the manual operation of the switch for easy understanding of these fundamentals. But in actual digital circuits these switches are realized using transistors, which will be discussed in Section 8.6.
Digital Buffer
A buffer can be realized using a switch as illustrated in Figure 8.14(a), which is operated by the input voltage Vi. When Vi is low, the switch is connected to ground
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and output voltage V0 is low. When Vi is high, the switch is connected to Vcc and the output voltage V0 is high. This can be tabulated in the form of a truth table as shown in Figure 8.14(b), where the output follows the value of the input. Figure 8.14(c) depicts the symbol of a Digital Buffer.
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Vi V0
Vcc
Vi V0
L L
H H
Vi V0
(a) (b) (c)
Figure 8.14 : (a) Switch Configuration, (b) Truth Table, and (c) Symbol of a Digital Buffer
Tri-state Buffer
In the logic circuit of Figure 8.15(a), there is an additional switch to a digital buffer, which is called as enabled input denoted by E. When E is low, the output is disconnected from the input circuit. When E is high, the switch is connected and the circuit behaves like a digital buffer. All these states are listed in Truth Table 8.15(b). Figure 8.15(c) depicts the symbol of a Tri-state Buffer.
(a) (b) (c)
Figure 8.15 : (a) Switch Configuration, (b) Truth Table, and (c) Symbol of a Tri-state Buffer
Digital Inverter
Inverter performs the function of logic negation or output voltage V0 is the inverse or complement of the input voltage Vi or it is also called as NOT logic gate. Figure 8.16(a) shows the switch configuration for realization of a Digital Inverter. When input is low, the switch is connected to Vcc, and the output is high. When the input is high, the switch is connected to the ground and the output is low as tabulated in the form a truth table as shown in Figure 8.16(b). The symbol for Digital Inverter is drawn in Figure 8.16(c).
(a) (b) (c)
Figure 8.16 : (a) Switch Configuration, (b) Truth Table, and (c) Symbol of a Digital Inverter
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Digital ElectronicsTri-state Inverter
Like Tri-state buffer has an additional switch from the digital buffer, Tri-state Inverter has an additional switch than Digital Inverter as illustrated in Figure 8.17(a). This switch denoted by E, connects the input circuit to the output circuit when E is low. When E is high, the output circuit is disconnected from the circuit. Besides, when E is low it function as a Digital Inverter. These states are tabulated in Truth Table of Figure 8.17(b). The symbol for Tri-state inverter is also shown in Figure 8.17(c).
(a) (b) (c)
Figure 8.17 : (a) Switch Configuration, (b) Truth Table, and (b) Symbol of a Tri-state Inverter
SAQ 4 What are tri-state logic gates? Explain the function of Tri-state inverter and buffer with the help of switches.
8.5 SEQUENTIAL CIRCUITS
A digital system is required to store binary numbers in addition to performing logic; Flip-Flops implements the function of storing the binary information. Let us study how does this Flip-flops operates and performs as a memory unit/cell. Sequential circuits are those circuits whose output at any time instant t depends on input values of previous time instants and the present input or in other words it has a memory. All combinatorial logic circuits, which have been discussed till now, do not have memory and they are not sequential circuits. Besides Flip-flops we will also discuss the sequential circuits such as counters and shift registers and their possible use in the digital systems.
8.5.1 Flip-Flops Flip-flops are used in building counters and registers and other sequential circuits. Flip-flops are digital circuits whose output value will not change once it is set unlike the combinatorial circuits whose output values is dependent on the input values. They are used for storing binary numbers and they are memory elements for sequential circuits. There are four basic Flip-Flops viz. SR-, JK-, T- and D-type Flip-Flops. We will study them one by one and explore their possible applications in digital circuits. Any device or circuit which has two stable states are called bistable like switch in our previous section has two states either it is up or down. When it is up it is connected to Vcc (high) and when it is down it is connected to ground (low). Flip-flops also have two states of operation. When the flip-flop has output set to 0 V, it can be assumed as storing a logic 0 and when the output is set to 5 V (Vcc), it is storing logic 1. Since a Flip-flop holds or latch into either one of these states it is also called as a latch. A basic Flip-flop or latch is obtained by cross-coupling two NOT circuits NOT-1 and NOT-2 as shown in Figure 8.18. Note that single-input NAND gates perform the function of NOT gates. Do note that the Flip-Flop in Figure 8.18 also has feedback line, i.e. output in each gate is
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connected to the input of the others. The output bistable states are represented using Q = 1 ( Q = 0) is called the 1 state and Q = 0 ( Q = 1) is called the 0 state. It should be noted that the outputs Q and Q are always complementary for all cases.
Electronics
Q
Q
Figure 8.18 : Basic Flip-Flop or Latch
SR-type Flip Flops
An S R Flip Flop can be realized using two NAND gates as depicted in Figure 8.19(a) and its logic symbol is shown in Figure 8.19(b). Let us try to understand the truth table of S R Flip Flop drawn in Figure 8.19(c). We know that a low input on the NAND gate will set the output high. Thus a low on the input S will set the latch Q = 1 ( Q = 0) whereas a low on the R input will reset the latch Q = 0 ( Q = 1). A high on both the inputs will make the outputs to the previous state. But a low on both the inputs will make the outputs Q = 1 ( Q = 1) which is forbidden. SR Flip Flop can be realized from the S R Flip Flop with the help of two single input NAND gates (inverters) at the input of S R Flip Flops as shown in Figure 8.20(a). This S-R Flip Flop is an asynchronous circuit as it is independent of clock for its working. An S-R Flip Flop can be modified to a synchronous circuit by changing the connections as depicted in Figure 8.20(b). If Clock = 0, both the input NAND gates NAND-3 and NAND-4 are disabled and the circuit is disabled. If Clock = 1, the circuit will behave like a normal S-R Flip Flop.
Q
QR
SS R Q
Q
Q
S
R
(a) (b) (c)
Figure 8.19 : (a) An S R Flip-Flop, (b) Truth Table, and (c) Logic Symbol
Q
QR
S Q
Q
R
S
(a) (b)
Figure 8.20 : (a) An S-R Flip-Flop from S R Flip Flop, and (b) Clocked S-R Flip Flop
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Digital ElectronicsJK-type Flip Flops
JK Flip Flop can be achieved from the clocked SR Flip Flop of Figure 8.20(b) by adding two additional AND gates at the input as shown in Figure 8.21(a). For this case, S J Q= and R K Q= . The truth table for JK Flip Flop is drawn in Figure 8.21(b). Let us try to arrive at this truth table of JK Flip Flop from the detailed truth table of Table 8.7. There are four possible combinations of inputs J and K. For each of these combinations there are two possible states of Q, hence, there are 8 rows in the Table 8.7. From the values of J, K, Q and Q , the values S and R are calculated and listed in different columns in the same Table. Using these values of S and R we can calculate the values of Q at the next time instant. Note that columns 1, 2 and 8 of this Table form the JK Flip Flop truth table of Figure 8.21(b). In Table 8.7, toggle basically means the output will become complement of the last state.
Table 8.7 : Truth Table of JK Flip Flop
J K Q Q S R Q
0 0 0 1 0 0 Last State
0 0 1 0 0 0 Last State
Last State
1 0 0 1 1 0 1
1 0 1 0 0 0 Last State
1
0 1 0 1 0 0 Last State
0 1 1 0 0 1 0
0
1 1 0 1 1 0 1
1 1 1 0 0 1 0
Toggle
K
JQ
Q J K Q
Figure 8.21 : (a) Additional Connections and Logic Gates of an S-R Flip-Flop to Modify to a JK Flip-Flop, and (b) Truth Table
Preset and Clear Inputs
JK Flip Flops are usually clocked Flip Flops. But we can add PRESET and CLEAR inputs to the JK Flip Flops as illustrated in Figure 8.22(a). They are negative enabled inputs that mean they will be active only when they are low. These inputs override the other states of the Flip Flops and they are termed as asynchronous or forced inputs. If PR = 0 and CL = 1, then Q will become 1 no matter what are the values of J and K. Similarly, if PR = 1 and CL = 0, then Q will change to 0 for any values of J and K inputs. Only when PR = 1 and CL = 1, these forced or asynchronous inputs are disabled and it will behave like the normal JK Flip Flop. But the case when PR = 0 and CL = 0 is forbidden since that will make Q = 1 and Q = 1. All these states of JK Flip Flops with PR and CL inputs are summarized in the truth table of Figure 8.22(b).
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Q
Q
Q
(a) (b)
Figure 8.22 : (a) JK Type Flip Flop with PR and CLR Asynchronous Inputs, and (b) Truth Table
D-type Flip Flops
If a JK Flip Flop is modified by adding an inverter at the input as shown in Figure 8.23(a) thereby J and K inputs are always complementary to each other then we call such Flip-Flops as a D-type Flip Flops. Such Flip Flops act as a delay unit where the output follows the input which is delayed by a bit time, i.e. Qn + 1 at the (n + 1)th time instant is equal to Dn at the nth time instant. This can be verified from the truth table of JK Flip Flop when Dn = Jn = nK = 1, then Qn + 1 = 1, when Dn = Jn = nK = 0, then Qn + 1 = 0. Therefore the truth table for D Flip Flop can be summed up to this Boolean equation : Qn + 1 = Dn. That is the output Qn + 1 after n + 1 bit time is equal to the input Dn at the previous n bit time instant. We can also realize a D-type Flip Flop from SR Flip Flop by making the same connection in the inputs S and R as shown in Figure 8.23(b). Both the JK type and SR type Flip Flop has the same truth table as depicted in Figure 8.23(c).
Q
Q
Q
Q
(a) (b) (c)
Figure 8.23 : (a) JK Type, (b) SR Type D Flip Flop, and (c) Truth Table of a D Flip Flop
T-type Flip Flops
Let us study clocked pulse first. It will be a little bit of digression, but this will be necessary to understand Toggle Flip Flop properly. In order to bring synchronism into digital circuits many digital systems are clocked or pulsed and they operate in synchronism with a pulse train of period T depicted in Figure 8.24. The pulse width tp is assumed small compared to the time period T. The binary values are assumed to be constant during any interval T and it changes its state during clocked pulse either at the negative transition (negative triggered Flip Flops) or positive transition (positive triggered Flip Flops) of the pulse. Any output value of the logic circuit at the nth time instant (nT time interval) is represented by Qn and at (n + 1)th time instant ((n + 1) T time interval) is represented by Qn + 1.
Figure 8.24 : Clock Pulse Train to Synchronize a Sequential Digital Circuits
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Digital ElectronicsThe T-type Flip Flop changes its states with every clocked pulse and hence it is called as
Toggle (T) Flip Flop. T Flip Flops are realized by shorting the two input terminals of a JK Flip Flop as illustrated in Figure 8.25(a) and its truth table is drawn in Figure 8.25(b). Let us try to understand the truth table for such Flip Flops. When T = J = K = 1, Q toggles between 0 and 1 as the clock makes transition and hence it gives rise to toggling. Usually the T input is tied to 1 to make this happen. When T = 0, it behaves like a D type Flip Flop. It should be noted that we cannot construct T-type Flip Flops from SR Flip Flops since S = R = 1 is forbidden for SR Flip Flops.
Q
Q
Qn
Qn
(a) (b)
Figure 8.25 : (a) Toggle Flip Flop, and (b) Truth Table of T Flip Flop
8.5.2 Shift Registers A Flip Flop can store a single bit of information and to store several bits of data we need a series of Flip Flops, which are connected in cascade and such a group of Flip Flops, are called as Shift Registers. A three-element Shift Register is depicted in Figure 8.26 and it is constructed using three D type Flip Flops, which are connected in cascade form. It can store 3 bits of information. n Flip Flops can store n bits of information.
Figure 8.26 : 3-element Shift Register using D Flip Flops
The bits can be moved in the shift registers in two ways. Firstly, it can be moved into the shift register in serial fashion one by one at a time instant starting from the Most Significant Bit (MSB) or Least Significant Bit (LSB) and it is called Serial Shifting. Note that the MSB (left-most binary digit) and LSB (right-most binary digit) for the data 1110 is 1 and 0, respectively. Secondly all the bits of information can be shifted simultaneously at a time instant and it is called Parallel Shifting. Since there are two ways to shift in the data, similarly there are two ways to shift out a data. Shift registers can be classified into four for each case :
• Serial-in, serial out (SISO)
• Serial-in, parallel out (SIPO)
• Parallel-in, parallel out (PIPO)
• Parallel-in, serial out (PISO)
Let us study them one by one.
SISO Shift Register
A SISO shift register is depicted in Figure 8.27. Here the data are serially entered one by one through the input terminal D1 and serially taken out through Q3. When the first clock pulse is applied, data from D1 will go to Q1, D2 will go to Q2 and D3 will go to Q3. For each clock pulse, the data will get shifted through the Flip Flops
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in progression and they can be read from the output Q3 serially in synchronism with the system clock pulse. For example when a data 01101 is entered through D1, the shifting of bit information for each clock pulse is given in Figure 8.27. Note that the first data to be entered for SISO Shift Register is MSB and for this case is 0. Then in the next clock pulse the next MSB, i.e. 1 is entered to D1 and so on.
Electronics
Vol
tage
Figure 8.27 : Shift Table for 3 Element SISO Shift Register
SIPO Shift Register
If the output lines are directly taken out from Q1, Q2 and Q3 as shown in Figure 8.28, then we can achieve SIPO shift registers. For SIPO shift registers the data are entered serially through D1 and read out simultaneously from Q1, Q2 and Q3. They can be used for applications of serial to parallel conversions.
Figure 8.28 : SIPO Shift Registers
PIPO Shift Register
In Figure 8.29, if PR = 1 and CLR = 0, all the Flip Flops will be cleared, i.e. Q1 = Q2 = Q3 = 0. Now by applying CLR = 1, parallel data are applied at the PRESET terminals PR1, PR2 and PR3 and Preset and all the outputs will be loaded with the parallel data and they will be immediately available at Q1, Q2 and Q3.
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Figure 8.29 : PIPO Shift Registers
PISO Shift Register
If the clocking pulse is applied in sequence in Figure 8.29, we can get data serially at the output P3 only and it results in a PISO shift register.
Applications of Shift Registers
(a) As a Delay Line : n number of D Flip Flops connected in series (SISO shift register) as depicted in Figure 8.30(a) produces a propagation delay of n tp where tp is the propagation delay for one D Flip Flop and it can be used as delay line for applications in computers.
(b) As a Sequence Generator : It can be realized using a PISO shift register as depicted in Figure 8.30(b). Let us assume that the waveform to be generated as shown in Figure 8.30(c) and its binary equivalent is 11100 where 1s represent positive voltage and 0 represents zero voltage. For this particular case, w can enter the data 11100 in parallel fashion at the preset terminals PR1 = 1, PR2 = 1, PR3 = 1, PR4 = 0 and PR5 = 0 keeping CLR = 1. The data will appear at the outputs of the Flip Flops and they can be taken out serially at the last output of Flip Flop by applying clock pulse.
Figure 8.30 : (a) SISO Shift Register as a Delay Line, (b) PISO Shift Register as a Sequence Generator, and (c) Waveform for Sequence Generator
(c) As a Ring Counter : Consider the 3-bit shift register of Figure 8.29. Assume that all the Flip Flops are cleared and then Flip Flop 1 is preset so that Q1 = 1 and Q2 = Q3 = 0. During the first clock, the data from Q1 will be transferred to Q2. Thus the data will be progressively transferred around the Shift Register with each clock pulse. If the last output Q3 and D1 are connected then the 1 state will keep on circulating in the Flip Flops of the shift registers and it is called a Ring Counter and the count is read by noting which Flip Flop of the Shift Register is in state 1. For N Flip Flop based ring counters, it acts as a
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Divide by N counter since there is one output pulse for each clock pulse for N clock pulse.
Electronics
Figure 8.30 : (d) Movement of State 1 in the SISO Shift Register Functioning as a Ring Counter
8.5.3 Counters Asynchronous (Ripple) Counters
Consider a chain of four T-type Flip Flop with the output Q of each stage connected to the clock input of the following T Flip Flop as shown in Figure 8.31. The pulses to be counted are applied to the clock input of the first Flip Flop. Here the T input for all the Flip Flops is tied to 1 hence it acts as Toggle Flip Flop. Q1 changes state at the falling edge of each pulse. All other Q’s make changes its states only when the Flip Flop changes from 1 to 0. This negative transition “ripples” through the counter from the LSB to the MSB. This will be clearer from the waveform chart given in Figure 8.32 and Table 8.8 lists the states of all the binaries of the ripple counter. Let us see how to draw this waveform chart of Figure 8.32. Knowing that the Q1 changes its state at the negative transition of clock pulse we can draw the waveform for output Q1. Knowing that the Q2 changes its state at the negative transition of Q1 we can draw the waveform for output Q2 and so on. Let us see how to read this waveform to get the binary count number. Let us assume that the 4th pulse is already given to Clock input of the Ripple Counter, then we can read the binary count as 0100 (decimal value is 4) as shown in Figure 8.32. Similarly after the 5th pulse is given to Clock input of Figure 8.32 we can read the binary count as 0101 (decimal value is 5). So basically it is up counting the binary numbers.
Figure 8.31 : A Group of T-type Flip Flops Acting as a Ring Counter
Figure 8.32 : Waveform Chart of Four-stage Ripple Counter
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Digital ElectronicsTable 8.8 : States of Flip Flops for Ripple Counter
Flip Flop Outputs No. of Input Pulses
Q4 Q3 Q2 Q1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
Synchronous Counters
In Synchronous counters the Flip Flops are triggered in synchronism with the clock unlike the ripple or asynchronous counters. There are some inherent problems with the ripple counters since each Flip Flop has a time delay. The overall time delay of a ripple counter is the summation of time delays of each Flip Flops, which limits the highest operating frequency of counters. The Synchronous counter depicted in Figure 8.33 has overcome this problem by some kind of parallel operation. The truth table is the same as in Table 8.8 and the waveform chart is also the same as illustrated in Figure 8.32. Let us try to understand the operation of these binary counters. Each Flip Flop is a T-type Flip Flop with the input T tied to 1 and hence it acts as toggle Flip Flop. The Clock input has some modifications for parallel operation as shown in Figure 8.33. Whenever Q1 is high, AND-1 output is high; a clock pulse is passed through the clock input of second Flip Flop. Thus Q2 changes its state at the negative transition of pulse 1, 3, 5 and 7. Note that these Flip Flops are negative triggered Flip Flops. The AND-2 output is high only when Q1 and Q2 are high thereby enabling the third Flip Flop hence the Q3 will change state at the negative transition of pulse number 3 and 7 only. If we try to write down the Binary numbers, which are made up of values of Q1, Q2, Q3 and Q4 for different time periods from the waveform chart of Figure 8.32, we will get the Truth Table 8.8 which is basically a upward binary count for mod-16 parallel counter. Note that the problem of propagation delay has been overcome in such counters since all the Flip Flops changes its state at the same time or in synchronism with the system clock pulse. The waveform chart and truth table for the synchronous counter is the same with the previous ripple counter only that now we are changing the states of the Flip Flops simultaneously or in synchronism with system clock.
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Q1 Q2 Q3 Q4
Pulses
1 T1 T2 T3 T4
Ck Ck Ck Ck
AND-1 AND-2 AND-3
Figure 8.33 : Four Element Synchronous Counter
SAQ 5 (a) How to realize D-type and T-type Flip Flops from JK Flip Flops? Is it
possible to realize T-type Flip Flop from SR Flip Flop?
(b) What are Shift Registers? What are the different types of Shift Registers?
(c) What is the difference between Synchronous and Asynchronous Counters? What are the functions of Counters? Which Flip Flops are used for construction of Counters?
8.6 TTL AND CMOS CIRCUITS
8.6.1 TTL Circuits TTL is the short form of transistor transistor logic. As the name suggests here transistors are used for realization of digital logic or circuits. For our purpose, it will be necessary to know how the bipolar junction transistor (BJT) acts as a switch. It will be a digression from the main topic. Nonetheless, the following topic cannot be understood without having knowledge of this. There are two types of BJTs viz. npn and pnp and their corresponding symbols are depicted in Figures 8.34(a) and (b), respectively. Both the BJT has terminals termed as base, collector and emitter as also shown in the same Figure. Let us see how they behave as an electronic switch. When the voltage between the base and emitter is zero, the switch is open, there is no current between collector and emitter junction and the transistor is off. Whereas when the voltage between the base and emitter is non-zero, the switch is closed, there is current between collector and emitter junction and the transistor is on. Note that the voltage applied between the base and emitter should be positive for npn transistor whereas it should be negative for pnp transistor. For npn transistor the direction of current is out of the transistor whereas it is into the transistor for pnp transistor. BJT can realize the switch shown in Figure 8.34(c) as we have discussed above.
The most fundamental TTL logic gate is NAND gate as depicted in Figure 8.34(d). In this circuit, TA is a multiple emitter transistor and in this transistor there is only one collector and base but there are multiple emitters. Here the multiple base emitter junction behaves just like an independent diodes. The actual practical circuit has an additional totem pole output driver as illustrated in Figure 8.34(e). Let us try to understand how this circuit behaves like a NAND gate. When Input1 and Input2 are at 0 V, the multiple emitter base junctions of transistor TA are forward biased whereas the base collector is
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VB
cc. Since the base voltage for transistor TC is Vcc, this transistor is on and the output is also Vcc. And the input to transistor TD is 0 V, hence it remains off. When either one of the Input 1 and Input 2 is 0 V, the corresponding collector emitter junction of transistor TA is conducting then it has the same operation with the previous case and the output is at Vcc. For the case when Input1 and Input 2 are at Vcc, both the base emitter junctions are reverse biased and the base collector junction of the transistor TA is forward biased therefore the transistor TBB is on. Hence the input to transistor TC is 0 V and the input to transistor TD is 0.8 V hence TD is on. Therefore the output voltage at the collector of transistor TB is 0.8 V + VB CES (saturation voltage between conductor and emitter of a transitor is equal to 0.2 V) = 1 V. Since Diode D is present TC remains in off state. But TD is on, the collector emitter voltage of the TD in saturation is 0.2 V and the output is also equal to 0.2 V, i.e. at logic 0.
Figure 8.34 : (a) npn BJT, (b) pnp BJT, (c) Switch Configuration, (d) Simplified TTL NAND Gate, and (e) TTL NAND Gate with Totem Pole Output Configuration
8.6.2 CMOS Circuits Before we go to CMOS circuits we must understand what is CMOS and how does it behave like a switch. Even before that let us study NMOS and PMOS since complementary MOS (CMOS) constitute of NMOS FET and PMOS FET. Negative MOS FET (NMOS FET) depicted in Figure 8.35(a) acts as negative logic device and Positive MOS FET (PMOS FET) depicted in Figure 8.35(b) acts as positive logic device. Note that the current direction for PMOS FET is into the transistor whereas it is out of the transistor for NMOS FET. The three terminals of a FET are termed as Gate, Source and Drain. Field Effect Transistor is a type of transistor and it is abbreviated as FET. A circuit diagram of CMOS is drawn in Figure 8.35(c), which is a combination of NMOS FET and PMOS FET. For our purpose, we just need to understand the following two points on the operation of CMOS devices :
(i) A Vcc input on the gate of NMOS FET will turn it on whereas it will turn off the PMOS FET.
(ii) A 0 V input on the gate of NMOS FET will turn it off whereas it will turn on the PMOS FET.
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Input Output
Vcc
Input 1
Input 2
VccVcc
Input 1Input 2
OutputInput 1 Input 2
Output
Input 1
Input 2
TN
TP
TN2
TN1
TP1TP2
TN1 TN2
TP1
TP2
(d) (e) (f)
Figure 8.35 : (a) NMOS FET, (b) PMOS FET, (c) CMOS FET, (d) CMOS NOT Gate, (e) CMOS NAND Gate, and (f) CMOS NOR Gate
CMOS NOT Gate
Figure 8.35(d) depicts the CMOS NOT Gate where TN is NMOS FET and TP is PMOS FET. When input is at 0 V, TP is on, TN is off and the output is at Vcc. But when input is at Vcc, TP is off and TN is on and the output is at 0 V. So the CMOS circuit of Figure 8.35(d) acts as NOT gate.
CMOS NAND Gate
Figure 8.35(e) depicts the CMOS NAND Gate where the TN1 and TP1 have the same Input1 and TN2 and TP2 has the same Input 2. When Input 1 = Input 2 = 1, TN1 and TN2 is on and TP1 and TP1 are off. Therefore the output is at 0 V. When Input 1 = Input 2 = 0, TN1 and TN2 is off and TP1 and TP1 are on. Hence the output is at Vcc. For the case when either one of the inputs is 0, one of the PMOS FET will be on and hence the output will be at 1 V. Thus the CMOS circuit of Figure 8.35(e) acts as a NAND Gate.
CMOS NOR Gate
Figure 8.35(f) depicts the CMOS NOR Gate where the TN1 and TP1 has the same Input 1 and TN2 and TP2 has the same Input 2. When Input 1 = Input 2 = 1, TN1 and TN2 is on and TP1 and TP1 are off. Therefore the output is at 0 V. When Input 1 = Input 2 = 0, TN1 and TN2 is off and TP1 and TP1 are on. Hence the output is at Vcc. For the case when one of the inputs is 1, one of the NMOS FET will be on and hence the output will be at 0 V. Thus the CMOS circuit of Figure 8.35(f) acts as a NOR Gate.
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Digital ElectronicsSAQ 6
(a) Draw the TTL NAND gate circuit and explain its operation. (b) Draw the CMOS NOT and NOR gate circuits.
8.7 MEMORIES
Computer possesses memories like human beings. There are two kinds of computer memory viz., volatile memory and non-volatile memory. As the name suggests volatile memories are not permanent and they go away when there is no power supply to computers. They are also called as Random Access Memory (RAM). Non-volatile memories do not go away when the computer is switched off. Such kinds of memories are also called as Read Only Memory (ROM). When we store information in some kind of circuit or device, we not only needs some way to store and retrieve it, but also to locate precisely where in the device that it is. Most, if not all, memory devices can be thought of as a series of mailboxes, folders in a file cabinet, or some other metaphor where information can be located in a variety of places. When we refer to the actual information being stored in the memory device, we usually refer to it as the data. The location of this data within the storage device is typically called the address, in a manner reminiscent of the postal service. With some types of memory devices, the address in which certain data is stored can be called up by means of parallel data lines in a digital circuit. With other types of devices, data is addressed in terms of an actual physical location on the surface of some type of media (the tracks and sectors of circular computer disks, for instance). However, some memory devices such as magnetic tapes have a one-dimensional type of data addressing: if you want to play your favorite song in the middle of a cassette tape album, you have to fast-forward to that spot in the tape, arriving at the proper spot by means of trial-and-error, judging the approximate area by means of a counter that keeps track of tape position, and/or by the amount of time it takes to get there from the beginning of the tape. The access of data from a storage device falls roughly into two categories: random access and sequential access. Random access means that you can quickly and precisely address a specific data location within the device, and non-random simply means that you cannot. A vinyl record platter is an example of a random-access device: to skip to any song, you just position the stylus arm at whatever location on the record that you want (compact audio disks so the same thing, only they do it automatically for you). Cassette tape, on the other hand, is sequential. You have to wait to go past the other songs in sequence before you can access or address the song that you want to skip to. The process of storing a piece of data to a memory device is called writing, and the process of retrieving data is called reading. Memory devices allowing both reading and writing are equipped with a way to distinguish between the two tasks, so that no mistake is made by the user (writing new information to a device when all you wanted to do is see what was stored there). Some devices do not allow for the writing of new data, and are purchased “pre-written” from the manufacturer. Such is the case for vinyl records and compact audio disks, and this is typically referred to in the digital world as read-only memory, or ROM. Cassette audio and video tape, on the other hand, can be re-recorded (re-written) or purchased blank and recorded fresh by the user. This is often called read-write memory. Another distinction to be made for any particular memory technology is its volatility, or data storage permanence without power. Many electronic memory devices store binary data by means of circuits that are either latched in a “high” or “low” state, and this latching effect holds only as long as electric power is maintained to those circuits. Such memory would be properly referred to as volatile. Storage media such as magnetized disk or tape is nonvolatile, because no source of power is needed to maintain data storage. This is often confusing for new students of computer technology, because the volatile electronic memory typically used for the construction of computer devices is commonly and distinctly referred to as RAM (Random Access Memory). While RAM memory is typically randomly-accessed, so is
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virtually every other kind of memory device in the computer. Nonvolatile memory integrated circuits in personal computers are commonly (and properly) referred to as ROM (Read-Only Memory), but their data contents are accessed randomly, just like the volatile memory circuits. Finally, there needs to be a way to denote how much data can be stored by any particular memory device. This, fortunately for us, is very simple and straightforward: just count up the number of bits (or bytes, 1 byte = 8 bits) of total data storage space. Due to the high capacity of modern data storage devices, metric prefixes are generally affixed to the unit of bytes in order to represent storage space : 1.6 Gigabytes is equal to 1.6 billion bytes, or 12.8 billion bits, of data storage capacity. The only caveat here is to be aware of rounded numbers. Because the storage mechanisms of many random-access memory devices are typically arranged so that the number of “cells” in which bits of data can be stored appears in binary progression (powers of 2), a “one kilobyte” memory device most likely contains 1024 (2 to the power of 10) locations for data bytes rather than exactly 1000. A “64 kbyte” memory device actually holds 65,536 bytes of data (2 to the 16th power), and should probably be called a “66 kbyte” device to be more precise. When we round numbers in our base-10 system, we fall out of step with the round equivalents in the base-2 system. Let us try to understand basic memory digital circuits for ROM and RAM.
8.7.1 Read Only Memory (ROM) Read-only memory (ROM) is similar in design to static or dynamic RAM circuits, except that the “latching” mechanism is made for one-time (or limited) operation. The simplest type of ROM is that which uses tiny “fuses” which can be selectively blown or left alone to represent the two binary states. Obviously, once one of the little fuses is blown, it cannot be made whole again, so the writing of such ROM circuits is one-time only. Because it can be written (programmed) once, these circuits are sometimes referred to as PROMs (Programmable Read-Only Memory). However, not all writing methods are as permanent as blown fuses. If a transistor latch can be made which is resettable only with significant effort, a memory device that's something of a cross between a RAM and a ROM can be built. Such a device is given a rather oxymoronic name: the EPROM (Erasable Programmable Read-Only Memory). EPROMs come in two basic varieties: Electrically-erasable (EEPROM) and Ultraviolet-erasable (UV/EPROM). Both types of EPROMs use capacitive charge MOSFET devices to latch on or off. UV/EPROMs are “cleared” by long-term exposure to ultraviolet light. They are easy to identify: they have a transparent glass window which exposes the silicon chip material to light. Once programmed, you must cover that glass window with tape to prevent ambient light from degrading the data over time. EPROMs are often programmed using higher signal voltages than what is used during “read-only” mode. Although transistors are used for realization of Read Only Memory, it will be good to understand how does a ROM works using the diodes for easy understanding. A typical diode matrix network for realization of ROM is depicted in Figure 8.36. In this network, whichever switch is closed, those diodes will conduct and the output will be high (1), sections where there is no diode connected there will be no current flowing and the output will be low (0). For instance, when we close the switch S5, the diodes D6 and D7 are on and they are at high (1), therefore Output 1 = 1, Output 3 = 1 whereas Output 2 = 0, Output 4 = 0 since diodes are not connected. Hence the corresponding binary number is 0101 and its decimal value is 5. Therefore we can connect to the computer keyboard button 5 with the switch S5. Similarly we can realize all other buttons on the computer keyboard. Since such circuits can realize all decimal numbers and alphabets on the computer keyboard into equivalent binary representations, which could be understood by digital computers, we called such circuits as encoder. Next question is how to realize such circuits using transistors instead of using diodes. It is quite simple, in the previous section, we have used BJTs with multiple emitters as independent diodes, we can use such transistors since each base emitter junctions of such transistors act as independent diodes and in the emitter junction we can tie the output resistors.
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D1
D2
D3 D4
D5
D6 D7
D8 D9
D10 D11 D12
D13
D14 D15
R1R2R3R4
S1
S2
S3
S4
S5
S6
S7
S8
S9
Output1Output2Output3Output4
Figure 8.36 : A Diode ROM Matrix
8.7.2 Random Access Memory (RAM) RAM is the main memory of the computer. It controls the computer speed. Information can be randomly written or read from such memories and hence the name Random Access Memory or RAM. We can use SR Type or JK Type Flip Flops to realize a RAM. Let us try to understand a basic element of RAM as depicted in Figure 8.37. To write an input to the Flip Flop, we enable the inputs AND-1 and AND-2 by keeping it high. If the write input is 1 (0), then the S/J input is 1(0), R/K input is 0(1), Q value is 1 (0). To read an input, we make the Address line high, therefore AND-3 is enabled and we read the output 1 (0) for this particular case.
A very simple type of electronic memory is the bistable multivibrator. Capable of storing a single bit of data, it is volatile (requiring power to maintain its memory) and very fast. The D-latch is probably the simplest implementation of a bistable multivibrator for memory usage, the D input serving as the data “write” input, the Q output serving as the “read” output, and the enable input serving as the read/write control line as shown in Figure 8.37(a). If we desire more than one bit’s worth of storage (and we probably do), we will have to have many latches arranged in some kind of an array where we can selectively address which one (or which set) we’re reading from or writing to. Using a pair of tristate buffers, we can connect both the data write input and the data read output to a common data bus line, and enable those buffers to either connect the Q output to the data line (READ), connect the D input to the data line (WRITE), or keep both buffers in the High-Z state to disconnect D and Q from the data line (unaddressed mode). One memory “cell” would look like this, internally as depicted in Figure 8.37(b). In Figure 8.37(c), when the address enable input is 0, both tristate buffers will be placed in high-Z mode, and the latch will be disconnected from the data input/output (bus) line. Only when the address enable input is active (1) will the latch be connected to the data bus. Every latch circuit, of course, will be enabled with a different “address enable” (AE) input line, which will come from a 1-of-n output decoder. In the above circuit, 16 memory cells are individually addressed with a 4-bit binary code input into the decoder. If a cell is not addressed, it will be disconnected from the 1-bit data bus by its internal tristate buffers : consequently, data cannot be either written or read through the bus to or from that cell.
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D QEData write Data read
Read/Write
A0
A1
A2
A3
AEE
Data
AEE
Data
Read/Write
Address EnableMemory cell 15
Memory cell 14
Memory cell 0
Memory cell 1Memory cell 2Memory cell 3Memory cell 4Memory cell 5Memory cell 6Memory cell 7Memory cell 8Memory cell 9Memory cell 10Memory cell 11Memory cell 12Memory cell 13
1-bit data bus
(c)
(a)
Address
J Q
Enable Input
K
Write Read
(b)
Figure 8.37 : (a) A Simple RAM, (b) Basic RAM Cell, and (c) 16 × 1 Bit Memory
Only the cell circuit that is addressed by the 4-bit decoder input will be accessible through the data bus. This simple memory circuit is random-access and volatile. Technically, it is known as a static RAM. Its total memory capacity is 16 bits. Since it contains 16 addresses and has a data bus that is 1 bit wide, it would be designated as a 16 × 1 bit static RAM circuit. As you can see, it takes an incredible number of gates (and multiple transistors per gate) to construct a practical static RAM circuit. This makes the static RAM a relatively low-density device, with less capacity than most other types of RAM technology per unit IC chip space. Because each cell circuit consumes a certain amount of power, the overall power consumption for a large array of cells can be quite high. Early static RAM banks in personal computers consumed a fair amount of power and generated a lot of heat, too. CMOS IC technology has made it possible to lower the specific power consumption of static RAM circuits, but low storage density is still an issue. To address this, engineers turned to the capacitor instead of the bistable multivibrator as a means of storing binary data. A tiny capacitor could serve as a memory cell, complete with a single MOSFET transistor for connecting it to the data bus for charging (writing a 1), discharging (writing a 0), or reading. Unfortunately, such tiny capacitors have very small capacitances, and their charge tends to “leak” away through any circuit impedances quite rapidly. To combat this tendency, engineers designed circuits internal to the RAM memory chip which would periodically read all cells and recharge (or “refresh”) the capacitors as needed. Although this added to the complexity of the circuit, it still required far less componentry than a RAM built of multivibrators. They called this type of memory circuit a dynamic RAM, because of its need of periodic refreshing. Recent advances in IC chip manufacturing has led to the introduction of flash memory, which works on a capacitive storage principle like the dynamic RAM, but uses the insulated gate of a MOSFET as the capacitor itself. Before the advent of transistors (especially the MOSFET), engineers had to implement digital circuitry with gates constructed from vacuum tubes. As you can imagine, the enormous comparative size and power consumption of a vacuum tube as compared to a transistor made memory circuits
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Digital Electronicslike static and dynamic RAM a practical impossibility. Other, rather ingenious,
techniques to store digital data without the use of moving parts were developed.
SAQ 7 (a) Draw the Diode ROM matrix and a basic RAM cell.
(b) What is the difference between volatile and non-volatile memory?
8.8 MODEM
What does MODEM stands for? The modem is a peripheral device for computers, which allows two computers to communicate over standard phone lines. Modems come in many shapes and sizes to serve all sorts of needs. So how exactly does this common device work? The word modem stands for modulator-demodulator. A modem’s main purpose is to convert digital information to analog signals (DAC) and to convert analog signals back into useful digital information (ADC) along with modulation and demodulation. Let us study ADC and DAC in brief. Connecting digital circuitry to sensor devices is simple if the sensor devices are inherently digital themselves. Switches, relays, and encoders are easily interfaced with gate circuits due to the on/off nature of their signals. However, when analog devices are involved, interfacing becomes much more complex. What is needed is a way to electronically translate analog signals into digital (binary) quantities, and vica-versa. An analog-to-digital converter, or ADC, performs the former task while a digital-to-analog converter, or DAC, performs the latter. An ADC inputs an analog electrical signal such as voltage or current and outputs a binary number. In block diagram form, it can be represented as in Figure 8.38(a). A DAC, on the other hand, inputs a binary number and outputs an analog voltage or current signal. In block diagram form, it looks like Figure 8.38(b). Together, they are often used in digital systems to provide complete interface with analog sensors and output devices for control systems such as those used in automotive engine controls as in Figure 8.39(c). It is much easier to convert a digital signal into an analog signal than it is to do the reverse. Therefore, we will begin with DAC circuitry and then move to ADC circuitry.
(a) (b)
(c)
Figure 8.38 : Block Diagram of (a) ADC; (b) DAC; and (c) Combined A/D, D/A Converters
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Suppose we were to set the input resistor values at multiple powers of two : R, 2R, and 4R of the comparator circuit of Figure 8.39(a). Starting from V1 and going through V3, this would give each input voltage exactly half the effect on the output as the voltage before it. In other words, input voltage V1 has a 1 : 1 effect on the output voltage (gain of 1), while input voltage V2 has half that much effect on the output (a gain of 1/2), and V3 half of that (a gain of 1/4). These ratios are not arbitrarily chosen: they are the same ratios corresponding to place weights in the binary number system. If we drive the inputs of this circuit with digital gates so that each input is either 0 volts or full supply voltage, the output voltage will be an analog representation of the binary value of these three bits. If we wish to expand the resolution of this DAC (add more bits to the input), all we need to do is add more input resistors, holding to the same power-of-two sequence of values as in Figure 8.39(b).
Electronics
(a)
(b) Figure 8.39 : (a) Simple 3-bit DAC; and (b) 6-bit Binary-weighted DAC
Also called the parallel A/D converter, the circuit of Figure 8.40 is the simple to understand. It is formed of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which then produces a binary output. Following illustration of Figure 8.40 shows a 3-bit flash ADC circuit. And, of course, the encoder circuit itself can be made from a matrix of diodes of Figure 8.36, demonstrating just how simply this converter design may be constructed. Not only is the flash converter the simplest in terms of operational theory, but it is the most efficient of the ADC technologies in terms of speed, being limited only in comparator and gate propagation delays. Unfortunately, it is the most component-intensive for any given number of output bits. This three-bit flash ADC requires eight comparators. A four-bit version would require 16 comparators. With each additional output bit, the number of required comparators doubles. Considering that eight bits is generally considered the minimum necessary for any practical ADC (256 comparators needed), the flash methodology quickly shows its weakness. An additional advantage of the flash converter, often overlooked, is the ability for it to produce a non-linear output. With equal-value resistors in the reference voltage divider network, each successive binary count represents the same amount of analog signal increase, providing a proportional response. For special applications, however, the resistor values in the divider network may be made non-equal. This gives the ADC a
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Digital Electronicscustom, nonlinear response to the analog input signal. No other ADC design is able to
grant this signal-conditioning behaviour with just a few component value changes.
Figure 8.40 : Parallel ADC
SAQ 8 (a) What is the full form of MODEM? What are the basic functions of a
MODEM?
(b) Draw a circuit diagram of DAC and ADC.
8.9 SUMMARY
In this unit, we have learned the fundamentals of Digital circuits. First we have studied the mathematics of Binary numbers also called as Boolean algebra and how to implement this Boolean algebra in digital circuits with the help of Logic gates. Then we have done a thorough study of how to make K-maps from the truth tables of SOP equations and how to simplify K-maps to get the most simplified combinatorial logic circuits. A digital system, which uses Binary numbers, has only two possible states. But for some specific applications we need an extra state called High Z state, here comes the ideas/concepts of Tristate Logic gates. Till now whatever combinatorial logic circuits considered were asynchronous circuits. In the next section we have studied Sequential circuits like Flip Flops, Counters and Shift registers which works in synchronism with the clock pulse. Next we have studied how transistors are used for realization of digital circuits viz. TTL and CMOS circuits. We have also investigated different kinds of memories in the computers: volatile, non-volatile, Read only and Random access memories. Finally, we tried to understand the main function of MODEMs and have also studied simple ADC and DAC circuits.
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Electronics 8.10 ANSWERS TO SAQ
SAQ 1
(a) Tie the two inputs of a AND gate it will give us a buffer as depicted in Figure 8.41(a).
Figure 8.41 : SAQ 1 (a), (b) and (c)
(b) Symbol of three input OR gate is shown in Figure 8.41(b) and truth table in Table 8.9.
Table 8.9 : Truth table of three input OR gate
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
(c) Symbol of three input AND gate is shown in Figure 8.41(c) and truth table in Table 8.10.
Table 8.10 : Truth table of three input AND gate
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
SAQ 2
(a) ( 1) ( )A B AB AB A AB A B B A A A A+ + = + + = + + = + =
(b) ( ) ( )RHS A B A C AA AC BA BC A AC AB BC= + + = + + + = + + +
A AB BC A BC= + + = +
LHS=
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Digital ElectronicsSAQ 3
(a) Refer to Figure 8.10 for pairs, Figure 8.11 for quads and Figure 8.12 for octets in K-maps. For pairs a variable, for quads two variables and for octets three variables will get eliminated in K-maps.
(b) ( )Y ABC D ABC D A A BC D BC D= + = + =
CD CD CD CD
AB
AB
AB
AB
0 0
0
0
00
0
1
0 X
X
0
X0
0
0
BC YD
(a) (b)
Figure 8.42 : SAQ 3 (a) and (b)
Simplest logic circuit is shown in Figure 8.42(b).
SAQ 4
Tristate logic gates are devices with three operating states/modes whereas digital logic gates have only two operating modes. Refer to Figure 8.15 and Figure 8.17.
SAQ 5
(a) Refer to Figure 8.22(a) and Figure 8.23(a). No we cannot construct T-type Flip Flop from SR Flip Flops since S = R = 1 is forbidden for SR Flip Flops.
(b) To store several bits of data we need a series of Flip Flops, which are connected in cascade, and such a group of Flip Flops are called as Shift registers. There are four types of Shift registers viz. SISO, SIPO, PISO and PIPO.
(c) In Synchronous counters, the Flip Flops are triggered in synchronism with clock pulse unlike Asynchronous counters. T-type Flip Flops are generally used for construction of Counters.
SAQ 6
(a) Refer to CMOS NAND gate subsection of Section 8.6.2.
(b) Refer to Figures 8.35(d) and (e).
SAQ 7
(a) Refer to Figure 8.36 and Figure 8.37(b).
(b) Volatile memory goes away when the power is switched off whereas non-volatile memory retains when the power is off.
SAQ 8
(a) MODEM is the abbreviated form of Modulator and Demodulator. The main or basic function is Analog to Digital Conversion (ADC) and Digital to Analog Conversion (DAC).
(b) Refer to Figure 8.39 and Figure 8.40.
