Upload
suhel-mulla
View
323
Download
2
Tags:
Embed Size (px)
DESCRIPTION
Advanced Trends in Microprocessors Covered Topics : 1. Multicore Processor basics 2. Inbuit USB feature
Citation preview
04/10/2023 06:41 AM
A Seminar on ADVANCED TRENDS IN Microprocesssors
PRESENTED BY: 1. Suhel Mulla (MIS no: 121333009)
2. Anjani Gheware (MIS no: 121333003)
College of Engineering, Pune 1
04/10/2023 06:41 AM
Discussed TechnologyMicroprocessors advanced through many
stages in the course of time, different features are added to it,two of them which are discussed in the presentation are as follows :
Multicore processing
Inbuilt USB Connectivity
College of Engineering, Pune 2
04/10/2023 06:41 AM
Moore’s lawIt states that,
“For every 18 to 24 months later in IC fabrication, any one of below case possible –
1. No of transistors on a die gets doubled.2. Size of the chip gets halved.3. Operating frequency gets doubled.4. Supply voltage decreases by √2 times.
If any two conditions are satisfied, that is best design. Any three or all four can never be satisfied.”
College of Engineering, Pune 3
04/10/2023 06:41 AM
Why Multi-core……?? !!!Shrinking die size and increasing component
density has came to a limit.Escalating clock speed are boosting heat
dissipation problems.Sophisticated pipelining techniques have
reached an optimum balance between improving best case and doing minimum harm in worst case.
Thus, Multi-core processor is a way to extend Moore’s law so that the user gets more performance out of a single piece of silicon.College of Engineering, Pune 4
04/10/2023 06:41 AM
Contd… Computer architects needed a new approach to improve
performance. Adding an additional processing core to the same chip
would result in twice the performance and dissipate less heat.
The actual speed of each core is slower than the fastest single core processor.
IEEE Review noted that “the power consumption increases by 60% with every 400MHz rise in clock speed”. But the dual-core approach means you can get a significant boost in performance without the need to run at ruinous clock rates.”
College of Engineering, Pune 5
04/10/2023 06:41 AM
Microprocessors using multicore architecture
Intel’s Pentium D, core 2 duo & xenon series
AMD’s Athlon, Turion and Opteron series
Sony-Toshiba-IBM’s Cell Processor series
Tilera’s TILE64 Processor
College of Engineering, Pune 6
04/10/2023 06:41 AM
Conventional Processor Architecture
College of Engineering, Pune 7
04/10/2023 06:41 AM
Performance and design parameters of multicore processor systems
Power ConsumptionTemperature DissipationFrequency RequirementNo. of Cores in a dieType of cores ( Homogeneous or Heterogeneus )Communication Protocol (e.g. Round Robin, Daisy Chain etc.)Memory Configuration ( Universal vs. Distributed cache )
College of Engineering, Pune 8
04/10/2023 06:41 AM
Memory Models in Multi-core Processors
College of Engineering, Pune 9
a) Shared memory model b) Distributed memory model
04/10/2023 06:41 AM
Comparison of single core and Multi-core Processors
Multicore processors seem to answer the deficiencies of single core processors, by increasing bandwidth while decreasing power consumption.
College of Engineering, Pune 10
04/10/2023 06:41 AM
Intel and AMD Dual-Core Processors
College of Engineering, Pune 11
04/10/2023 06:41 AM
Multicore Challenges
Power and Temperature Dependence
Cache Coherence Problem
Multithreading
College of Engineering, Pune 12
04/10/2023 06:41 AM
Power and Temperature DependenceTo combat unnecessary power consumption
many designs incorporate a power control unit that has the authority to shut down unused cores or limit the amount of power. By powering off unused cores, the amount of leakage in the chip is reduced.
To lessen the heat generated by multiple cores on a single chip, the chip is architected so that the number of hot spots doesn’t grow too large and the heat is spread out across the chip.
College of Engineering, Pune 13
04/10/2023 06:41 AM
Contd…
College of Engineering, Pune 14
Cell Processor Thermal Digram
04/10/2023 06:41 AM
Cache Coherence
College of Engineering, Pune 15
In general there are two schemes for cache coherence, a snooping protocol and a directory-based protocol.
The snooping protocol only works with a bus-based system, and uses a number of states to determine whether or not it needs to update cache entries and if it has control over writing to the block. The directory-based protocol can be used on an arbitrary network and is, therefore, scalable to many processors or cores, in contrast to snooping which isn’t scalable
Intel’s Core 2 Duo tries to speed up cache coherence by being able to query the second core’s L1 cache and the shared L2 cache simultaneously. Having a shared L2 cache also has an added
benefit since a coherence protocol doesn‟t need to be set for this level. AMD‟s Athlon 64 X2,
04/10/2023 06:41 AM
Multi-threadingProgrammers have to write applications with
subroutines able to be run in different cores, meaning that data dependencies will have to be resolved or accounted for.
If one core is being used much more than another, the programmer is not taking full advantage of the multi-core system. Applications should be balanced.
Languages with multithreaded extensions are more useful for this purpose.
College of Engineering, Pune 16
04/10/2023 06:41 AM
Contd…In order to use a multi-core processor at full
capacity the applications run on the system must be multithreaded.
Programmers have to write applications with subroutines able to be run in different cores.
In recent time, companies like Apple, Microsoft designed new products with multi-core facility.
College of Engineering, Pune 17
04/10/2023 06:41 AM
Universal serial busFeatures:Easy to useFastReliableFlexibleInexpensivePower conserving
18College of Engineering, Pune
04/10/2023 06:41 AM
TERMS USED IN USBUSB HostUSB DeviceEnumerationHubEndpoint
19College of Engineering, Pune
04/10/2023 06:41 AM
Speed of usb
20College of Engineering, Pune
04/10/2023 06:41 AM
Bus Topology
21College of Engineering, Pune
04/10/2023 06:41 AM
Data flowControl TransferBulk TransferIsochronous TransferInterrupt Transfer
22College of Engineering, Pune
04/10/2023 06:41 AM
Electrical design
Fig : USB Cable
23College of Engineering, Pune
04/10/2023 06:41 AM
Powered deviceAt host should pull down register in range
14.25 to 24.8 kohm.Required pull up register of 500 to 900
ohmat device. Bus powerd device.Self power device.
24College of Engineering, Pune
04/10/2023 06:41 AM
References Bryan Schaumer, ”Multi-core Processor : A Necessity”,
Realised in Proquest September 2008 D. Geer, “Chip Makers Turn to Multi-core Processors”,
Computer, IEEE Computer Society, May 2009 W. Knight, “Two Heads Are Better Than One”, IEEE
Review, September 2009 P. Frost Gorder, “Multi-core Processors for Science and
Engineering”, IEEE CS, March/April 2007 “Universal Serial Bus Specification”, Revision 2.0,April
27, 2000 Jan Axelson, “USB Complete”, 2nd Edition, Penram
International Publishing.
College of Engineering, Pune 25
04/10/2023 06:41 AM
Any Questions… ???
College of Engineering, Pune 26
04/10/2023 06:41 AM
Thank You…!!!
College of Engineering, Pune 27