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Twitter/GitHub: @shtaxxx
IPSJ-ONE 2017
Twitter/GitHub: @shtaxxx
IPSJ-ONE 2017
J
IntelIntel Core i7
#include <stdio.h>int main(){printf("Hello!¥n");return 0;
}
FPGA
[1] Agile Co-Design for a Reconfigurable Datacenter, FPGA'16
Digilent PYNQ-Z1Python$229 (Academic $65)
ScalableCore System(Xilinx Spartan-6 128)
CPU100
L
int main(){
return 0;} J
J
conv1_input_enable:1 delayR
conv1_input_act_0_0:8 *L
conv1_input_wgt_0_0:8
R
conv1_input_act_0_1:8
*
L
conv1_input_wgt_0_1:8 R
conv1_input_act_0_2:8
*L
conv1_input_wgt_0_2:8 R
conv1_input_act_1_0:8 *L
conv1_input_wgt_1_0:8
R
conv1_input_act_1_1:8
*L
conv1_input_wgt_1_1:8 R
conv1_input_act_1_2:8
*L
conv1_input_wgt_1_2:8 R
conv1_input_act_2_0:8
*
L
conv1_input_wgt_2_0:8 R
conv1_input_act_2_1:8
*
L
conv1_input_wgt_2_1:8 R
conv1_input_act_2_2:8
*L
conv1_input_wgt_2_2:8
R
delayR
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delayR
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delayR
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delayR
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delayR
+L
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+L
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+
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delayR
+L
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delay
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delayR
+L
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delayR
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delayR
delayR
Cond0
2
conv1_act_output_valid:1
conv1_act_output:80 R
0
1
IntelIntel Core i7
#include <stdio.h>int main(){printf("Hello!¥n");return 0;
}
FPGA