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TOWARD A METHODOLOGY TO TURN SMALLTALK CODE INTO FPGA LE Xuan Sang 1,2 Loïc LAGADEC 1 , Luc FABRESSE 2 , Jannik LAVAL 2 and Noury BOURAQADI 2 1 Lab-STICC, ENSTA Bretagne 2 Institut Mines-Telecom, Mines Douai

Toward a Methodology to turn Smalltak code into FPGA

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Toward a Methodology to turn Smalltak code into FPGA IWST 2014 at ESUG, Cambridge

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Page 1: Toward a Methodology to turn Smalltak code into FPGA

TOWARD A METHODOLOGY TO TURN SMALLTALK CODE INTO FPGA

LE Xuan Sang1,2 Loïc LAGADEC1, Luc FABRESSE2,

Jannik LAVAL2 and Noury BOURAQADI2

1 Lab-STICC, ENSTA Bretagne 2 Institut Mines-Telecom, Mines Douai

Page 2: Toward a Methodology to turn Smalltak code into FPGA

Robotic application requirements

2

Sensors Sensing Planification Control Actuators

• Robotics applications demand :

• Real-time + amount of data : Processing powerExample in vision : 20 images of 320x240/s ≃ 37Mbps.

• Flexibility to evolution and unforeseen change of hardware (adding more device/sensor/actuators, improvement of circuit etc.)

Page 3: Toward a Methodology to turn Smalltak code into FPGA

• Simplicity & rich semantic

• High-level abstraction

• Smalltalk is also an IDE:

• Support Agile methodology

• Valuable ability of debugging & testing application

• BUT : Time-consuming for mass data processing3

Smalltalk in Robotic Software Development

Page 4: Toward a Methodology to turn Smalltak code into FPGA

• Configurable hardware/chip

• Parallel processing

• FPGA circuits are designed using Hardware Description Language (HDLs).

• BUT: HDL-based design is unsuitable for hardware/software co-design

4

Field Programmable Gate Array (FPGA)

Page 5: Toward a Methodology to turn Smalltak code into FPGA

5

1. Hardware Design (HDL)

2. Write tech-bench and perform Register Transfer Level simulation (RTL)

3. Synthesis and code generation

4. Deployment on FPGA

FPGA HDL-BASED DESIGN

HW Design

Synthesis and

code generation

Deployment on FPGA

Test bench

RTL simulation

Vendor toolchain

dependent

Page 6: Toward a Methodology to turn Smalltak code into FPGA

• HDLs support specification up to Register Transfer Level (RTL). But :

• Lack abstractions to implement high-level algorithms

• Debugging is really hard (waveforms)

• Not adequate for high-level modelling/programming

• Hardware dependency → limit reusability

6

FPGA HDL-BASED DESIGN

Page 7: Toward a Methodology to turn Smalltak code into FPGA

OBJECTIVE

Using Smalltalk in hardware/software co-design

• Hardware : Smalltalk as a high-level description and verification language

!• Software : Smalltalk robotic

application that interact with FPGA

7

Smalltalk application

HW/SW Partitioning

SW HW

Pharo VM FPGA

Interface

Page 8: Toward a Methodology to turn Smalltak code into FPGA

8

• Smalltalk-based design

• Hardware design abstraction layer

• RTL simulation

• Waveform tracing

• Unit Test

• Smalltalk-VHDL conversion

• Reusability & extensibility

• Vendor’s tool interaction

SMALLTALK FOR HARDWARE DESIGN

Pharo VM

Smalltalk code

Hardware design abstraction layer

Smalltalk to VHDL RTL Simulation

FPGAVendor’s tools chain

Page 9: Toward a Methodology to turn Smalltak code into FPGA

SMALLTALK FOR SOFTWARE PROGRAMMING ON FPGA (1)

• Standalone FPGA

• Operate independently with the host system

• Communicate with the host system via interfaces of communication : USB, RS232, etc.

• Smalltalk application talk to FPGA via Foreign Function Interfaces (such as Native Boost)

• Problem : bandwidth bottleneck

9

Host System

Pharo VM

FPGA

FFI/ Language Binding

Interface (USB,

UART, etc.)

Page 10: Toward a Methodology to turn Smalltak code into FPGA

SMALLTALK FOR SOFTWARE PROGRAMMING ON FPGA (2)

• FPGA-ARM SoC/SoM

• FPGA System on Chip/Module : all in one system

• Accelerate FPGA - ARM communication →reduced bottleneck.

• Direct access to FPGA registers via system library

• Smalltalk application talk to FPGA registers via Register interaction abstraction layer which uses FFI

10

Linux Embedded System

Pharo

Smalltalk application

Register interaction abstraction layer

FPGA

Drivers / Extension Processing Platform Architecture

FFI/ Language Binding

ARM

Page 11: Toward a Methodology to turn Smalltak code into FPGA

EXPERIMENT•Build a Pharo robotic application

•Identify critical parts •Project the critical parts on FPGA

•Evaluation of performance gain/loss

11

Page 12: Toward a Methodology to turn Smalltak code into FPGA

VIDEOhttp://car.mines-douai.fr/2014/04/pharos-based-tracker-robot/

12

Page 13: Toward a Methodology to turn Smalltak code into FPGA

13

Camera RGB →HSV

HSV filtrer

Laser sensor

Object detector Motors

EXPERIMENT

Sensor Smalltalk application Actuators

Page 14: Toward a Methodology to turn Smalltak code into FPGA

14

Camera RGB →HSV

HSV filtrer

Laser sensor

Object detector

EXPERIMENT

Critical part !

Sensor Smalltalk application Actuators

Motors

Page 15: Toward a Methodology to turn Smalltak code into FPGA

15

RGB →HSV HSV filtrer

PERFORMANCE COMPARISON

192x128, 32 bit

Pharo Smalltalk C(OpenCV) FPGA circuits

73 ms 1.5ms 2.5ms

Page 16: Toward a Methodology to turn Smalltak code into FPGA

16

RGB →HSV HSV filtrer

PERFORMANCE COMPARISON

192x128, 32 bit

Pharo Smalltalk C(OpenCV) FPGA circuits

73 ms 1.5ms 2.5ms

! Bottleneck problem

Page 17: Toward a Methodology to turn Smalltak code into FPGA

CONCLUSION

• Future works :

• Modelling methodology of hardware design using Smalltalk.

• Pharo and FPGA interaction.

• Software/hardware co-design integration.

17

Smalltalk application

HW/SW Partitioning

SW HW

Pharo VM FPGA

Interface

Page 18: Toward a Methodology to turn Smalltak code into FPGA

TOWARD A METHODOLOGY TO TURN SMALLTALK CODE INTO FPGA

1 Lab-STICC, ENSTA Bretagne 2 Institut Mines-Telecom, Mines Douai

LE Xuan Sang1,2 Loïc LAGADEC1, Luc FABRESSE2,

Jannik LAVAL2 and Noury BOURAQADI2


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