Lect5stickdiagramlayoutrules 1226994677707873-9

02/19/15 1

VLSI Design and Layout PracticeVLSI Design and Layout PracticeLect5 – Stick Diagram & Scalable Lect5 – Stick Diagram & Scalable

Design RulesDesign Rules

Danny Wen-Yaw ChungDanny Wen-Yaw ChungInstitute of Electronic EngineeringInstitute of Electronic EngineeringChung-Yuan Christian UniversityChung-Yuan Christian University

Sept. 2008Sept. 2008

02/19/15 2 Wen-Yaw Chung/Chung-Yuan University VLSI Design

IC Layout Concept and Examples

I. Stick Diagram II. Design Rules III. Layout Verif ication

Ref: http://140.135.9.56/XMS/

http://140.135.9.56/XMS/




A. Basic Concept 1. Based on the view point of IC layout, the stick

diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks.

Legend:

contactmetal 2

metal 1

poly

ndiff

pdiff

VDD

in

VSS

out

■


A. Basic Concept 2. Although the st ick diagram is an abstract

presentation of real layout, it can use graphical symbols or legend to al locate the circuit to 2-diomensional plane and reach the aim same as the physical layout does.

3. The stick diagram is similar to a backbone of the real layout but without the real size and aspect rat io of the devices , it st i l l can reflect the real condit ion to layout of the si l icon chip.


B. Notations of the stick diagram


Stick Diagram Intermediate representation

between the transistor level and the mask (layout) level.

Gives topological information ( identif ies different layers and their relationship)

Assumes that wires have no width. It is possible

to translate stick diagram automatically to layout with correct design rules.

[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫

EDA 聯盟 – 推廣課程 Chap.1


Stick Diagram

1. When the same material (on the same layer) touch or cross, they are connected and belong to the same electrical node.

2. When polysil icon crosses N or P diffusion, an N or P transistor is formed.

Polysilicon is drawn on top of diffusion. Diffusion must be drawn connecting the source and the drain. Gate is automatically self-aligned during fabrication.




Stick Diagram

3. When a metal line needs to be connected to one of the other three conductors, a contact cut (via) is required.




Stick Diagram 4. Manhattan geometrical rule: When we use only vertical

and horizontal l ines In orthogonal to describe circuitry. Boston geometrical rule: The stick diagram also al lows

curves to describe circuitry. 5. In order to describe N/PMOS more completely, to

add n-well 、 P+ select 、 well contact and substrate

contact are optional for 4-terminal notation.


Conclusion 1. Stick diagram is a draft of real layout, it serves

as an abstract view between the schematic and layout.

2. Stick diagram uses different lines, colors and geometrical shapes to present circuit nodes, devices, and their relative location.

3. Stick diagram doesn’t include information about the accurate coordinates and sizes of device, the length and width of conductors and the real size of well region.


CMOS Inverter Stick Diagrams

Basic layout

․ More area efficient layout




CMOS inverter described in other way.

VDD

in

VSS

out

CMOS Inverter Stick Diagrams


CMOS Transmission Gate The transmission gate Circuit schematic Stick diagram


CMOS Stick Diagrams NAND/NOR




CMOS Stick Diagrams NAND


< Exercise 1 >To draw the following circuitry by using a stick diagram


< Exercise 2 > To draw the st ick diagram and the schematic for the fol lowing layout

NWELL

NSELECT

PSELECT

POLY

ACTIVE

METAL1

NWELL

NSELECT

PSELECT

POLY

ACTIVE

METAL1


CMOS Stick Diagrams[Ref]: 教育部顧問室

「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1

NOR


CMOS Inverter Mask Layout

Min. spacing andline width consideration


Lambda-based Design Rules

Lambda design rules are based on a reference metric λthat has units of um.

All widths, spacing and distances are written in the form Value = m λ

Where m is scaling multiplier.<e.g.> λ= 1um w = 2 λ=2um s = 3λ=3um


Lambda based design: half of technology since 1985. As technologychanges with smaller dimensions, a simple change in the value of λ canbe used to produce a new mask set.

All device mask dimensions are based on multiples of λ, e.g., polysilicon minimum width = 2λ. Minimum metal to metal spacing = 3λ

6λ

2λ

6λ

λ

3λ

3λ

Lambda-based Design Rules


Active Contact and Surround Rule


Potential Problem - Misalignment


Potential Problem – Short between Source and Drain


Degree of anisotropy A = 1 – rlat/rvert

Where r respective etch rates

Physical Limitations


Design Rule (0)

Due to the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment.

In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule 。


The purpose of design rules Ref. Jan M. Rabaey, et. al, © Digital

Integrated Circuits 2nd Edition Interface between designer and process

engineer Guidelines for constructing process masks Unit dimension: Minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)


Design Rules(1)

Layout rules are used for preparing the masks for fabrication.

Fabrication processes have inherent l imitations in accuracy.

Design rules specify geometry of masks to optimize yield and reliabi l i ty (trade-offs: area, yield, reliabi l i ty).

Three major rules: Wire width: Minimum dimension associated with a

given feature. Wire separation: Allowable separation. Contact: overlap rules.




Design Rules(2) Two major approaches:

“Micron” rules: stated at micron resolut ion. λ rules: simplif ied micron rules with

l imited scaling attr ibutes. λ may be viewed as the size of minimum

feature. Design rules represents a tolerance which

insures very high probabil i ty of correct fabrication (not a hard boundary between correct and incorrect fabrication).

Design rules are determined by experience.




Terminology & Definit ion Min. Width : The min. width of the l ine

( layer) <Example> Wpoly(min.) = 0.5um

Min. Space : The min. spacing between l ines with same material

<Example> Spoly-poly(min.) = 0.5um


<Min. Extension : The min. extension over different layers

<Example> Poly-gate extension over diffusion area = 0.55um

Min. Overlap : The overlap between different layers <Example> Poly1 overlap Poly2 min. = 0.7um

Terminology & Definit ion


Terminology & Definit ion

Max. area of the specif ic region. <Example> Bonding Pad Area, max. = 100um x

100um


Conventional Layer Definition

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green

Layer

Polysilicon

Metal1

Metal2

Contact To Poly


Via

Well (p,n)

Active Area (n+,p+)


Yellow

Green

Red

Blue

Magenta

Black

Black

Black


Layer

Polysilicon

Metal1

Metal2

Contact To Poly


Via

Well (p,n)

Active Area (n+,p+)


Yellow

Green

Red

Blue

Magenta

Black

Black

Black



SCMOS Design Rules

IntraIntra--Layer Design RulesLayer Design Rules

Metal24

3

Ref. Jan M. Rabaey, et. al, © Digital Integrated Circuits 2nd Edit ion


SCMOS Design Rules

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


SCMOS Design Rules

1

3 3

2

2

2

WellSubstrate

Select3

5


SCMOS Design Rules




MOSIS Layout Design Rules MOSIS design rules (SCMOS rules) are available at

http://www.mosis.org. 3 basic design rules:

Wire width Wire separation Contact rule

MOSIS design rule examples




I I I. Layout Verif ication

A. Definit ion DRC – Design Rule Check ERC – Electrical Rule Check LVS – Layout Versus Schematic LPE – Layout Parameter

Extraction


Layout Verif ication

B. DRC(Design Rule Check) ： => To check the min. l ine width and

spacing based on the design rules.

C. ERC(Electrical Rule Check) ： => To check the short circuit

between Power and Ground, or check the floating node or devices.



D. LVS(Layout versus Schematic) ： => To verify the consistency between Schematic

and Layout. For example ： to check the amount of transistor numbers, sizes of W/L.

E. LPE or PEX(Layout Parameter Extraction) ：

=> From the database of layout, to extract the devices with parasit ics including effective W/L, parasit ic capacitances and series resistance. The extracted fi le is in SPICE format and can be used for Post-Layout Simulation 。


Layout Verif icationF. SimulationsPre-Layout Simulation - before layout workPost-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.



The complete design environment of Fil l-Custom Design Design database – Cadence Design Framework IICircuit Editor – Text editor/Schematic editor (S-edit , Composer)Circuit Simulator – SPICE,TSPICE, HSPICELayout Editor – Cadence Virtuoso, Laker, L-editLayout Verif ication Diva, Dracula, Calibre, Hercules


Concluding Remarks Milestones technology in si l icon era

Transistor Integrated Circuits CMOS Technology

Key weapons in SOC era Design Automation Design Reuse

Breakthrough techniques in design automation Simulation (e.g., SPICE, Verilog-XL, etc.) Automatic Placement and Routing (APR) Logic Synthesis (e.g., Design Compiler) Formal Verif ication Test Pattern Generation

It is EDA that pushes the IC design technology forward !




[Ref.] John P. Uyemura, “Physical Design of CMOS Integrated Circuits Using L-EDIT”, PWS Publishing Company, 1995.

SCNA Layout Rules


SCNA Layout Rules


SCNA Layout Rules


SCNA Layout Rules


SCNA Layout Rules


SCNA Layout Rules


LAB. 3

Set#1 – Stick Diagram Practice Set#2 – Reverse Engineering

Self Improvement

Lect5stickdiagramlayoutrules 1226994677707873-9