VTU ECE 7th sem VLSI lab manual

VLSI LAB MANUAL

Bearys Institute of Technology, Dept. of ECE, Mangaluru Page 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

BEARYS INSTITUTE OF TECHNOLOGY

Innoli, Boliyar Village, Mangalore

VLSI Lab manual

(10ECL77)

Prepared by:

MR. SUSHANTH K.J

ASST. PROF, BIT, MANGALORE

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P.A. COLLEGE OF ENGINEERING

(Affiliated to VTU, Recognized by AICTE, NBA Accredited)

Near Mangalore University, Mangalore – 574 153, Karnataka

LABORATORY CERTIFICATE

This is to certify that …………………………………………… has

satisfactorily completed the course of experiments in CAD for VLSI

Laboratory practical prescribed by the Visveswaraiah Technological

University for 7th

sem. of Electronics and Communication branch of

Engineering in this College.

Register No: Signature of the Staff-in-charge

Signature of the H.O.D.

Marks awarded in words

BEARYS INSTITUTE OF TECHNOLOGY

Innoli, Boliyar Village

Mangalore - 574153

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Part A

Sl.no. Programs Page No.

Remarks

1 Timing verification with gate level simulation of an Inverter (Sample program)

2 Timing verification with gate level simulation of a Buffer

3 Timing verification with gate level simulation of Transmission Gate

4(a) 4(b) 4(c) 4(d) 4(e) 4(f)

Timing verification with gate level simulation of AND gate

Timing verification with gate level simulation of OR gate

Timing verification with gate level simulation of XOR gate

Timing verification with gate level simulation of XNOR gate

Timing verification with gate level simulation of NAND gate

Timing verification with gate level simulation of NOR gate

5(a) 5(b) 5(c) 5(d) 5(e)

Timing verification with gate level simulation of SR flip-flop

Timing verification with gate level simulation of D flip-flop

Timing verification with gate level simulation of JK flip-flop

Timing verification with gate level simulation of MS flip-flop

Timing verification with gate level simulation of T flip-flop

6 Timing verification with gate level simulation of Parallel Adder

7(a) 7(b)

Timing verification with gate level simulation of Synchronous Counter

Timing verification with gate level simulation of an Asynchronous Counter

8

Timing verification with gate level simulation of Successive Approximation Register (SAR)

Part B

Sl.No. Programs PageNo. Remarks

1. Design of an inverter using analog design flow

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2. Design of an Differential Amplifier using analog design flow

3. Design of an Common Source Amplifier using analog design flow

4. Design of an Common Drain Amplifier using analog design flow

5. Design of an Operational Amplifier using analog design flow

VLSI Viva Questions and Answers

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PART-A DIGITAL DESIGN BASIC-DIGITAL

DESIGN FLOW

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VLSI LAB MANUAL


VLSI LAB MANUAL


Procedure:

1)Simulation

pwd- To check the present working directory.

ls- to list the contents of the directory

cd cadence_DB - to change the directory

csh- invoke C shell script

source cshrc – to link cadence with c shell

“Welcome to cadence_tools”

mkdir (dirname)- to make a directory

cd dirname

vi (filename.v)– to invoke the vi editor

Press I to go into INSERT mode

Type the program

Esc :wq to save and exit

nclaunch

launch verilog compiler with current selection

elaborate ( top level module)

launch simulator with current selection

send to waveform

run simulation

2) Synthesis

Copy the library to the current directory

rc

set_attribute library dirname/library/slow or fast.lib

read_hdl dirname/filename.v

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elaborate

gui_show

synthesize –to_mapped –effort medium

report timing

report gates

report gates –power

report area

report summary

write_hdl > net_name.v

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Experiment No. 1. An inverter

Sample Program (INVERTER)

Boot the system to Red Hat Linux

Right click on the Desktop

Click on open terminal tab

To check whether the system is connected to server, the command used is

[root@llocal host ~]ping 192.168.80.1 { press Enter }

Press ctrl+c to stop pinging

To mount into the system:

mount –t nfs 192.168.80.1:/home/cadence /mnt/cadence {press Enter}

To initialize your client , the command is:

/etc/init.d/nfs restart {press Enter}

[root@local host ~]# will be displayed on the screen

Type [root@local host ~] csh to go to C shell

Then the # will be replaced with a $ symbol

[root@local host ~]$

Type [root@local host ~] $ source cshrc

If the above steps are done correctly a message will be displayed saying:

Welcome to Cadence tool suite

To make a directory type mkdir ourlabs

To go to the created directory type cd ourlabs

[root@local host ourlabs]$

To see files within the directory type [root@local host ourlabs]$ ls {Press Enter}

NOTE (1): To move from the present directory to previous directory type cd .. {Press Enter}

NOTE (2): To move from the present directory to the root directory type cd<SPACE> {Press

Enter}

To create a directory for the inverter program type:

[root@local host ourlabs]$ mkdir invertr {Press Enter}

To open the created directory :

[root@local host ourlabs]$ cd invertr {Press Enter}

The above the path will change to:- [root@local host invertr]$

If we need to check the path type:

[root@local host invertr]$ pwd {Press Enter}

Steps to create a file in verilog:

[root@local host invertr]$ vi invertr.v

The above command will open a window where the module program can be written

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VLSI LAB MANUAL


The writing of the program can be done after activating the insert mode by pressing I in the

program window

Module Program

module inv(a,y);

input a;

output y;

assign y=~a;

endmodule

To save and quit the module program press ESC and type :wq

To quit without saving press ESC and type :q!

Test bench file is used for simulation

To create a test bench file type

[root@local host invertr]$ vi invertr_test.v

The above command will open a window where the testbench program can be written

The writing of the program can be done after activating the insert mode by Pressing I in the

program window

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VLSI LAB MANUAL


Testbench Program

module inv_test;

reg a;

wire y;

inv abc(a,y);

initial

begin

$monitor($time,"y=%d",y);

a=1'b0;

#10 a=1'b1;

#10 a=1'b0;

#10 $finish;

end

endmodule

To save and quit the module program press ESC and type :wq

To quit without saving press ESC and type :q!

Compilation of the module and the testbench program can be

done using the commands

ncvlog invertr.v –mess {Press Enter}

ncvlog invertr_test.v –mess {Press Enter}

To elaborate the program to the libraries

ncelab inv_test –mess {Press Enter}

Simulation can be done by

ncsim inv_test {Press Enter}

To launch the simulation window the command is

nclaunch {Press Enter}

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VLSI LAB MANUAL


Simulation window :

In the simulation window set the directory as root

Delete files from worklib

Select invertr on the lower right side of the window

Click on invertr.v and click vlog icon on the nclaunch window

Click on invertr_test.v and click vlog icon on the nclaunch window

Then within the worklib we can see two files

Invertr

Invertr_test

Click on inv and select the launch icon on top of the nclaunch window

Click on inv_test and select the launch icon on top of the nclaunch window

Then click on the snapshots folder which will contain the below two files

Worklib.invertr.module

Worklib.invertr_test.module

Click on worklib.invertr_test.module and select the Launch Simulator with current selection

icon on the nclaunch window

After simulation go back to the directory invertr

The path should be as shown below

[root@local host invertr]$

Open root’s home in the desktop and open the Cadence_digital_labs folder

Copy the directory rclabs present in the Workarea folder

Go to your directory in root’s home i.e. invertr in this case

Paste the rclabs in your directory

Go back to the rtl directory in Cadence_digital_labs and move it to trash

Copy the module program to the rtl folder in your directory.

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VLSI LAB MANUAL


When the copying is done correctly check whether the file is present in the rtl directory by

following the below given steps

Enter the rclabs directory

cd rclabs

Enter the rtl directory

cd rtl

List the files within the directory and check whether the files have been copied properly, if not

repeat the copying procedure again

ls

Return back to the rclabs directory using the below given command

cd ..

Go to the work directory by

cd work

Create a log file for the inverter file using the command:

rc –gui –logfile invertr.log

When the inverter log file is executed a new screen will open displaying rc:\> on the screen

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The below given command is used to generate the template script from the compiler by

entering:

rc:\>write_template –outfile template.tcl

rc:\>set_attr hdl_search_path {../rtl} /

rc:\>set_attr lib_search_path {../library} /

rc:\>set_attr script_search_path {../tcl} /

rc:\>include setup.g

The reading of the libraries can be done by:

rc:\>set_att library $LIBRARY

Reading and elaborating is done by the commands:

rc:\>read_hdl invertr.v

rc:\>elaborate

Maximize the Cadence window and observe the circuit diagram

For Synthesis

Synthesize –to_mapped –eff medium –no_incr

Synthesis succeeded

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VLSI LAB MANUAL


Program No.2 : A Buffer Module Program ‘timescale 1ns/ 1ns module buff(a,y); input a; output y; reg y,c; always@ (a) begin c=~a; y=~c; end endmodule Testbench program ‘timescale 1ns/ 1ns module buf_test; reg a; wire y; buff al(a,y); initial begin $monitor($time,”y=%d”,y); a=1’b0; #10 a=1’b1; #10 a=1’b0; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No.3 : Transmission gate Module Program module transgate(s,x,y); input x,s; output y; reg y; always@(x or s) begin if(x==0 && s==1) y=1’b0; if (x==1 && s==1) y=1’b1; else y=1’bz; end endmodule Testbench program module transgate_test; reg x,s; wire y; transgate al(s,x,y); initial begin $monitor($time,”y=%d”,y); x=1’b0; s=1’b0; #10 x=1’b1; s=1’b0; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 4(a) : AND gate Module Program ‘timescale 1ns/ 1ns module andgate(a,b,c); input a,b; output c; assign c=a&b; endmodule Testbench program ‘timescale 1ns/ 1ns module andgate_test; reg a,b; wire c; andgate abc(a,b,c); initial begin $monitor($time,"c=%d",c); a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 4(b) : OR gate Module Program ‘timescale 1ns/ 1ns module or1(a,b,c); input a,b; output c; assign c=a|b; endmodule Testbench program ‘timescale 1ns/ 1ns module or1_test; reg a,b; wire c; or1 abc(a,b,c); initial begin $monitor ($time,"c=%d",c); a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 4(c) : An XOR gate Module Program ‘timescale 1ns/ 1ns module exor(a,b,c); input a,b; output c; assign c=(a^b); endmodule Testbench Program ‘timescale 1ns/ 1ns module exor_test; reg a,b; wire c; exor abc(a,b,c); initial begin $monitor($time,"c=%d",c); a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 4(d) :An XNOR gate Module Program ‘timescale 1ns/ 1ns module xnor1(a,b,c); input a,b; output c; assign c=~(a^b); endmodule Testbench Program ‘timescale 1ns/ 1ns module xnor1_test; reg a,b; wire c; xnor1 g1(a,b,c); initial begin $monitor($time,"c=%d",c); a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 4(e): A NAND gate Module Program module nand1(a,b,c); input a,b; output c; assign c=~(a&b); endmodule Testbench Program module nand1_test; reg a,b; wire c; nand1 g1(a,b,c); initial begin $monitor($time,"c=%d",c); a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; #10 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 4(e): A NOR gate Module Program module nor1(a,b,c); input a,b; output c; assign c=~(a|b); endmodule Testbench program module nor1_test; reg a,b; wire c; nor1 abc(a,b,c); initial begin $monitor ($time,"c=%d",c); a=1'b0; b=1'b0; #10 a=1'b0; b=1'b1; #10 a=1'b1; b=1'b0; #10 a=1'b1; b=1'b1; #10 $finish; end endmodule

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Program no. 5(a): SR flip flop

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Program no 5(a) : S R Flip Flop Module program module srff2(s,r,clk,q,qb); input s,r,clk; inout q,qb; wire d,e; nand1 g0(s,clk,d); nand1 g1(r,clk,e); nand1 g2(d,qb,q); nand1 g3(e,q,qb); endmodule module nand1(a,b,y); input a,b; output y; assign y=~(a&b); endmodule Testbench Program module srff2_test; reg s,r,clk; wire q,qb; srff2 abc(s,r,clk,q,qb); initial clk=1’b0; always #10 clk= ~clk; Initial begin $monitor($time, “q=%d”,”qb=%d”,q, qb); #20 s=1’b0; r=1’b0; #20 s=1’b0; r=1’b1; #20 s=1’b1; r=1’b0; #20 s=1’b1; r=1’b1; #20 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 5(b): A D Flip Flop Module Program module dff1(d,q,qb,clk); input d,clk; output q,qb; reg q,qb; initial begin q=0; end always@(posedge clk) begin if(d==0) q=0; else q=1; qb=~q; end endmodule Testbench Program module dff1_test; reg d,clk; wire q,qb; dff1 al(d,q,qb,clk); initial clk=1'b0; always #10 clk=~clk; initial begin $monitor($time,"q=%d","qb=%d",q,qb); d=1'b0; #30 d=1'b1; #30 d=1'b0; #30 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 5(c): A JK Flip Flop Module Program module jkff1(jk,clk,q,qb); input [1:0]jk; input clk; output q,qb; reg q,qb; initial begin q=0; qb=1; end always@(posedge clk) begin case(jk) 2'b00:q=q; 2'b01:q=0; 2'b10:q=1; 2'b11:q=~q; endcase qb=~q; end endmodule Testbench Program module jkff1_test; reg clk; reg [1:0]jk; wire q,qb; jkff1 abc(jk,clk,q,qb); initial clk=1'b0; always #10 clk=~clk; initial begin $monitor($time,"q=%d","qb=%d",q,qb); jk=2'b00; #30 jk=2'b01; #30 jk=2'b10; #30 jk=2'b11; #30 $finish; end endmodule

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VLSI LAB MANUAL


Program No. 5(d): A MS Flip Flop Module Program module msff(j,k,clk,q,qb); input j,k,clk; output q,qb; reg q,qb,tq; initial begin q=1'b0; qb=1'b1; end always @(clk) begin if(clk) begin if(j==1'b0 && k==1'b0) tq=tq; else if(j==1'b0 && k==1'b1) tq=1'b0; else if(j==1'b1 && k==1'b0) tq=1'b1; else if(j==1'b1 && k==1'b1) tq=~tq; end if(!clk) begin q=tq; qb=~tq; end end endmodule Testbench Program module msff_test; reg j,k,clk; wire q,qb,tq; msff abc(j,k,clk,q,qb); initial clk=1'b0; always #10 clk=!clk; initial begin $monitor($time,"q=%d","qb=%d",q,qb); j=1'b0; k=1'b0; #30 j=1'b0; k=1'b1; #30 j=1'b1; k=1'b0; #30 j=1'b1; k=1'b1; #30 $finish; end endmodule

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VLSI LAB MANUAL


Program no. 5(e): T flip flop Module program module tff(tin,rst,clk,q,qbar); input tin,rst,clk; output q,qbar; reg tq; always@(posedge clk or negedge rst) begin if(!rst) tq=0; else begin if(tin) tq=~tq; end end assign q=tq; assign qbar=~q; endmodule Testbench Program module tff_test; initial reg tin,rst,clk; #2000 $finish; wire q,qbar; endmodule tff t1(tin,rst,clk,q,qbar); initial clk=1’b0; always #10 clk= ~clk; initial begin rst=1’b0; tin=1’b0; #30 rst=1’b1; #10 tin=1’b1; #205 tin=1’b0; #300 tin=1’b1; #175 tin=1’b0; #280 rst=1’b0; #20 rst=1’b1; #280 tin=1’b1; end

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VLSI LAB MANUAL


Program No. 6: A Parallel Adder Module Program module par(cin,x,y,sum,cout); input cin; input [3:0]x,y; output [3:0]sum; output cout; fulladd g0(cin,x[0],y[0],sum[0],c0); fulladd g1(c0,x[1],y[1],sum[1],c1); fulladd g2(c1,x[2],y[2],sum[2],c2); fulladd g3(c2, x[3],y[3],sum[3],cout); endmodule module fulladd(cin,x,y,sum,cout); input cin,x,y; output sum,cout; assign sum=x^y^cin; assign cout=((x&y)||(x&cin)||(y&cin)); endmodule Testbench Program module par_test; reg [3:0] x,y; reg cin; wire [3:0] sum; wire cout; par al (cin,x,y,sum,cout); initial begin $monitor($time, "sum=%d",sum); x=4'b0000; y=4'b0000; cin=1'b0; #20 x=4'b1111; y=4'b1010; #40 x=4'b1011; y=4'b0110; #40 x=4'b1111; y=4'b1111; #50 $finish; end endmodule

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VLSI LAB MANUAL


Program no. 7(a): Synchronous counter Module program module syncount(cnt,e,q); module and1(a,b,c); input cnt,e; input a,b; output [3:0]q; output c; wire e1,e2,e3; assign c=a&b; tff aaa(e,cnt,q[0]); endmodule and1 g0(q[0],e,e1); tff bbb(e1,cnt,q[1]); module and2(d,e,f,g); and2 g1(q[0],q[1],e,e2); input d,e,f; tff ccc(e2,cnt,q[2]); output g; and3 g2(q[0],q[1],q[2],e,e3); assign g=d&e&f; endmodule endmodule module tff(t,clk,q); module and3(p,q,r,s,t); input t,clk; input p,q,r,s; output q; output t; reg q; assign t=p&q&r&s; initial endmodule q=1’b0; reg tq; always@(posedge clk) begin if(t==0) q=q; else q=~q; end endmodule Testbench Program module syncount_test; reg cnt,e; wire [3:0]q; syncount zzz(cnt,e,q); initial begin cnt=0; e=1; end always #100 cnt=~cnt; endmodule

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VLSI LAB MANUAL


Program no. 7(b): An Asynchronous counter Module program module acount(cnt,e,q); input cnt,e; output [3:0]q; wire q1,q2,q3,q4; tff aaa(e,cnt,q[0],q1); tff bbb(e,q1,q[1],q2); tff ccc(e,q2,q[2],q3); tff ddd(e,q3,q[3],q4); endmodule module tff(t,clk,q,qb); input t,clk; output q,qb; reg q,qb; initial begin q=1’b0; qb=1’b1; end always@(posedge clk) begin if(t==0) q=q; else q=~q; qb=~q; end endmodule Testbench Program module syncount_test; reg cnt,e; wire [3:0]q; syncount zzz(cnt,e,q); initial begin cnt=0; e=1; end always #100 cnt=~cnt; endmodule

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VLSI LAB MANUAL


Program no. 8: Successive Approximation Register [SAR] Module program module sar(R,L,E,W,clk,q); parameter n=8; input[n-1:0] r input L,E,W,clk; output [n-1:0] q reg [n-1:0] q; integer k; always@(posedge(clk)) begin if(L) q=R; else if(R) begin for(k=n-1;k>0;k=k-1) q[k-1]<=q[k]; q[n-1]<=W; end end endmodule Testbench Program module syncount_test; reg [7:0]r; reg l,e,w,clk; wire [7:0]q; sar bbb( R(r),L(l),E(e),W(w),clk(clk),q(q)); initial begin l=1’b1; e=1’b0; r=8’b11110000; clk=1’b0; #10 w=1’b1; l=1’b0; e=1’b1; #10 w=1’b0; end always #5 clk=~clk; endmodule

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PART-B ANALOG DESIGN FLOW

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Lab Getting Started

1. Log in to your workstation using the username and password.

The home directory has a cshrc file with paths to the Cadence installation.

2. In a terminal window, type csh at the command prompt to invoke the C shell.

>csh

>source cshrc

Starting the Cadence Software

Use the installed database to do your work and the steps are as follows:

1. Change to the course directory by entering this command:

> cd ~/cadence_DB/cadence_ms_labs_614

2. In the same terminal window, enter:

> virtuoso

The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the screen.

3. If the “What’s New ...” window appears, close it with the File— Close command.

4. Keep opened CIW window for the labs.

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Lab 1: AN INVERTER

Schematic Capture

Objective: To create a library and build a schematic of an Inverter

Execute Tools – Library Manager in the CIW or Virtuoso window to open Library Manager.

Creating a New library

1. In the Library Manager, execute File - New – Library. The new library form appears.

2. In the “New Library” form, type “myDesignLib (arbitrary name)” in the Name section.

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4. In the field of Directory section, verify that the path to the library is set

to ~/cadence_DB/cadence_ms_lab_614 and click OK.

5. In the next “Technology File for New library” form, select option Attach to an existing

techfile and click OK.

6. In the “Attach Design Library to Technology File” form, select gpdk180 from the cyclic

field and click OK.

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7. After creating a new library you can verify it from the library manager.

8. If you right click on the “myDesignLib” and select properties, you will find that gpdk180

library is attached as techlib to “myDesignLib”.

Creating a Schematic Cellview

In this section we will learn how to open new schematic window in the new “myDesignLib”

library and build the inverter schematic as shown in the figure at the start of this lab.

1. In the CIW or Library manager, execute File – New – Cellview.

2. Set up the New file form as follows:

Do not edit the Library path file and the one above might be different from the path shown in

your form.

3. Click OK when done the above settings. A blank schematic window for the Inverter design

appears.

Adding Components to schematic

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1. In the Inverter schematic window, click the Instance fixed menu

icon to display the Add Instance form.

Tip: You can also execute Create — Instance or press i.

2. Click on the Browse button. This opens up a Library browser from which you

can select components and the symbol view .

You will update the Library Name, Cell Name, and the property values

given in the table on the next page as you place each component.

3. After you complete the Add Instance form, move your cursor to the

schematic window and click left to place a component.

This is a table of components for building the Inverter schematic.

If you

place a

component with the wrong parameter values, use the

Edit— Properties— Objects command to change the parameters.

Use the Edit— Move command if you place components in the

wrong location.

You can rotate components at the time you place them, or use the

Edit— Rotate command after they are placed.

Library name Cell Name Properties/Comments

gpdk180 pmos For M0: Model name = pmos1, W= wp,

L=180n

gpdk180 nmos For M1: Model name = nmos1, W= 2u,

L=180n

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4. After entering components, click Cancel in the Add Instance form

or press Esc with your cursor in the schematic window.

Adding pins to Schematic

1. Click the Pin fixed menu icon in the schematic window.

You can also execute Create — Pin or press p.

The Add pin form appears.

2. Type the following in the Add pin form in the exact order leaving space

between the pin names

Pin Names Direction

vin Input

vout Output

Make sure that the direction field is set to input/output/inputOutput when placing

theinput/output/inout pins respectively and the Usage field is set to schematic.

3. Select Cancel from the Add – pin form after placing the pins.

In the schematic window, execute Window— Fit or press the f bindkey.

Adding Wires to a Schematic

Add wires to connect components and pins in the design.

1. Click the Wire (narrow) icon in the schematic window.

You can also press the w key, or execute Create — Wire (narrow).

2. In the schematic window, click on a pin of one of your components as the first

point for your wiring. A diamond shape appears over the starting point of this wire.

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3. Follow the prompts at the bottom of the design window and click left on the destination point

for your wire. A wire is routed between the source and destination points.

4. Complete the wiring as shown in figure and when done wiring press ESC key in the schematic

window to cancel wiring.

Saving the Design

1. Click the Check and Save icon in the schematic editor window.

2. Observe the CIW output area for any errors.

Symbol Creation

Objective: To create a symbol for the Inverter

1. In the Inverter schematic window, execute

Create — Cellview— From Cellview.

The Cellview From Cellview form appears. With the Edit Options

function active, you can control the appearance of the symbol to generate.

2. Verify that the From View Name field is set to schematic, and the

To View Name field is set to symbol, with the Tool/Data Type set as SchematicSymboL

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3. Click OK in the Cellview From Cellview form.

The Symbol Generation Form appears.

4. Modify the Pin Specifications as follows:

5. Click OK in the Symbol Generation Options form.

6. A new window displays an automatically created Inverter symbol

as shown here

Editing a Symbol

In this section we will modify the inverter symbol to look like a Inverter gate symbol.

1. Move the cursor over the automatically generated symbol, until the green rectangle

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is highlighted, click left to select it.

2. Click Delete icon in the symbol window, similarly select the red rectangle and

Delete that.

3. Execute Create – Shape – polygon, and draw a shape similar to triangle.

4. After creating the triangle press ESC key.

5. Execute Create – Shape – Circle to make a circle at the end of triangle.

6. You can move the pin names according to the location.

7. Execute Create — Selection Box. In the Add Selection Box form, click Automatic.

A new red selection box is automatically added.

8. After creating symbol, click on the save icon in the symbol editor window to save the symbol.

In the symbol editor, execute File — Close to close the symbol view window.

Building the Inverter_Test Design

Objective: To build an Inverter Test circuit using your Inverter

Creating the Inverter_Test Cellview

1. In the CIW or Library Manager, execute File— New— Cellview.

2. Set up the New File form as follows:

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3. Click OK when done. A blank schematic window for the Inverter_Test design appears.

Building the Inverter_Test Circuit

1. Using the component list and Properties/Comments in this table,

build the Inverter_Test schematic.

Note: Remember to set the values for VDD and VSS. Otherwise, your circuit will have no

power.

2. Add the above components using Create — Instance or by pressing I.

3. Click the Wire (narrow) icon and wire your schematic.

Tip: You can also press the w key, or execute

Create— Wire (narrow).

4. Click Create — Wire Name or press L to name the input (Vin) and output (Vout) wires as

in the below schematic.

Library name Cellview name Properties/Comments

myDesignLib Inverter Symbol

analogLib vpulse v1=0, v2=1.8,td=0 tr=tf=1ns,

ton=10n, T=20n

analogLib vdc, gnd vdc=1.8

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4. Click on the Check and Save icon to save the design.

5. The schematic should look like this.

6. Leave your Inverter_Test schematic window open for the next section.

Analog Simulation with Spectre

Objective: To set up and run simulations on the Inverter_Test design

Starting the Simulation Environment

Start the Simulation Environment to run a simulation.

1. In the Inverter_Test schematic window, execute

Launch – ADE L

The Virtuoso Analog Design Environment (ADE) simulation window appears.

Choosing Analyses

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This section demonstrates how to view and select the different types of analyses to

complete the circuit when running the simulation.

1. In the Simulation window (ADE), click the Choose - Analyses icon.

You can also execute Analyses - Choose.

The Choosing Analysis form appears. This is a dynamic form, the bottom of the form

changes based on the selection above.

2. To setup for transient analysis

a. In the Analysis section select tran

b. Set the stop time as 200n

c. Click at the moderate or Enabled button at the bottom, and then click Apply.

3. To set up for DC Analyses:

a. In the Analyses section, select dc.

b. In the DC Analyses section, turn on Save DC Operating Point.

c. Turn on the Component Parameter.

d. Double click the Select Component, Which takes you to the schematic window.

e. Select input signal vpulse source in the test schematic window.

f. Select “DC Voltage” in the Select Component Parameter form and click OK.

f. In the analysis form type start and stop voltages as 0 to 1.8 respectively.

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g. Check the enable button and then click Apply.

4. Click OK in the Choosing Analyses Form.

Setting Design Variables

Set the values of any design variables in the circuit before simulating.

Otherwise, the simulation will not run.

1. In the Simulation window, click the Edit Variables icon.

The Editing Design Variables form appears.

2. Click Copy From at the bottom of the form.

The design is scanned and all variables found in the design are listed.

In a few moments, the wp variable appears in the Table of Design variables section.

3. Set the value of the wp variable:

With the wp variable highlighted in the Table of Design Variables,

click on the variable name wp and enter the following:

Value(Expr) 2u

Click Change and notice the update in the Table of Design Variables.

3. Click OK or Cancel in the Editing Design Variables window.

Selecting Outputs for Plotting

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1. Execute Outputs – To be plotted – Select on Schematic in the simulation window.

2. Follow the prompt at the bottom of the schematic window, Click on output net Vout, input net

Vin of the Inverter. Press ESC with the cursor in the schematic after selecting it.

Running the Simulation

1. Execute Simulation – Netlist and Run in the simulation window to start the

Simulation or the icon, this will create the netlist as well as run the simulation.

2. When simulation finishes, the Transient, DC plots automatically will be popped up along with

log file.

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Saving the Simulator State

We can save the simulator state, which stores information such as model library file,

outputs, analysis, variable etc. This information restores the simulation environment

without having to type in all of setting again.

1. In the Simulation window, execute Session – Save State.

The Saving State form appears.

2. Set the Save as field to state1_inv and make sure all options are selected under

what to save field.

3. Click OK in the saving state form. The Simulator state is saved.

Loading the Simulator State

1. From the ADE window execute Session – Load State.

2. In the Loading State window, set the State name to state1_inv as shown

3. Click OK in the Loading State window.

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Creating Layout View of Inverter

1. From the Inverter schematic window menu execute

Launch – Layout XL. A Startup Option form appears.

2. Select Create New option. This gives a New Cell View Form

3. Check the Cellname (Inverter), Viewname (layout).

4. Click OK from the New Cellview form.LSW and a blank layout window appear along with

schematic window.

Adding Components to Layout

1. Execute Connectivity – Generate – All from Source or click the icon in the layout

editor window, Generate Layout form appears. Click OK which imports the schematic

components in to the Layout window automatically.

2. Re arrange the components with in PR-Boundary as shown in the next page.

3. To rotate a component, Select the component and execute Edit –Properties. Now select the

degree of rotation from the property edit form.

4. To Move a component, Select the component and execute Edit -Move command.

Making interconnection

1. Execute Connectivity –Nets – Show/Hide selected Incomplete Nets or click the

icon in the Layout Menu.

2. Move the mouse pointer over the device and click LMB to get the connectivity information,

which shows the guide lines (or flight lines) for the inter connections of the components.

3. From the layout window execute Create – Shape – Path/ Create wire or Create – Shape –

Rectangle (for vdd and gnd bar) and select the appropriate Layers from the LSW window and

Vias for making the inter connections

Creating Contacts/Vias

You will use the contacts or vias to make connections between two different layers.

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1. Execute Create — Via or select command to place different Contacts, as given in

below table

Connection Contact Type

For Metal1- Poly

Connection

Metal1-Poly

For Metal1-

Psubstrate Connection

Metal1-Psub

For Metal1- Nwell

Connection

Metal1-Nwell

Saving the design

1. Save your design by selecting File — Save or click to save the layout, and layout

should appear as below.

Physical Verification Assura DRC

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1. Open the Inverter layout form the CIW or library manger if you have closed that.

Press shift – f in the layout window to display all the levels.

2. Select Assura - Run DRC from layout window.

The DRC form appears. The Library and Cellname are taken from the current

design window, but rule file may be missing. Select the Technology as gpdk180. This

automatically loads the rule file.

Your DRC form should appear like this

3. Click OK to start DRC.

4. A Progress form will appears. You can click on the watch log file to see the log

file.

5. When DRC finishes, a dialog box appears asking you if you want to view your

DRC results, and then click Yes to view the results of this run.

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6. If there any DRC error exists in the design View Layer Window (VLW) and Error

Layer Window (ELW) appears. Also the errors highlight in the design itself.

7. Click View – Summary in the ELW to find the details of errors.

8. You can refer to rule file also for more information, correct all the DRC errors and

Re – run the DRC.

9. If there are no errors in the layout then a dialog box appears with No DRC errors

found written in it, click on close to terminate the DRC run.

ASSURA LVS

Running LVS

1. Select Assura – Run LVS from the layout window.

The Assura Run LVS form appears. It will automatically load both the schematic and layout

view of the cell.

2. Change the following in the form and click OK.

3. The LVS begins and a Progress form appears.

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4. If the schematic and layout matches completely, you will get the form displaying Schematic

and Layout Match.

5. If the schematic and layout do not matches, a form informs that the LVS completed

successfully and asks if you want to see the results of this run.

6. Click Yes in the form.

LVS debug form appears, and you are directed into LVS debug environment.

7. In the LVS debug form you can find the details of mismatches and you need to

correct all those mismatches and Re – run the LVS till you will be able to match the

schematic with layout.

Assura RCX

Running RCX

1. From the layout window execute Assura – Run RCX.

2. Change the following in the Assura parasitic extraction form. Select output type under Setup

tab of the form.

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3. In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and specify the

Reference node for extraction.

4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter Ground Nets as

gnd

5. Click OK in the Assura parasitic extraction form when done.

The RCX progress form appears, in the progress form click Watch log file to see

the output log file.

5. When RCX completes, a dialog box appears, informs you that Assura RCX run

Completed successfully.

6. You can open the av_extracted view from the library manager and view the parasitic.

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Creating the Configuration View

In this section we will create a config view and with this config view we will run the

simulation with and without parasitic.

1. In the CIW or Library Manager, execute File – New – Cellview

2. In the Create New file form, set the following:

3. Click OK in create New File form.

The Hierarchy Editor form opens and a New Configuration form opens in front of it.

4. Click Use template at the bottom of the New Configuration form and select

Spectre in the cyclic field and click OK.

The Global Bindings lists are loaded from the template.

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5. Change the Top Cell View to schematic and remove the default entry from the

Library List field.

6. Click OK in the New Configuration form.

The hierarchy editor displays the hierarchy for this design using table format.

7. Click the Tree View tab. The design hierarchy changes to tree format. The form should look

like this:

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8. Save the current configuration.

9. Close the Hierarchy Editor window. Execute File – Close Window.

To run the Circuit without Parasites

1. From the Library Manager open Inverter_Test Config view.

Open Configuration or Top cellview form appears.

2. In the form, turn on the both cyclic buttons to Yes and click OK.

The Inverter_Test schematic and Inverter_Test config window appears. Notice the

window banner of schematic also states Config: myDesignLib Inverter_Test config.

3. Execute Launch – ADE L from the schematic window.

4. Now you need to follow the same procedure for running the simulation. Executing Session–

Load state, the Analog Design Environment window loads the previous state

5. Click Netlist and Run icon to start the simulation.

The simulation takes a few seconds and then waveform window appears.

6. In the CIW, note the netlisting statistics in the Circuit inventory section. This

list includes all nets, designed devices, source and loads. There are no

parasitic components. Also note down the circuit inventory section.

Measuring the Propagation Delay

1. In the waveform window execute Tools – Calculator.

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The calculator window appears

2. From the functions select delay, this will open the delay data panel.

3. Place the cursor in the text box for Signal1, select the wave button and select

the input waveform from the waveform window.

4. Repeat the same for Signal2, and select the output waveform.

5. Set the Threshold value 1 and Threshold value 2 to 0.9, this directs the

calculator to calculate delay at 50% i.e. at 0.9 volts.

6. Execute OK and observe the expression created in the calculator buffer.

7. Click on Evaluate the buffer icon to perform the calculation, note down the value

returned after execution.

8. Close the calculator window.

To run the Circuit with Parasites

In this exercise, we will change the configuration to direct simulation of the av_extracted view

which contains the parasites.

1. Open the same Hierarchy Editor form, which is already set for Inverter_Test config.

2. Select the Tree View icon: this will show the design hierarchy in the tree format.

3. Click right mouse on the Inverter schematic.

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A pull down menu appears. Select av_extracted view from the Set Instance view menu, the

View to use column now shows av_extracted view.

4. Click on the Recompute the hierarchy icon, the configuration is now updated from

schematic to av_extracted view.

6. From the Analog Design Environment window click Netlist and Run to

start the simulation again.

7. When simulation completes, note the Circuit inventory conditions, this time the list shows

all nets, designed devices, sources and parasitic devices as well.

8. Calculate the delay again and match with the previous one. Now you can conclude how much

delay is introduced by these parasites, now our main aim should to minimize the delay due to

these parasites so number of iteration takes place for making an optimize layout.

Generating Stream Data

Streaming Out the Design

1. Select File – Export – Stream from the CIW menu and Virtuoso Xstream out form appears

change the following in the form.

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2. Click on the Options button.

3. In the StreamOut-Options form select under Layers tab and click OK.

4. In the Virtuoso XStream Out form, click Translate button to start the stream translator.

5. The stream file Inverter.gds is stored in the specified location.

Streaming In the Design

1. Select File – Import – Stream from the CIW menu and change the following

in the form.

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You need to specify the gpdk180_oa22.tf file. This is the entire technology file that

has been dumped from the design library.

2. Click on the Options button.

3. In the StreamOut-Options form select under Layers tab and click OK.

4. In the Virtuoso XStream Out form, click Translate button to start the stream translator.

5. From the Library Manager open the Inverter cellview from the GDS_LIB

library and notice the design.

6. Close all the windows except CIW window, which is needed for the next lab.

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Lab 2: DIFFERENTIAL AMPLIFIER

Schematic Capture

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Simulation

To Calculate the gain of Differential pair:

Configure the Differential pair schematic as shown below –

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Now, open the ADE L, from LAUNCH ADE L , choose the analysis set the ac response and

run the simulation, from Simulation Run. Next go to ResultsDirect plot select AC dB20

and output from the schematic and press escape.

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LAB 3 COMMON SOURCE AMPLIFIER

Schematic Capture

Test Circuit

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Layout Capture

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Lab 4: COMMON DRAIN AMPLIFIER

Schematic Capture


myDesignLib cd_amplifier Symbol

analogLib

vsin

Define pulse specification as

AC Magnitude= 1; DC Voltage= 0;

Offset Voltage= 0; Amplitude= 5m;

Frequency= 1K

analogLib vdd,vss,gnd vdd=2.5 ; vss= -2.5

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Test Circuit

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Lab 5: OPERATIONAL AMPLIFIER

Schematic Capture


myDesignLib op-amp Symbol

analogLib

vsin

Define pulse specification as

AC Magnitude= 1; DC Voltage= 0;

Offset Voltage= 0; Amplitude= 5m;

Frequency= 1K

analogLib vdc, gnd vdd=2.5 ; vss= -2.5

analogLib Idc Dc current = 30u

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Note: Remember to set the values for vdd and vss. Otherwise your circuit will have no power.

Test Circuit

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Layout Capture

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VLSI Viva questions

Which is the software used in this lab?

cadence .

What are the other alternative software apart from cadence used for VLSI design?

Microwind, Tanner, Hspice, Pspice, Mentor graphics, Xilinx etc…

Name the Simulator used in cadence for simulation ?

Insim or incisive simulator

What is RTL ?

RTL stands for Register Transfer Level. It is a high-level hardware description language (HDL)

used for defining digital circuits. The most popular RTL languages are VHDL and Verilog.

What is the difference between simulation and synthesis?

Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of

ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study

including estimated delays, verify setup, hold and other timing requirements of devices like flip

flops are met

Synthesis: One of the foremost in back end steps where by synthesizing is nothing but converting

VHDL or VERILOG description to a set of primitives or components(as in FPGA'S)to fit into

the target technology. Basically the synthesis tools convert the design description into equations

or components.

Which is the tool used for analog design of vlsi circuits?

Virtuoso

What is the platform for virtuoso?

Encounter

Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of

them together for that purpose.

Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass

transistor, both voltage levels need to be passed and hence both nmos and pmos need to be used.

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What are set up time & hold time constraints? What do they signify?

Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the

signal changes state during this interval, the output of that flip-flop cannot be predictable (called

metastable).

Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the

signal changes during this interval, the output of that flip-flop cannot be predictable (called

metastable).

Explain Clock Skew?

clock skew is the time difference between the arrival of active clock edge to different flip-flops’

of the same chip.

Why is not NAND gate preferred over NOR gate for fabrication?

NAND is a better gate for design than NOR because at the transistor level the mobility of

electrons is normally three times that of holes compared to NOR and thus the NAND is a faster

gate. Additionally, the gate-leakage in NAND structures is much lower.

What is Body Effect?

In general multiple MOS devices are made on a common substrate. As a result, the substrate

voltage of all devices is normally equal. However while connecting the devices serially this may

result in an increase in source-to-substrate voltage as we proceed vertically along the series chain

(Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

we try to reverse bias not the channel and the substrate but we try to maintain the drain, source

junctions reverse biased with respect to the substrate so that we don’t loose our current into the

substrate.

What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons (n-channel MOS) or due to holes(p-channel

MOS) - In BJT, we see current due to both the carriers..Electrons and holes. BJT is a current

controlled device and MOSFET is a voltage controlled device

In CMOS technology, in digital design, why do we design the size of pmos to be higher than

the nmos. What determines the size of pmos wrt nmos. Though this is a simple question try

to list all the reasons possible?

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the

carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos

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helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If the

sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output

node. If we have a larger PMOS than there will be more carriers to charge the node quickly and

overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for

the output node.

Why PMOS and NMOS are sized equally in a Transmission Gates?

In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's

the reason why we need not size them like in CMOS. In CMOS design we have NMOS and

PMOS competing which is the reason we try to size them proportional to their mobility.

What happens when the PMOS and NMOS are interchanged with one another in an

inverter?

If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1

O/P will be degraded 1 Similarly degraded 0

Why are pMOS transistor networks generally used to produce high signals, while nMOS

networks are used to product low signals?

This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS

can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in

pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing.

What’s the difference between Testing & Verification?

Testing: A manufacturing step that ensures that the physical device , manufactured from the

synthesized design, has no manufacturing defect.

Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will

perform the given I/O function

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you

avoid Latch Up?

A latch up is the inadvertent creation of a low-impedance path between the power supply rails of

an electronic component, triggering a parasitic structure(The parasitic structure is usually

equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning

of the part. Depending on the circuits involved, the amount of current flow produced by this

mechanism can be large enough to result in permanent destruction of the device due to electrical

over stress - EOS

What is slack?

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The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a

particular path. Slack may be +ve or -ve.

Explain the working of Nmos and Pmos?

Explain the fabrication steps of nmos ,pmos and CMOS?

What happens if we interchange the nmos and pmos in an inverter?

Explain the DC and transient characteristics of inverter?

What is the Need for DRC? And explain the design rules.

Working of flip flops ,counters and adders..

Difference between combinational and sequential circuits?

Difference between MOSFET and BJT?

Difference between latch and flip flops?

Steps involved in digital and analog design.

Why germanium is not used generally for nmos and pmos manufacturing

Moores law

Regions of operation of nmos/pmos.