Test Cost Reduction – Is there more to cut ?

Confidential © ams AG

Test Cost Reduction – Is there more to cut ?

2016 IEEE International Test Conference – Panel 3

Peter Sarson SMIEEE

15th November 2016

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Is there more to cut?

I believe there is a great deal that can be cut depending on the nature of a design and the purpose of the test.

• If a design is marginal, test is not intended to find defects, its intended to find marginal devices – In this case nothing can be done with regard to test time reduction

• If a design has good margins to the specifications then specification based tests are intended to cover defects which is very test time inefficient, if sufficient access to the building blocks of the devices are given then a pure defect based approach to test can be achieved such that both test time and quality can be significantly improved


About Peter Sarson

Who is Peter Sarson exactly?

• I am semiconductor test professional with 16 years of experience developing test solutions.

• My business background is primarily in applications engineering business for the ATE market i.e. selling test services


Definition of test cost

What is my definition of test cost?

• Cost of a test second multiplied by the test time of a device in seconds. The cost of retest needs to be added for devices that fail marginally.

• This can be made more complicated by stating it’s a percentage of a device cost and complexity etc but at the end cost is cost….


Definition of test quality

What is my definition of test quality?

• Test quality is simply the of amount(hopefully in ppm) of a devices that leaves the factory and do not function in the application due to issues not found at test. i.e. 1/(Field Return Rate).

• This should not includes soldering, EOS etc that effect a device after test


Techniques

What techniques do you use for test cost reduction?

We currently use high multisite testing and elements of BIST to try and reduce and control test costs

We have developed/are developing structural test approaches so as reduce the amount of test time of inefficient specification based testing.


Expectations

What do you expect to BIST/BOST/DFT for LSI test cost reduction and test quality improvement?

BIST can certainly help with test time savings due to having to use less complex tester instruments which helps with the multisite count, however this comes at the cost of quality as generally BIST will miss some outliers


Test cost balance for mixed-signal SoC

What is the test cost balance between analog part and digital part for mixed-signal SoC at ams?

ams devices are primarily analogue devices, the digital content is generally low and tested with some SCAN vectors. ams is a Big-A/Little-d house.

However the cost of the digital in a typical project is negligible compared to the analogue as the test time is significantly lower such that the cost of the balance would be 99.5% analogue to digital ratio


LSI test cost reduction

Your position regarding LSI test cost reduction?

My position on LSI test cost reduction is simply to test for defects and not specifications, in the automotive space this is difficult as all datasheet parameters with Max, Min limits have to be tested. However if correlation is proven then this is allowed.


Management strategy

What is the ams management strategy regarding LSI testing?

• The management strategy at the Full Service Foundry division of ams is to encourage our customers to implement as much DFT, BIST and test access as is possible without affecting the device cost margins due to die size limitations.

• Our test engineers double as DFT consultants during the design phase of a device however the customer design engineer is finally responsible for the end test strategy as they are the final owner of the product.


Further steps

Is only test cost reduction enough?

• No, we need to be driving the quality aspect also with Defect based testing,

• Better and cheaper!


Cost/performance for LSI testing

What do you think about cost/performance for LSI testing?

Cost should be a function of the test access, not specifically BIST. More effort/cost should be made such that individual nodes of a device are easily accessible so that test of individual building blocks of the device can be tested independently.


FOM for LSI test technology

What is your definition of FOM for LSI test technology?

• I think the FOM is simply the return rate from the field in ppm multiplied by the amount it costs to test device no matter if it is Automotive or consumer.

• If it is a problem for the customer, they will return it

• FOM = RMA(ppm) x test_cost_per_device x 1e6

• The lower the number the better


Balance between test cost and quality

What do you think about balance between test cost and quality?

The question really means when do you want to spend the money…

If the quality isn’t addressed at test, it has to be addressed by QA professionals as they receive an avalanche of RMA’s

The question of cost cannot be avoided, nothing is for free

There is no such thing as a free lunch people


Future innovations and challenges

What are the expected innovation and challenge for test cost reduction in the future?

• This purely lies in the Defect based testing area using tools such as the Mentor DefectSim

• Requires to invest in test access mechanisms such as the industry working group to extend 1687


Happiness

How do your LSI testing work make people (users of final products, your customers, your company, yourself) happy?

If the device works to spec, has no returns, is cheap and a large margin. Everyone is happy.


Philosophy

What is your overall philosophy related to LSI testing?

A device might be the best in the world but if you cant test it, it is worthless

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Test Cost Reduction – Is there more to cut ?