Spiceを活用した電源回路シミュレーションセミナーテキスト 18 feb2015

SPICE を活用した電源回路シミュレーションセミナー

1. 　回路方式 ( トポロジー ) 検討時の SPICE 活用方法1.1 　降圧回路1.2 　昇圧回路1.3 　昇降圧回路1.4 　 PFC 回路1.5 　アベレージモデルの活用 ( 降圧回路 )

2. 　詳細設計時の SPICE 活用方法2.1 DCDC コンバータによる昇圧回路2.2 擬似共振電源回路 (Quasi-resonant Switching Power Supply)

3. 　質疑応答

2015 年 2 月 18 日 ( 水曜日 )

1Copyright(C) MARUTSU ELEC 2015


2014 年 9 月 25 日 ( 木曜日 )


Copyright(C) MARUTSU ELEC 2015 4

半導体メーカー及び電子部品メーカー ( サプライヤ企業 )

電子機器メーカー

自動車メーカー

社会インフラメーカー

(1) お客様への自社製品の SPICE モデルの提供(2) 自社製品のアプリケーション回路開発

(1) 研究開発及び設計(2) 故障解析キーワード：電源回路、インバータ回路、モーター駆動回路、 LED 照明回路及び電池回路

(1) 研究開発及び設計キーワード： AC モーター駆動回路、インバータ回路、 LED 照明回路 HEV 、 EV 、　　　　　　　二次電池、燃料電池及び回生回路

(1) 全体システム回路設計(2) 故障解析キーワード：太陽電池システム、スマートグリッドシステム、二次電池

対象の市場


【環境発電 ( エナジーハーベスト ) 分野】発電デバイス + ハーベスト IC+ アプリケーション回路

【生体信号分野】⇒ 人体の SPICE モデル＋電子回路シミュレーション(1) 心臓(2) 脳＋神経(3) 血液

【教育分野】(1) 実務向けオンサイトセミナー⇒ 企業向け教育プログラムの提供及び実施(2) 教育用プログラム⇒LTspice で回路学習 + キットで実機学習

光起電力 ( 太陽電池 )

振動発電 ( ピエゾ素子 )

温度差発電 ( ペルチェ素子 )

＋ハーベスト IC ＋アプリケーション回路

対象の市場


回路解析シミュレータの用途は、多様化しています。

(1) 研究開発　　①次世代半導体のデバイスモデリング及びアプリケーション開発　　②システム開発及び回路開発の回路動作現象(2) 回路設計　　①アプリケーション開発　　②トポロジーの開発及び選定　　③回路設計及び回路動作検証　　④損失計算　　⑤ノイズ検証　　⑥熱解析(3) クレーム解析　　①故障解析　　②オープン・ショート　　③想定外使用　　④サージ解析

回路解析シミュレータの用途の多様化


回路シミュレーションのポイント

【ポイント 1】回路解析シミュレーションの解析精度 =スパイスモデルの解析精度である。　■有償 SPICE でも無償 SPICE でも採用する SPICE モデルで解析精度が決定される。　■ 1 個でも変な動作をするスパイスモデルがあると NG

【ポイント 2】シミュレーションの用途に応じた SPICEモデルを採用する。　■波形動作確認であれば、簡易 SPICE モデルでも問題ない。　■損失計算を行う場合、過渡現象において再現性のある SPICE モデルを採用する。　■温度シミュレーションをしたい場合には、温度対応 SPICE モデルを採用する。　■ノイズシミュレーションをしたい場合には、ノイズ対応 SPICE モデルを採用する。

【ポイント 3】回路シミュレーションをする回路は正確に入力する。　■回路シミュレーションをする場合、回路知識が必要です。　■回路解析結果の正誤を判断する必要があります。


回路設計のワークフロー

仕様

回路方式選択( トポロジーの選定 )

詳細回路設計回路図作成材料表作成

基板設計

回路設計

ビー・テクノロジー製品及びサービス

コンセプトキット製品

デザインキット製品シンプルモデル

デバイスモデリング教材スパイス・パーク

デバイスモデリングサービス

カスタムデザインキットサービス

ビー・テクノロジー製品及びサービス


シミュレーション上の課題について

第一の壁

第二の壁

第三の壁

第一の壁： SPICE の習得第二の壁： SPICE モデルの入手第三の壁：シミュレーション技術


シミュレーション解析時間

10％90％

実際のシミュレーション解析時間

実際の解析時間は 10％程度です。 90％の時間を SPICE モデルの入手に費やしています。

SPICE モデルの入手に費やしています。

●サプライヤ企業から入手する●スパイス・パークからダウンロードする●デバイスモデリングサービスを活用する●自分で SPICE モデルを作成する



ダイオードの SPCIE モデルを作成する場合の事例(ダイオードの SPICE モデルは 3種類ある )

デバイスモデリングの難易度

高い

低い

電流減少率モデル⇒等価回路で -didt を再現している

IFIR 法モデル⇒等価回路で Trr(trj +trb) を再現している

パラメータモデル⇒ パラメータだけで作成できる簡易型モデル



① 再現性問題　　実機波形とシミュレーション波形が合わない【解決方法】○目的に合った SPICE モデルを採用する○目に見えない寄生素子も考慮し、回路図に反映させる【ご提供するサービス】○SPICE モデルをご提供する「デバイスモデリングサービス」○シミュレーションデータをご提供する「デザインキットサービス」

② 解析時間問題　　早くシミュレーション結果を知りたいのにシミュレーションに多くの時間を有する【解決方法】○目的に合った SPICE モデルを採用する○タイムスケール機能を採用する【ご提供するサービス】○SPICE モデルをご提供する「デバイスモデリングサービス」○シミュレーションデータをご提供する「デザインキットサービス」

③収束エラー問題　　最後までシミュレーションが実行出来ず、途中で計算が止まってしまう。【解決方法】○SPICE の .OPTIONS のパラメータを最適化する。○スナバ回路等を挿入して急変する過渡応答性、過渡現象を緩和する。○回路動作に影響しないように微小抵抗を適宜挿入する。【ご提供するサービス】○収束エラー解決サービス



14

1.1 降圧回路のトポロジー

出展： TDK

Copyright(C) MARUTSU ELEC 2015

15

降圧回路

降圧回路のタイミングチャート

1.1 降圧回路のトポロジー

①VCTRL

①

②

②IL

③

③VL

④

⑤

⑥IF

⑤VDS

⑥

④ID

⑦

⑦VKA


16

1.1 降圧回路シミュレーション

降圧回路シミュレーションの回路図

http://youtu.be/NOS2cJSH2is


http://youtu.be/NOS2cJSH2is

17

降圧回路シミュレーション結果


起動状態の観察

シミュレーション結果の観察のポイントは、 3つあります。

突入状態の観察定常状態の観察


18

降圧回路シミュレーション結果 (M1)



19

降圧回路シミュレーション結果 (D1)



20

降圧回路シミュレーション結果 (M1)



21

降圧回路シミュレーション結果 (D1)



22

1.2 昇圧回路のトポロジー

出展： TDK


23

昇圧回路

昇圧回路のタイミングチャート

1.2 昇圧回路のトポロジー

①VCTRL

①

②

②IL

③

③VL

④

⑤

⑥IF

⑤VDS

⑥

④ID

⑦VKA

⑦


24

1.2 昇圧回路シミュレーション

昇圧回路シミュレーションの回路図

http://youtu.be/KZdb6drG408


http://youtu.be/KZdb6drG408

25

昇圧回路シミュレーション結果



26


昇圧回路シミュレーション結果 (M1)


27


昇圧回路シミュレーション結果 (D1)


28


昇圧回路シミュレーション結果 (M1)


29


昇圧回路シミュレーション結果 (D1)


30

1.3 昇降圧回路シミュレーション


31



32



33



34



35



V 1

F R E Q = 5 0V A M P L = 9 0V O F F = 0

A C =

D 1D 2 5 XB 8 0

D 2D 2 5 XB 8 0

D 3D 2 5 XB 8 0

D 4D 2 5 XB 8 0

L 1

0 . 5 8 m H

L 2

0 . 5 8 m H

U 1S F 1 0 L C 4 0

U 22 S K 4 2 0 7

U 32 S K 4 2 0 7

V P U L S E 1

TD = 5 u

TF = 1 nP W = 3 uP E R = 1 0 u

V 1 = 0

TR = 1 n

V 2 = 1 2

V P U L S E 2

TD = 0

TF = 1 nP W = 3 uP E R = 1 0 u

V 1 = 0

TR = 1 n

V 2 = 1 2

R 1

1 5

R 2

1 5

C 11 0 0 0 0 u

R L1 8

0

V

V

V

PFC(Interleaved CCM) IC

MOSFET1

MOSFET2

1.4 PFC 回路シミュレーション


MOSFET2

MOSFET1

OUTPUT

Inductor Current



MOSFET2

MOSFET1

OUTPUT

Inductor Current



1.5 アベレージモデルの活用 ( 降圧回路 )

Concept Kit:PWM Buck Converter Average Model

Power Switches Filter & LoadPWM Controller (Voltage Mode Control)

VREF

VOUT

REF

PWM

1 / V p

-

+

U ?P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

D

U ?B U C K _ S W

L1 2

C

R lo a d

V o

E S R



• Concept of Simulation• Buck Converter Circuit• Averaged Buck Switch Model• Buck Regulator Design Workflow

1. Setting PWM Controller’s Parameters.2. Programming Output Voltage: Rupper, Rlower3. Inductor Selection: L4. Capacitor Selection: C, ESR5. Stabilizing the Converter (Example)

• Load Transient Response Simulation (Example)AppendixA. Type 2 Compensation Calculation using ExcelB. Feedback Loop CompensatorsC. Simulation Index



Power Switches

Averaged Buck Switch Model

Filter & Load

Parameter:• L• C• ESR• Rload

PWM Controller (Voltage Mode Control)

Parameter:• VP

• VREF

Models:

Block Diagram:

VREF

VOUT

D

U ?B U C K _ S W

REF

PWM

1 / V p

-

+

U ?P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

L1 2

C

R lo a d

V o

E S R



L1 2

C

R lo a d

0

C o m p

C 2

R 2 C 1

F B

Type 2 Compensator

R u p p e r

R lo we r

0

d

V inD

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

V o

E S R

Filter & Load

PWM Controller

Power Switches



• The Averaged Buck Switch Model represents relation between input and output of the switch that is controlled by duty cycle – d (value between 0 and 1).

• Transfer function of the model is

vout = d vin

• The current flow into the switch is

iin = d iout

D

U 2B U C K _ S W

vin

+

-

vout

+

-D

iin iout

Averaged Buck Switch Model



Setting PWM Controller’s Parameters: VREF, VP1

Setting Output Voltage: Rupper, Rlower2

Inductor Selection: L3

Capacitor Selection: C, ESR4

Stabilizing the Converter: R2, C1, C2

• Step1: Open the loop with LoL=1kH and CoL=1kF then inject an AC signal to generate Bode plot. (always default)

• Step2: Set C1=1kF, C2=1fF, (always keep the default value) and R2= calculated value (Rupper//Rlower) as the initial values.

• Step3: Select a crossover frequency (about 10kHz or fc < fosc/4). Then complete the table.

• Step4: Read the Gain and Phase value at the crossover frequency (10kHz) from the Bode plot, Then put the values to the table

• Step5: Select the phase margin at the fc ( > 45 ). Then change the K value until it gives the satisfied phase margin, for this example K=6 is chosen for Phase margin = 46.

• Remark: If K-factor fail to gives the satisfied phase margin, Increase the output capacitor C then try Step1 to Step5 again.

Load Transient Response Simulation

5

6

デザインのワークフロー



1

2

3

4

5

L1 2

C

R lo a d

0

C o m p

C 2

R 2 C 1

F B

Type 2 Compensator

R u p p e r

R lo we r

0

d

V inD

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

V o

E S R

デザインのワークフロー



1 Setting PWM Controller’s Parameters

•VREF, feedback reference voltage, value is given by the datasheet

•VP = (Error Amp. Gain vFB ) / d• vFB = vFBH – vFBL

• d = dMAX – dMIN

• Error Amp. Gain is 100 (approximated)

where

VP is the sawtooth peak voltage.

vFBH is maximum FB voltage where d = 0

vFBL is minimum FB voltage where d =1(100%)

dMAX is maximum duty cycle, e.g. d = 0(0%)

dMIN is minimum duty cycle, e.g. d =1(100%)

REF

PWM

1 / V p

-

+

U ?P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

vcomp

d

Error Amp.

FB

The PWM block is used to transfer the error voltage (between FB and REF) to be the duty cycle.

If vFBH and vFBL are not provided, the default value, VP=2.5 could be used.

TimeV(PWM)

V(osc) V(comp)0V

2.0V

3.0V

SEL>> VP

Duty cycle (d) is a value from 0 to 1



1 Setting PWM Controller’s Parameters (Example)

from

VP = (Error Amp. Gain vFB )/d

•Error Amp. Gain = 100 (approximated)•from the graph on the left, vFB = 25mV (15m - (-10m))•d = 1 – 0 = 1

VP ≈ ( 100 25mV )/1 ≈ 2.5V

If the VP ( sawtooth signal amplitude ) does not informed by the datasheet, It can be approximated from the characteristics below.

LM2575: Feedback Voltage vs. Duty Cycle

vFB = 25mV

d = 1 (100%)

dMIN dMAX

vFBH

vFBL

If vFBH and vFBL are not provided, the default value, VP=2.5 could be used.



2 Setting Output Voltage: Rupper, Rlower

• Use the following formula to select the resistor values.

• Rlower can be between 1k and 5k.

ExampleGiven: VOUT = 5V

VREF = 1.23

Rlower = 1k

then: Rupper = 3.065k

C o m p

C 2

R 2 C 1

Type 2 Compensator

F B

R u p p e r

R lo we r

0

d

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

Error Amp.

Vo

lower

upperREFOUT

R

RVV 1



3

Inductor Value• The output inductor value is selected to set the converter

to work in CCM (Continuous Current Mode) or DCM (Discontinuous Current Mode).

• Calculated by

Where

• LCCM is the inductor that make the converter to work in CCM.

• VI,max is input maximum voltage

• RL,min is load resistance at the minimum output current ( IOUT,min )

• fosc is switching frequency

L1 2

C

R lo a d

V o

E S R

max,

min,max,

2 Iosc

LOUTICCM

Vf

RVVL

Inductor Selection: L



3 Inductor Selection: L (Example)

Inductor Valuefrom

Given: • VI,max = 40V, VOUT = 5V

• IOUT,min = 0.2A

• RL,min = (VOUT / IOUT,min ) = 25

• fosc = 52kHz

Then:• LCCM 210(uH), • L = 330(uH) is selected

L1 2

C

R lo a d

V o

E S R

max,

min,max,

2 Iosc

LOUTICCM

Vf

RVVL



4 Capacitor Selection: C, ESR

Capacitor Value• The minimum allowable output capacitor value should be

determined by

Where• VI, max is the maximum input voltage.

• L (H) is the inductance calculated from previous step ( ).

• In addition, the output ripple voltage due to the capacitor ESR must be considered as the following equation.

L1 2

C

R lo a d

V o

E S R

F)H(

785,7max,

LV

VC

OUT

I

RIPPLEL

RIPPLEO

I

VESR

,

,

3



4 Capacitor Selection: C, ESR (Example)

Capacitor ValueFrom

and

Given:• VI, max = 40 V

• VOUT = 5 V• L (H) = 330

Then:• C 188 (F)

In addition:• ESR 100m

L1 2

C

R lo a d

V o

E S R

RIPPLEL

RIPPLEO

I

VESR

,

,

F)H(

785,7max,

LV

VC

OUT

I



5

• Loop gain for this configuration is

L1 2

R lo a d

C

0

C o m p

C 2

R 2 C 1

Type 2 Compensator

F B

R u p p e r3 . 0 6 6 k

R lo we r1 . 0 k

0

d

V in1 2 V d c

D

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

V o

E S R

• The purpose of the compensator G(s) is to tailor the converter loop gain (frequency response) to make it stable when operated in closed-loop conditions.

PWMGsGsHsT )()()( GPWM

G(s)

H(s)

Stabilizing the Converter



5 Stabilizing the Converter (Example)

Specification:VOUT = 5VVIN = 7 ~ 40VILOAD = 0.2 ~ 1A

PWM Controller:VREF = 1.23VVP = 2.5VfOSC = 52kHz

Rlower = 1k,Rupper = 3.1k,L = 330uH, C = 330uF (ESR = 100m)

Task: • to find out the element of the Type 2

compensator ( R2, C1, and C2 )

L3 3 0 u H

1 2

C3 3 0 u F

R lo a d5

0

0

C O L1 k F

L O L

1 k H

C 2

R 2 C 1

F B

R u p p e r3 . 1 k

Type 2 Compensator

R lo we r1 . 0 k

0

d

V 31 V a c0 V d c

V in1 2 V d c

D

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

V o

E S R1 0 0 m

G(s)

e.g. Given values from National Semiconductor Corp. IC: LM2575

1

34

2



L3 3 0 u H

1 2

C3 3 0 u F

R lo a d5

0

0

C O L1 k F

L O L

1 k H

R 20 . 7 5 6 k

F B

R u p p e r3 . 1 k

Type 2 Compensator

R lo we r1 k

0

d

V 31 V a c0 V d c

V in1 2 V d c

D

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

V o

E S R1 0 0 m

C 21 f

C 11 k

Step2 Set C1=1kF, C2=1fF, and R2=calculated value (Rupper//Rlower) as the initial values.

Step1 Open the loop with LoL=1kH and CoL=1kF then inject an AC signal to generate Bode plot.

The element of the Type 2 compensator ( R2, C1, and C2 ), that stabilize the converter, can be extracted by using Type 2 Compensator Calculator (Excel sheet) and open-loop simulation with the Average Switch Models (ac models).

C1=1kF is AC shorted, and C2 1fF is AC opened (or Error-Amp without compensator).





Type 2 Compensator Calculator

Switching frequency, fosc : 52.00 kHzCross-over frequency, fc (<fosc/4) : 10.00 kHzRupper : 3.1 kOhmRlower : 1 kOhmR2 (Rupper//Rlower) : 0.756 kOhm (automatically calculated)

PWMVref : 1.230 VVp (Approximate) : 2.5 V

Step3 Select a crossover frequency (about 10kHz or fc < fosc/4 ), for this example, 10kHz is selected. Then complete the table.

Calculated value of the Rupper//Rlower

values from 2

values from 1




Parameter extracted from simulationSet: R2=R1, C1=1k, C2=1fGain (PWM) at foc ( - or + ) : -44.211Phase (PWM) at foc : 65.068

Frequency

100Hz 1.0KHz 10KHz 100KHzP(v(d))

0d

90d

180d

SEL>>

(10.000K,65.068)

DB(v(d))

-80

-40

0

40

80

(10.000K,-44.211)

Step4 Read the Gain and Phase value at the crossover frequency (10kHz) from the Bode plot, Then put the values to the table.

Tip: To bring cursor to the fc = 10kHz type “ sfxv(10k) ” in Search Command.

Cursor Search

Gain: T(s) = H(s)GPWM

Phase at fc




K-factor (Choose K and from the table)K 6q -199 ° (automatically calculated)

Phase margin : 46 (automatically calculated)

R2 : 122.780 kOhm (automatically calculated)C1 : 0.778 nF (automatically calculated)C2 : 21.600 pF (automatically calculated)

Step5 Select the phase margin at fc (> 45 ). Then change the K value (start from K=2) until it gives the satisfied phase margin, for this example K=6 is chosen for Phase margin = 46.

As the result; R2, C1, and C2 are calculated.

K Factor enable the circuit designer to choose a loop cross-over frequency and phase margin, and then determine the necessary component values to achieve these results. A very big K value (e.g. K > 100) acts like no compensator (C1 is shorted and C2 is opened).

Remark: If K-factor fail to gives the satisfied phase margin, Increase the output capacitor C then try Step1 to Step5 again.




R 21 2 2 . 7 8 0 k

Type 2 Compensator

C 22 1 . 6 p

C 10 . 7 7 8 n

L3 3 0 u H

1 2

C3 3 0 u F

R lo a d5

0

0

C O L1 k F

L O L

1 k H

F B

R u p p e r3 . 1 k

R lo we r1 k

0

d

V 31 V a c0 V d c

V in1 2 V d c

D

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

V o

E S R1 0 0 m

The element of the Type 2 compensator ( R2, C1, and C2 ) extraction can be completed by Type 2 Compensator Calculator (Excel sheet) with the converter average models (ac models) and open-loop simulation.

The calculated values of the type 2 elements are, R2=122.780k, C1=0.778nF, and C2=21.6pF.

*Analysis directives: .AC DEC 100 0.1 10MEG




Frequency

100Hz 1.0KHz 10KHz 100KHzP(v(d))

0d

90d

180d

(9.778K,45.930)

DB(v(d))

-40

0

40

80

-100SEL>>

(9.778K,0.000)

• Phase margin = 45.930 at the cross-over frequency - fc = 9.778kHz.

Tip: To bring cursor to the cross-over point (gain = 0dB) type “ sfle(0) ” in Search Command.

Cursor Search

Gain: T(s) = H(s) G(s)GPWM

Phase at fc

Gain and Phase responses after stabilizing



Load Transient Response Simulation (Example)

R 21 2 2 . 7 8 0 k

C 22 1 . 6 p

Type 2 Compensator

C 10 . 7 7 8 n

L o a d

V o

I 1

TD = 1 0 mTF = 2 5 u

P W = 0 . 4 3 mP E R = 1

I 1 = 0I 2 = 0 . 8

TR = 2 0 u

R lo a d2 5

0

F B

R u p p e r3 . 1 k

R lo we r1 k

0

d

V in2 0 V d c

D

U 2B U C K _ S W

REF

PWM

1 / V p

-

+

U 3P W M _ C TR L

V P = 2 . 5V R E F = 1 . 2 3

L3 3 0 u H

1 2

C3 3 0 u F

E S R1 0 0 m

The converter, that have been stabilized, are connected with step-load to perform load transient response simulation.

5V/2.5 = 0.2A step to 0.2+0.8=1.0A load

*Analysis directives: .TRAN 0 20ms 0 1u



Load Transient Response Simulation (Example)

• Simulation • MeasurementOutput Voltage Change

Load Current

• The simulation results are compared with the measurement data (National Semiconductor Corp. IC LM2575 datasheet).

Time

9.9ms 10.1ms 10.3ms 10.5ms 10.7ms 10.9ms1 V(vo) 2 I(load)

4.4V

4.5V

4.6V

4.7V

4.8V

4.9V

5.0V

5.1V

5.2V1

0A

0.5A

1.0A

1.5A

2.0A

2.5A

3.0A

3.5A

4.0A2

>>



A. Type 2 Compensation Calculation using Excel

Switching frequency, fosc : 52.00 kHz Given spec, datasheetCross-over frequency, fc (<fosc/4) : 10.00 kHz Input the chosen value ( about 10kHz or < fosc/4 )Rupper : 3.1 kOhm Given spec, datasheet, or calculated Rlower : 1 kOhm Given spec, datasheet, or value: 1k-10k OhmR2 (Rupper//Rlower) : 0.756 kOhm (automatically calculated)

PWMVref : 1.230 V Given spec, datasheetVp (Approximate) : 2.5 V Given spec, or calculated, (or leave default 2.5V)

Parameter extracted from simulationSet: R2=R2, C1=1k, C2=1fGain (PWM) at foc ( - or + ) : -44.211 dB Read from simulation resultPhase (PWM) at foc : 65.068 ° Read from simulation result

K-factor (Choos K and q from the table)K 6 Input the chosen value (start from k=2)q -199 ° (automatically calculated)

Phase margin : 46 (automatically calculated) Target value > 45

R2 : 122.780 kOhm (automatically calculated)C1 : 0.778 nF (automatically calculated)C2 : 21.60 pF (automatically calculated)



B. Feedback Loop Compensators

Type 1 Compensator

C 1

V O U T

F B

R u p p e r

R lo we r

0

d

REF

PWM

1 / V p

-

+

P W M _ C TR L

Type1 Compensator Type2 Compensator Type2a Compensator

Type2b Compensator Type3 Compensator

Type2b Compensator

C 1

V O U T

F B

R u p p e r

R lo we r

0

d

REF

PWM

1 / V p

-

+

P W M _ C TR L

R 2

Type2a Compensator

C 1

V O U T

F B

R u p p e r

R lo we r

0

d

REF

PWM

1 / V p

-

+

P W M _ C TR L

R 2

Type3 Compensator

C 1

F B

R u p p e r

R lo we r

0

d

REF

PWM

1 / V p

-

+

P W M _ C TR L

C 2

R 2

C 3

R 3

V O U T

Type2 Compensator

C 1

F B

R u p p e r

R lo we r

0

d

REF

PWM

1 / V p

-

+

P W M _ C TR L

C 2

R 2

V O U T


2.1 DCDC コンバータによる昇圧回路

Design KitNJM2377–Boost DC/DC Converter



1. NJM2377 – Boost DC/DC Converter Circuit2. PWM – Boost DC/DC Converter Basic Operation and Design

2.1 Boost DC/DC Converter – VOUT

2.2 Boost DC/DC Converter – tON /tOFF

2.3 Boost DC/DC Converter – Inductor Selection2.4 Boost DC/DC Converter – Inductor Peak Current2.5 Boost DC/DC Converter – COUT Selection

3. NJM2377 – Application Circuit Configuration3.1 NJM2377 – Soft Start Time Setting3.2 NJM2377 – Oscillation Frequency Setting3.3 Error Amp Feed Back Loop Setting

4. Performance Characteristics4.1 Output Start-Up Voltage and Current4.2 Output Ripple Voltage4.3 Efficiency4.4 Step-Load Response

5. Voltage and Current Simulation Result6. Losses

6.1 Bipolar Junction Transistor Losses6.2 Schottky Barrier Diode Losses

7. Waveforms7.1 Start-Up Sequencing Waveforms7.2 Switching Waveform at Load 50mA7.3 Switching Waveform at Load 10mA



C L P1 0 0 p F

R f5 6 0 k

E S R0 . 1 0 3

C in2 2 0 u F

L

1 5 0 u

1 2

R lo a d

1 8 0

R 19 . 1 k

R 21 5 0 k

Q 1Q 2 S D 2 6 2 3

O U TR 3

0 . 8

U 1N J M 2 3 7 7

-IN

FB

GN

DO

UT

V+

CS

CT

RE

F

R t2 4 k

C t4 7 0 p FI C = 0

D 1H R U 0 3 0 2 A

0V +

5 V

0

I N

C o u t

2 2 0 u F

R s f1 6 0 k

C S4 . 7 u FI C = 0

0

R s r1 8 0 k

0

5V to 9V at 50mA Boost DC/DC Converter (fOSC=150kHz, Vripple=30mVp-p)

U1: New Japan Radio NJM2377 Control IC

Q1: Panasonic 2SD2623 NPN

D1: Renesas HRU0302A Schottky Barrier Diode

1. NJM2377 – Boost DC/DC Converter Circuit



2. PWM – Boost DC/DC Converter Basic Operation and Design

E S R

I NL

1 2

R lo a d

O U T

R 1

R 2

Q 1Q N _ S W

V +

0

C o u t

D 1

PWM ControlCircuit PWM output

pulse

VOUT=9V

tON tOFF

VIN=5V L: IL

• VOUT is monitored by R1 and R2 then compared to reference voltage VB in NJM2377.

• Error voltage is pulse width modulated with sawtooth waveform.• PWM output pulse width is proportional to the error level. This signal will control the

switch ON/OFF(tON /tOFF).

• Therefore VOUT, which is proportional to tON /tOFF, is controlled to the desired voltage.

2.1)

2.5)

2.2)

2.3),2.4)


2.1 DCDC コンバータによる昇圧回路2.1 Boost DC/DC Converter – VOUT

• VOUT is determined by R1 and R2, without considering I(IN-) of NJM2377 VOUT is calculated as below.

• For VOUT=9V, R1=9.1kΩ, R2=150kΩ are selected.

9.09V0.5219.1k

150k

11

2

REFOUT V

R

RV


2.1 DCDC コンバータによる昇圧回路2.2 Boost DC/DC Converter – tON /tOFF

• If the circuit works in continuous conduction mode (CCM), output voltage (VOUT) and ON/OFF time (tON /tOFF) follow the equation below.

then

• From VIN =5V, VOUT =9V and fOSC =150kHz, these result as tON /tOFF are tON=2.96μs, tOFF=3.71μs, and duty=45%.

INOFF

OFFONOUT V

t

ttV

OSCOUT

INOUTON

fV

VVt


2.1 DCDC コンバータによる昇圧回路2.3 Boost DC/DC Converter – Inductor Selection

• LMIN value for the convertor to work in continuous conduction mode (CCM), is calculated as below.

• From VIN =5V, VOUT =9V, IOUT =50mA and tON=2.96μs, these result as LMIN=82.2μH.

• A larger value will be used to increase the available output current, but limit it to around twice the LMIN value. L =150μH is selected.

ONOUTOUT

INMIN t

IV

VL

2

2

MINMIN LL L 2


2.1 DCDC コンバータによる昇圧回路2.4 Boost DC/DC Converter – Inductor Peak Current

Time

86.810ms 86.816ms 86.822ms 86.828msI(L)

0A

50mA

100mA

150mA

200mA

(86.818m,140.985m)

(86.821m,40.531m)

• PSpice is used to verify the circuit design.

• IL, PK=140.985mA and

IL,PK=140.985m-40.531m=100.454mA

• IL, PK is calculated as below.

• And the current ripple - IL, PK is calculated as below

140mA2.96μ150μ2

5

5

0.059

2

ONIN

IN

OUTOUTL,PK t

L

V

V

IVI

mA992.96μ150μ

5

ONIN

L,PK tL

VΔI

•Add trace I(L)•Zoom to check the peak value.

IL, PK


2.1 DCDC コンバータによる昇圧回路2.5 Boost DC/DC Converter – COUT Selection

• PSpice is used to verify the circuit design.

• IL,PK=101.168mA, ton=3μs.

• Vripple =14.8mVp-p

• Irms*=53.856mArms.

Irms is larger than calculated value due to feedback loop

response ripple current.

Time

87.5484ms 87.5684msV(OUT)

9.06V

9.07V

9.08V

9.09V

SEL>>

(87.556m,9.0792)

(87.553m,9.0644)

I(L) rms(I(Cout))0A

100mA

200mA(87.556m,141.564m)

(87.553m,40.396m)

• COUT is determined from the Vripple Spec (30mVp-p).

• If COUT >> IOUTton/Vripple (50m2.96μ/30m=4.933μF), Vripple will mainly caused by ESR.

• Select the capacitor that can handle the ripple current Irms.

• COUT=220μF, ESR=103m is selected.

m10399m

30m

)(

L

ppripple

I

VESR

IL, PK

13mArms6.67μ

2.96μ

32

99m

32

t

tonII

Lrms

Irms

Vripple


2.1 DCDC コンバータによる昇圧回路3. NJM2377 – Application Circuit Configuration

C L P1 0 0 p F

R f5 6 0 k

E S R0 . 1 0 3

C in2 2 0 u F

L

1 5 0 u

1 2

R lo a d

1 8 0

R 19 . 1 k

R 21 5 0 k

Q 1Q 2 S D 2 6 2 3

O U TR 3

0 . 8

U 1N J M 2 3 7 7

-IN

FB

GN

DO

UT

V+

CS

CT

RE

F

R t2 4 k

C t4 7 0 p FI C = 0

D 1H R U 0 3 0 2 A

0V +

5 V

0

I N

C o u t

2 2 0 u F

R s f1 6 0 k

C S4 . 7 u FI C = 0

0

R s r1 8 0 k

0

5V to 9V at 50mA Boost DC/DC Converter (fOSC=150kHz)




3.1)

3.2)

3.3)



3.1 NJM2377 – Soft Start Time Setting

• First, caculate Rsr by Rsr>VTHLA(max.)/ICHG(min.) (1.8V/10μA=180k)

• During steady state operation, I(CS)=IBCS=250ns. Maximum duty cycle is determined by V(CS). Set V(CS)=VTHCS(max.)=0.8V, Rsf is calculated by

160kΩRsf

1.5Rsf180k

180k 0.8

.)(max

REFTHCS VRsfRsr

RsrV

• Soft-start time or tduty(max.) is time needed for V(CS) to reach VTHCS(max.) by charging capacitor Cs.

• CS is charged by current Ics, calculated by:

then

NJM2377 soft-start time is determined by Rsr, CS and Rsf

4.41uA160k180k

1.5

RsfRsr

VI

REFCS

109ms30μ4.41μ

4.7μ0.8

.)(max.)(max

CHGCS

THCSduty

II

CsVt


2.1 DCDC コンバータによる昇圧回路3.1 NJM2377 – Soft Start Time Setting (Simulation)

NJM2377 soft-start time is determined by Rsr, Rsf and CS

• Select Rsr, Rsf, and CS then check tduty(max.) by simulation.

• tduty(max.)=109.170ms. for CS=4.7uF

• tduty(max.)=76.653ms for CS=3.3uF and tduty(max.)=157.953ms for CS=6.8uF.

C S{C S }

I C = 0

PARAMETERS:C S = 4 . 7 u

C L P1 0 0 p F

R f5 6 0 k

C in2 2 0 u F

U 1N J M 2 3 7 7

-IN

FB

GN

DO

UT

V+

CS

CT

RE

F

R t1 0 M E G

C t1 0 n F

I C = 00 C S

V +

5 V

I N

R E F

0

R s f1 6 0 k

0

R s r1 8 0 k

0

R 11 M E G

.TRAN 0 500ms 0 Time

0s 250ms 500msV(CS)

0V

0.5V

1.0V

1.5V

(109.170m,800.000m)

(76.653m,800.000m)

(157.953m,800.000m)


2.1 DCDC コンバータによる昇圧回路3.2 NJM2377 – Oscillation Frequency Setting

• CT = 470pF and RT = 24kΩ to set an oscillation frequency to be 150kHz.

V

C L P1 0 0 p F

R f5 6 0 k

C in2 2 0 u F

U 1N J M 2 3 7 7

-IN

FB

GN

DO

UT

V+

CS

CT

RE

F

R t2 4 k

C t4 7 0 p F

I C = 00

V +

5 V

I N

0

R s f1 6 0 k

C S4 . 7 u FI C = 0

0

R s r1 8 0 k

0

R 11 M E G

NJM2377 oscillation frequency fOSC is determined by CT and RT

fosc=150kHz

RT=24k


2.1 DCDC コンバータによる昇圧回路3.3 Error Amp Feed Back Loop Setting

• For F.B loop gain G > 100, Rf is calculated as:

• CLP is suggested to use value between 100pF~1,000pF

• Inappropriate F.B loop design can cause an oscillation. PSpice is used to verify the ripple voltage vs. Rf and CLP values.

• Simulation result shows Vripple of the circuit with RF=1000k compare to the circuit with RF=560k.

• Changing RF to be 560k can reduce Vripple from 34mVp-p to less than 20mVp-p.

1000kRf

177150k//9.1k

1,000k

2//1

RR

RfG

Error Amp Feed Back Loop is determined by R1, R2, Rf and CLP

Time

79.00ms 79.25ms 79.50ms 79.75ms 80.00msV(OUT)

9.04V

9.06V

9.08V

9.10V

9.12V

RF=1000k, CLP=100pF

RF=560k, CLP=100pF


2.1 DCDC コンバータによる昇圧回路4. Performance Characteristics

C L P1 0 0 p F

R f5 6 0 k

E S R0 . 1 0 3

C in2 2 0 u F

L

1 5 0 u

1 2

R lo a d

1 8 0

R 19 . 1 k

R 21 5 0 k

Q 1Q 2 S D 2 6 2 3

O U TR 3

0 . 8

U 1N J M 2 3 7 7

-IN

FB

GN

DO

UT

V+

CS

CT

RE

F

R t2 4 k

C t4 7 0 p FI C = 0

D 1H R U 0 3 0 2 A

0V +

5 V

0

I N

C o u t

2 2 0 u F

R s f1 6 0 k

C S4 . 7 u FI C = 0

0

R s r1 8 0 k

0

• VIN=5V

• VOUT=9V

• IOUT=50mA

• Vripple(P-P)= less than 30mV

• Efficiency= 75% at IOUT=50mA





2.1 DCDC コンバータによる昇圧回路4.1 Output Start-Up Voltage and Current

• Simulation result shows output start-up time of the circuit. This circuit needs 55ms to reach steady state.

Time

0s 20ms 40ms 60ms 80ms 90msV(OUT)

4V

5V

6V

7V

8V

9V

10VI(Rload)

20mA

30mA

40mA

50mA

SEL>>

V(OUT)

I(Rload)


2.1 DCDC コンバータによる昇圧回路4.2 Output Ripple Voltage

Time

60ms 65ms 70ms 75ms 80ms 85ms 90msV(OUT)

9.05V

9.06V

9.07V

9.08V

9.09V

9.10V

SEL>>

Time

89.90ms 89.91ms 89.92ms 89.93ms 89.94ms 89.95ms 89.96ms 89.97ms 89.98ms 89.99msV(OUT)

9.060V

9.065V

9.070V

9.075V

9.080V

• Simulation result shows output ripple voltage caused by switching(18mVP-P) and F.B loop oscillation(25mVP-P).

V(OUT)

V(OUT)[ZOOM] 18mVP-P

25mVP-P


2.1 DCDC コンバータによる昇圧回路4.3 Efficiency

• Efficiency of the converter at load IOUT=50mA is 75.5%. Time

70ms 75ms 80ms 85ms 90ms100*W(Rload)/rms(-W(V+))

0

25

50

75

100

(90.000m,75.500)Efficiency


2.1 DCDC コンバータによる昇圧回路4.4 Step-Load Response

• Simulation result shows the transient response of the circuit, when load currents are 50mA to 10mA to 50mA steps .

V(OUT)

I(L)

I(Load)

Time

60ms 65ms 70ms 75ms 80ms 85ms 90msV(OUT)

9.050V

9.075V

9.100V

9.125VI(L)

0A

100mA

200mA

I(I1)0A

20mA

30mA

40mA

50mA

SEL>>


2.1 DCDC コンバータによる昇圧回路5. Voltage and Current Simulation Result

• Simulation result shows voltage and current of the devices. • Select L and Cout that can handle their Irms value. • The absolute maximum value of Q1 and D1 are compared to simulation result for stress analysis.

Time

0s 20ms 40ms 60ms 80ms 90ms1 V(Cout:1) 2 rms(I(Cout))

0V

5V

10V1

0A

50mA

100mA2

SEL>>SEL>>

1 V(D1:2)- V(D1:1) 2 I(D1) avg(I(D1))

0V

10V

20V1

100mA

200mA

300mA2

>>

1 V(Q1:c) 2 I(Q1:c)0V

5V

10V

15V

20V1

250mA

500mA2

>>

I(L) rms(I(L))

0A

200mAI(L) peak, rmsI(L) = 261.054mA(peak) , 94.1399mA(rms)

V(Q1:C), I(Q1:C)

Q1 2SD2623: VCEO=20V, ICMAX=0.5A

V(D1:K,D1:A), IF(D1)

D1 HRU0302A: VRRM=20V, IO=0.3A(avg), IFSM=3A

V(Cout), I(Cout) rms

I(Cout) = 50.255mA(rms)

100% of Rated Value

100% of Rated Value


2.1 DCDC コンバータによる昇圧回路6.1 Bipolar Junction Transistor Losses

Time

89.964ms 89.966ms 89.968ms 89.970ms 89.972ms 89.974ms1 V(Q1:c) 2 I(Q1:c)

0V

5V

10V

15V

20V1

>>0A

100mA

200mA

300mA2

1 V(Q1:c)*I(Q1:c) 2 avg(W(Q1))0W

200mW

400mW

600mW1

SEL>>0W

50mW

100mW

150mW2

SEL>>

• Simulation result shows waveforms of IC and VCE of transistor Q1.Loss in peak and average values are also shown.

100% of Rated Value (PC, max.=150mW)

PC, avg.=17.254mW

turn-on loss

Conduction loss

turn-off loss

V(Q1:C), I(Q1:C)

P(Q1) peak, avg


2.1 DCDC コンバータによる昇圧回路6.2 Schottky Barrier Diode Losses

Time

89.964ms 89.965ms 89.966ms 89.967ms 89.968ms 89.969ms 89.970ms 89.971ms 89.972ms 89.973ms1 V(D1:1,D1:2) 2 I(D1)

-10V

-5V

0V

5V

10V1

-200mA

-100mA

0A

100mA

200mA2

SEL>>SEL>>

W(D1) avg(W(D1))-100mW

-50mW

0W

50mW

100mW

• Simulation result shows waveforms of IF and VAK of diode D1.Loss in peak and average values are also shown.

PD, avg.=18.45mW

Reverse recovery loss

Conduction loss

V(D1:A,D1:K), I(D1

P(D1) peak, avg

Reverse leakage loss

Reverse recovery characteristic


2.1 DCDC コンバータによる昇圧回路7.1 Start-Up Sequencing Waveforms

• Simulation result shows start-up sequencing waveforms, including V(OUT) and control signal (VRAMP, VOSC, and VFB).

V(OUT)

V(FB)

VOSC: V(CT)

VRAMP: V(CS)

Time

0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90msV(OUT)

5.0V

6.0V

7.0V

8.0V

9.0V

V(U1:CT) V(U1:CS) V(U1:FB)0V

0.5V

1.0V

1.5V

2.0V

2.5V

SEL>>



7.2 Switching Waveforms at Load 50 mA (RL=180)

• Simulation result shows boost converter switching waveforms at load 50mA, including IL, VC(Q1), IC(Q1), I(D1) and V(OUT)

I(D1)

I(L)

VC(Q1)

IC(Q1)

V(OUT)

Time

89.950ms 89.960ms 89.970ms 89.980ms89.944msV(OUT)

9.050V

9.075V

9.100V

SEL>>

I(D1)-50mA

0A50mA100mA150mA

1 V(Q1:c) 2 I(Q1:c)0V

2.5V5.0V7.5V10.0V

1

0A

100mA150mA200mA

2

>>

I(L)0A

50mA100mA150mA200mA


2.1 DCDC コンバータによる昇圧回路7.3 Switching Waveforms at Load 10 mA (RL=900)

• Simulation result shows boost converter switching waveforms at load 10mA, including IL, VC(Q1), IC(Q1), I(D1) and V(OUT)

I(D1)

I(L)

VC(Q1)

IC(Q1)

V(OUT)

Time

89.944ms 89.952ms 89.960ms 89.968ms 89.976ms 89.984msV(OUT)

9.075V

9.100V

9.125VI(D1)

-25mA

25mA50mA75mA

SEL>>

1 V(Q1:c) 2 I(Q1:c)-4V

4V8V12V

1

>>-25mA

0A25mA50mA75mA

2

I(L)-25mA

0A25mA50mA75mA


2.2 擬似共振電源回路

Design KitQuasi-Resonant Switching Power Supply using FA5541


2.2 擬似共振電源回路Contents

1. Quasi-Resonant Switching Power Supply 19V/5A

1.1 Output voltage

1.2 Output current

1.3 Output ripple voltage

1.4 Step-load response

2. Basic operation of switching power supply using FA5541

3. Start-up sequence simulation

4. Bridge diode peak current at start-up

5. Transformer

6. RCD Clamping network

7. Power MOSFET switching device

8. Schottky barrier diode D21 and D22 waveforms

9. Photocoupler


2.2 擬似共振電源回路1.Quasi-Resonant Switching Power Supply 19V/5A

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

D 2 1

Y G 8 6 5 C 1 5 R1

23

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 RL s

{N s p * N s p * L p }

1

2

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

C 12 2 0 u FI C = 1 3 9

K K 1

C O U P L I N G = 0 . 9 8K _ L in e a r

L 1 = L sL 2 = L pL 3 = L s u b

L s u b{N s u b p * N s u b p * L p }

1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 0

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

R S L 11 5 0 m

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 k

E S R 75 0 m

F B

I SR 1 31 0 0 k

0

C 33 3 u FI C = 1 0 . 1 9 9

F B

PARAMETERS:N p = 5 7

N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

IC=0/1

Z C D

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2

R p _ T10 . 1 5 0

C 22 2 0 0 p F

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

L E S L 71 2 n H

1

2

C 71 0 0 0 u F

V 1

F R E Q = 5 0 H zV A M P L = 1 4 1 . 4 2

C 1 21 0 0 0 p F

R L3 . 8 4

C 43 3 0 0 u F

E S R 44 0 m

L E S L 41 5 n H

1

2

C 53 3 0 0 u F

E S R 54 0 m

L E S L 51 5 n H

1

2

C 63 3 0 0 u F

E S R 64 0 m

L E S L 61 5 n H

1

2


2.2 擬似共振電源回路1.1 Output voltage

• Simulation result confirming that the output voltage would be 19 Volt at 5-A load. The result also shows that the circuit need 60ms to reach steady state.

Time

0s 20ms 40ms 60ms 80ms 100ms 120msV(VO_19V)

0A

5A

10A

15A

20A


2.2 擬似共振電源回路1.2 Output current

• Simulation result confirming that the output current would be 5 Amp. The result also shows that the circuit need 60ms to reach steady state.

Time

0s 20ms 40ms 60ms 80ms 100ms 120msI(RL)

0A

2.0A

4.0A

6.0A



• Simulation results shows the output ripple voltage at maximum current load (approximately 17.5mVP-P).

Time

107.56ms 107.58ms 107.60ms 107.62ms 107.64ms 107.66ms 107.68ms 107.70ms 107.72ms 107.74msV(VO_19V)

18.66V

18.67V

18.68V

18.69V

18.70V

1.3 Output ripple voltage


2.2 擬似共振電源回路1.4 Step-load response

• Simulation results shows waveform of the output voltage responding to stepping current 3/5A.

Time

16ms 18ms 20ms 22ms 24ms 25msV(VO_19V)

19.0V

18.5V

19.5V

SEL>>

I(IL)0A

4.0A

8.0A


2.2 擬似共振電源回路2.Basic operation of switching power supply using FA5541

• Power supply using FA5541 is switching using self-excited oscillation.• When IC turns the MOSFET ON ,drain current Id (primary current of T1) begins to rise from

zero. • V(IS pin) is voltage-converted from the Id current.

R E F

K

A

0

0

0OUT

ZCD

IS

FB

RZCD

CZCD

RS

0

M1

Cd

D1T1

0

0

+

Vds

-

ON

Id

+

V(RS) = Id*RS

-

OFF



Time

3.580ms 3.584ms 3.588ms 3.592ms 3.596ms 3.600ms 3.604ms 3.608ms 3.612ms-I(Lp)

0A

6AV(M1:1,M1:3)

0V

0.6KVV(IC1:OUT)

-1V

19V

SEL>>

• When Id reaches the reference level, FA5541 will turn M1 OFF

Id

Vds

VG

Id begins rising

M1 turns ON

Id reaches reference level

M1 turns OFF

VDS and winding voltage have step change



R E F

K

A

0

0

0OUT

ZCD

IS

FB

RZCD

CZCD

RS

0

M1

Cd

D1T1

0

0

• When M1 turns OFF ,and the winding voltage of the transformers has step change and IF(D1) is provided from the transformer into secondary side.

+

Vds

-

OFF

IF(D1)

ON

2.Basic operation of switching power supply using FA5541



Time

16.0us 20.0us 24.0us 28.0us 32.0us 36.0us 40.0us 44.0us12.8usV(IC1:ZCD)

0V

4.0VV(Lsub:1)

0V

-30V

30V

SEL>>

-I(Ls)0A

40A

• When IF(D1) gets zero, Vds drops rapidly due to resonance of transformers inductance and Cd. At the same time Vsub also drops rapidly.

• When V(ZCD) < Vth(of valley detection) ,FA5541 turns M1 ON again

IF(D1)

Id begins rising

IF(D1) is provided from the transformer into

secondary side

V(ZCD) < Vth, M1 turns ON

IF(D1) gets zero

VSUB

V(ZCD)

Vsub drops rapidly

Vth


2.2 擬似共振電源回路3.Start-up sequence simulation

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

C 49 9 0 0 u F

D 2 1

Y G 8 6 5 C 1 5 R

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 R

3300uFx3

L s{N s p * N s p * L p }

1

2

R L3 . 8 4

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

K K 1

C O U P L I N G = 1K _ L in e a r

L 1 = L sL 2 = L pL 3 = L s u b


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 0

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 kF B

I SR 1 31 0 0 k

0

F B


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

Z C D

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2C 2

2 2 0 0 p FR 25 6 k

V 1

F R E Q = 5 0V A M P L = 1 4 1 . 4 2

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

C 71 0 0 0 u

C 12 2 0 u F

C 33 3 u

C 1 21 0 0 0 p F

No parasitic elements and no initial condition is set

CVCC

Auxiliary winding



Time

0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms 100msV(IC1:OUT)

0V

4V

8V

12V

16V

SEL>>

V(IC1:VCC) 10.2 12.40V

4V

8V

12V

16V

VSTOFF

VCCON ,VSTRST1

VCC pin stop charging currentAuxiliary supply takes over

FA5541 turn onFA5541 turn off

t1 t2 t3

Total start-up time

VCC

OUT



FA5541 under voltage lockout (UVLO) characteristics (VCC pin)

ON threshold voltage: VCCON = 10.2V Startup circuit shutdown: VSTOFF = 12.4V Startup circuit reset voltage: VSTRST1 = 10.2V

t1,t2: VCC < VSTOFF ,startup circuit turns on ,VCC pin charges capacitor CVCC (C2).t2: VCC reaches VCCON ,FA5541 is turned ont3: after VCC reaches VSTOFF ,startup circuit turns off , VCC decreases until Auxiliary supply takes over.

D 2

D E R A 2 2 -0 2


1

2

I C 1F A 5 5 4 1

S S I C = 0

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

0

C 23 3 u

I(VCC)

I(Aux)



Time

0s 100msV(IC1:OUT)

0V

4V

8V

12V

16VV(IC1:VCC)

0V

4V

8V

12V

16V

SEL>>

• the simulation result shows the tradeoff between Total start-up time and Design margin, which is the difference of V(VCC) and VSTRST1 when the auxiliary winding takes over from the IC startup circuit.

• 33uF-CVCC is selected for higher Design margin although total start-up time is high.

CVCC=33uF

CVCC=22uF

Design margin (CVCC=22uF)

VSTRST1

Design margin (CVCC=33uF)

VCC (CVCC=22uF)

Total start-up time (CVCC=33uF)


2.2 擬似共振電源回路4.Bridge diode peak current at start-up

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

C 49 9 0 0 u F

D 2 1

Y G 8 6 5 C 1 5 R

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 R

3300uFx3


1

2

R L3 . 8 4

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

K K 1


L 1 = L sL 2 = L pL 3 = L s u b

V 1

F R E Q = 5 0V A M P L = 1 4 1 . 4 2


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 0

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 kF B

I SR 1 31 0 0 k

0

F B


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

Z C D

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2C 32 2 0 0 p F

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

C 71 0 0 0 u

C 12 2 0 u F

C 2{C v c c }

C 1 21 0 0 0 p F PARAMETERS:

C V C C = 3 3 u

No parasitic elements and no initial condition is set


2.2 擬似共振電源回路4.Bridge diode peak current at start-up

Time

0s 40ms 80ms 120msI(DBR1:2)

-12A

-8A

-4A

0A

4A

8A

12A

• Simulation result of the current through bridge rectifier diode DBR1 when the power supply is plug to the wall outlet. the peak current is approximately 9.8 which is less than Absolute maximum value IFSM from the datasheet.

I


2.2 擬似共振電源回路5.Transformer

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

C 49 9 0 0 u F

D 2 1

Y G 8 6 5 C 1 5 R

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 R

3300uFx3


1

2

R L3 . 8 4

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

K K 1


L 1 = L sL 2 = L pL 3 = L s u b

V 1

F R E Q = 5 0V A M P L = 1 4 1 . 4 2


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 1

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 k

I S

F B

R 1 31 0 0 k

0

F B


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

Z C D

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2C 32 2 0 0 p F

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

C 71 0 0 0 uI C = 1 8 . 7

C 12 2 0 u FI C = 1 3 9

C 23 3 uI C = 1 0 . 1 9 9

C 1 21 0 0 0 p FI C = 4 . 2

V+

V-

V+

V-

V+

V-

No parasitic elements



Time

0s 100us 200us 300us 400us 500usV(Lsub:1,Lsub:2)

0V

-20V

20V

SEL>>

V(Ls:1,Ls:2)

0V

-40V

40VV(Lp:2,Lp:1)

0V

-200V

200V

VP(t)

-VS(t)

-VSUB(t)

5.Transformer


2.2 擬似共振電源回路5.Transformer

• Lleak = LP(1-k2)

• LS/LP = N2

N : winding ratio of the transformer

VS = VP*(NS/NP)

VSUB = VP*(NSUB/NP)

• Transformer is modeled by using SPICE primitive k ,the transformer spec is Lp=360uH and Np:Ns:Nsub=57:10:8


2.2 擬似共振電源回路6.Transformer leakage inductance

I L5 A d c

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

D 2 1

Y G 8 6 5 C 1 5 R1

23

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 RL s

{N s p * N s p * L p }

1

2

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

C 12 2 0 u FI C = 1 3 9

K K 1

C O U P L I N G = {k }K _ L in e a r

L 1 = L sL 2 = L pL 3 = L s u b


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 1

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

R S L 11 5 0 m

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 k

E S R 75 0 m

I S

F B

R 1 31 0 0 k

0

F B

C 33 3 u FI C = 1 0 . 1 9 9


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

Z C D

IC=0/1

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2

R p _ T10 . 1 5 0

C 2{C c lp }

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

L E S L 71 2 n H

1

2

C 7

1 0 0 0 u FI C = 1 8 . 8

C 1 2

1 0 0 0 p FI C = 4 . 2

C 43 3 0 0 u FI C = 1 9 . 6 0

E S R 44 0 m

L E S L 41 5 n H

1

2

C 53 3 0 0 u F

E S R 54 0 m

L E S L 51 5 n H

1

2

C 63 3 0 0 u F

E S R 64 0 m

L E S L 61 5 n H

1

2

V 1

F R E Q = 5 0 H zV A M P L = 1 4 1 . 4 2

PARAMETERS:k = 0 . 9 8

C c lp = 2 2 0 0 p F

Parametric sweep “k”


2.2 擬似共振電源回路6.Transformer leakage inductance

• Transformer model using SPICE primitive k ,leakage inductance: Lleak = LP(1-k2)• LP=360uH ,leakage inductance is14.256uH for k=0.98 and 7.164uH for k=0.99• Check the VDS overshoot voltage versus the transformer leakage inductance.

Time

20us 40us 60us 80us 100us10us 110usV(M1:1)

0V

200V

400V

600V

Time

15.0us 20.0us 25.0us 30.0us 35.0us 40.0us12.8us 44.8usV(M1:1)

0V

200V

400V

600V

SEL>>

Design margin (Lleak=14.256uH)

M1: VDSS=600V

Design margin (Lleak=7.164uH)

M1: VDS(t) (Zoom)


2.2 擬似共振電源回路7.RCD Clamping network

I L5 A d c

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

D 2 1

Y G 8 6 5 C 1 5 R1

23

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 RL s

{N s p * N s p * L p }

1

2

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

C 12 2 0 u FI C = 1 3 9

K K 1

C O U P L I N G = {k }K _ L in e a r

L 1 = L sL 2 = L pL 3 = L s u b


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 1

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

R S L 11 5 0 m

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 k

E S R 75 0 m

I S

F B

R 1 31 0 0 k

0

F B

C 33 3 u FI C = 1 0 . 1 9 9


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

Z C D

IC=0/1

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2

R p _ T10 . 1 5 0

C 2{C c lp }

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

L E S L 71 2 n H

1

2

C 7

1 0 0 0 u FI C = 1 8 . 8

C 1 2

1 0 0 0 p FI C = 4 . 2

C 43 3 0 0 u FI C = 1 9 . 6 0

E S R 44 0 m

L E S L 41 5 n H

1

2

C 53 3 0 0 u F

E S R 54 0 m

L E S L 51 5 n H

1

2

C 63 3 0 0 u F

E S R 64 0 m

L E S L 61 5 n H

1

2

V 1

F R E Q = 5 0 H zV A M P L = 1 4 1 . 4 2

PARAMETERS:k = 0 . 9 8

C c lp = 2 2 0 0 p F

Parametric sweep “Cclp”


2.2 擬似共振電源回路7.RCD Clamping network

Time

0s 20us 40us 60us 80us 100usV(M1:1)

0V

200V

400V

600V

Time

20.0us 25.0us 30.0us 35.0us 40.0us 45.0us15.5usV(M1:1)

0V

200V

400V

600V

SEL>>

• Compare VDS overshoot of the circuit with CCLP(C2) = 220pF and 2200pF ,larger CCLP value get better design margin for MOSFET VDS

• CCLP=2200uF is selected for the better M1: VDS design margin.

M1: VDS(t)

Design margin (CCLP=C2=2200pF)

M1: VDSS=600V

Design margin (CCLP=C2=220pF) M1: VDS(t) (Zoom)


2.2 擬似共振電源回路8.Power MOSFET switching device

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

D 2 1

Y G 8 6 5 C 1 5 R1

23

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 RL s

{N s p * N s p * L p }

1

2

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

C 12 2 0 u FI C = 1 3 9

K K 1

C O U P L I N G = 0 . 9 8K _ L in e a r

L 1 = L sL 2 = L pL 3 = L s u b


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 1

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

R S L 11 5 0 m

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 k

E S R 75 0 m

I S

F B

R 1 31 0 0 k

0

C 33 3 u FI C = 1 0 . 1 9 9

F B


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

IC=0/1

Z C D

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2

R p _ T10 . 1 5 0

C 22 2 0 0 p F

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

L E S L 71 2 n H

1

2

C 7

1 0 0 0 u FI C = 1 8 . 8

C 1 2

1 0 0 0 p FI C = 4 . 2

I L5 A d c

C 43 3 0 0 u FI C = 1 9 . 6 1

E S R 44 0 m

L E S L 41 5 n H

1

2

C 53 3 0 0 u F

E S R 54 0 m

L E S L 51 5 n H

1

2

C 63 3 0 0 u F

E S R 64 0 m

L E S L 61 5 n H

1

2

V 1

F R E Q = 5 0 H zV A M P L = 1 4 1 . 4 2



Time

0s 20ms 40ms 60ms 80ms 100ms 120ms1 V(M1:1) 2 I(M1:1)

0V

250V

500V1

0A

25A

-15A

2

>>

Time

119.90ms 119.92ms 119.94ms 119.96ms 119.98ms 120.00ms1 V(M1:1) 2 I(M1:1)

-200V

0V

200V

400V

600V1

-2.0A

0A

2.0A

4.0A

6.0A2

SEL>>SEL>>

• Simulation results shows the peak value of M1: VDS and ID .

10usec. / Div.

VDS(t) ID(t)

VDS(t)

ID(t)

20msec. / Div.

Peak value

Peak value



Time

19.57ms 19.58ms 19.59ms 19.60ms 19.61ms 19.62ms 19.63ms 19.64ms 19.65ms 19.66ms1 V(M1:1) 2 I(M1:1) 3 V(M1:2)

-600V

-400V

-200V

0V

200V

400V

600V1

-6.0A

-2.0A

0A

2.0A

4.0A

6.0A2

SEL>>0V

50V3

SEL>>

1 W(M1) 2 AVG(W(M1))-0.5KW

0W

0.5KW

1.0KW

1.5KW1

0W

2.5W

5.0W

7.5W

10.0W2

>>

• Simulation results shows the peak value of MOSFET VDS and ID . Calculated switching power loss and average power loss are also shown

10usec. / Div.

M1 Power Loss

M1 Power Lossavg

VDS(t) ID(t)

Peak value

VGS(t)


2.2 擬似共振電源回路9.Schottky barrier diode D21 and D22 waveforms

Time

0s 20ms 40ms 60ms 80ms 100ms 120ms1 -I(Ls) 2 V(D22:2,D22:3)

20A

40A

-5A

1

SEL>> 0V

40V

80V2

SEL>>

Time

119.92ms 119.93ms 119.94ms 119.95ms 119.96ms 119.97ms 119.98ms 119.99ms1 -I(Ls) 2 V(D22:2,D22:3)

50A

-10A

1

>>0V

50V2

• Simulation results shows the peak value of SBD: VKA and IF .

10usec. / Div.

IF(t)VKA(t)

IF(t)

VKA(t)

20msec. / Div.

Peak value

Peak valuePeak

value


2.2 擬似共振電源回路9.Schottky barrier diode D21 and D22 waveforms

Time

19.57ms 19.58ms 19.59ms 19.60ms 19.61ms 19.62ms 19.63ms 19.64ms 19.65ms 19.66ms-I(LS) V(D22:2,D22:3)

-50

-25

0

25

50

SEL>>

1 W(D21)+ W(D22) 2 AVG(W(D21)+ W(D22))-40W

0W

40W1

-5.0W

0W

5.0W2

>>

• Simulation results shows the peak value of SBD VKA and IF . Calculated power loss and average power loss are also shown

10usec. / Div.

SBD Power Loss SBD Power Lossavg

VKA(t)IF(t)

Peak valuePeak

value


2.2 擬似共振電源回路10.Photocoupler

V

I

V-

V+

D 1D E R A 3 8 -0 6

D 2

D E R A 2 2 -0 2

R E F

K

A

S R 1TA 7 6 4 3 2 F

D 2 1

Y G 8 6 5 C 1 5 R1

23

C 1 00 . 0 1 u F

D 2 2Y G 8 6 5 C 1 5 RL s

{N s p * N s p * L p }

1

2

L 14 . 7 u H

1 2 V O _ 1 9 V

C _ T1

2 2 0 0 p F

0

100V/50Hz

C 12 2 0 u FI C = 1 3 9

K K 1


L 1 = L sL 2 = L pL 3 = L s u b


1

2

P C 1TL P 2 8 1

I C 1F A 5 5 4 1

S S I C = 1

Z C D

F B

I S

G N D O U T

V C C

N C

V H

R 1 24 . 7

R 84 . 7 k

R 1 41 0 0

R S L 11 5 0 m

C 1 14 7 0 0 p F

C 1 32 2 p F

R 31 3 k

R 41 5 k

C 82 2 0 0 p F

C 90 . 0 1 u FR 5

1 0 k

R 61 0 k

R 72 k

R 17 . 5 k

R 1 52 0 0 k

E S R 75 0 m

I S

F B

R 1 31 0 0 k

0

C 33 3 u FI C = 1 0 . 1 9 9

F B


N s = 1 0

L p = 3 6 0 u H

N s u b = 8

N s p = {N s / N p }

N s u b p = {N s u b / N p }

IC=0/1

Z C D

C d2 2 0 p F

19V / 0 to 5A

L p{L p }

1

2

R p _ T10 . 1 5 0

C 22 2 0 0 p F

R 25 6 k

R s n s0 . 2 2

R 1 01 0

R 1 11 0 0

0

D B R 1D 3 S B 8 0

D 3D 1 N L 2 0 U _ S

C 1 4

4 7 0 0 p F

D 4

D 1 N L 2 0 U _ S

M 12 S K 3 6 8 1 -0 1 S

C 7

1 0 0 0 u FI C = 1 8 . 9

C 1 2

1 0 0 0 p FI C = 4 . 2

I L5 A d c

C 49 9 0 0 u FI C = 1 9 . 6 6 5

E S R 41 3 . 3 m

3300uFx3

V 1

F R E Q = 5 0 H zV A M P L = 1 4 1 . 4 2

No parasitic elements: Lleak and ESL ,to aid simulation convergence


2.2 擬似共振電源回路10.Photocoupler

Time

0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20msV(VO_19V)

18V

19V

20VV(PC1:A,PC1:K)

0V

1.0V

SEL>>

Time

2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms1 I(PC1:C) 2 V(FB)

-12uA

380uA1

>>0V

2.5V

5.0V2

• When power supply output reaches spec voltage (19V) ,a shunt regulator draws current through resistor (R6) and VAK of photocoupler increases.

• When VAK turns on photocoupler, collector current Ic increases. This causes FB pin voltage to decreases before power supply output voltage go to the stable state.

2msec. / Div.

IC (photocoupler)V(FB pin)

VAK (photocoupler)

2msec. / Div.

VO_19V(t)

VAK turns on the photocoupler

VO stable at 19V


Engineering

Spiceを活用した電源回路シミュレーションセミナーテキスト 18 feb2015