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ADissertation Presentation
on
Reconfigurable PLC Development, Synthesis & Implementation for Industrial Application
8 October 2016
Presented ByMr. Paramveer TeliM.Tech II(Electronics Technology)
Guided byProf. P. C. BhaskarAssociate Professor
Department of Technology,Shivaji University, Kolhapur
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Contents
1. Introduction 2. Problem Formulation3. Objectives of the Proposed System4. Theory and Concept
1. PicoBlaze microcontroller2. Why the PicoBlaze microcontroller?3. Advantages of PLC designed using FPGA4. Water Level Monitoring And Control System
5. System Implementation 6. Results7. Conclusion8. Paper Publications9. References
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What is PLC?
• Digital computer designed for multiple inputs and outputs arrangements
• Basic building block of any industrial automation system
• Works in extended temperature ranges, immune to electrical noise, and has
resistance to vibration and impact.
• Real Time System
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Major Components of a Common PLC
PROCESSOR
POWERSUPPLY
I MN O P D U UT L E
O M U OT DP UU LT E
PROGRAMMING DEVICE
From SENSORSPushbuttons,
contacts,limit switches,
etc.
ToOUTPUT
Solenoids, contactors,
alarmsetc.
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PLC Operation Sequence
1. Self testTesting of its own hardware and software for faults
2. Input scanReading the inputs and copying their values into memory
3. Logic solve/scanUsing inputs, the ladder logic program is solved and outputs are updated into memory
4. Output scanWhile solving logic the output values are updated only in memory, output scan will be actually update the outputs using temporary values in memory
Input scan
Logic scan
Output scan
Self test
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What is a Ladder Diagram
A Ladder diagram is a symbolic and schematic representation of both the process hardware and process control.
Its called a ‘Ladder’ because all the devices are connected across the supply lines making it look like a ladder.
Each parallel connection is called a ‘Rung’, it can contain many inputs but only one output.
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Problem Formulation1. Performance of the traditional PLC is restricted by the
Length of ladder diagram Speed of the microprocessor Cyclic scan period
2. PLC program is easy to duplicate and analyze. This often results in the leakage of valuable trade secrets and the rise of clone products
3. Design threats to conventional PLC
Reverse Engineering: Taking an existing product, third parties can probe a design by looking at the layout, the devices used, downloading the firmware, and analyzing the interaction between devices
Cloning: building copies of an existing product Tampering: When an outside agent attempts to gain unauthorized access to an electronic
system, it is referred to as tampering8 October 2016 [email protected]
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4. It is difficult to implement complex control functions on conventional PLC
5. It is difficult to adapt to the requirements of high-speed control in modern industry
6. Finding out a way to realize high-speed PLC is becoming more and more important
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7. Implementing PLC on FPGA platform has advantage of
Improved execution speed of control logic Reduced cyclic scan period Faster response to input Better design security Protection from design threats Freedom of reconfiguration Easy to customize design as per the requirement Large I/O’s available Possible to implement complex control functions Easy to upgrade
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Objectives
1) To design and implement FPGA based Reconfigurable PLC
2) To design control & monitoring system modules on FPGA
3) To design GUI for monitoring and controlling Reconfigurable PLC
4) To develop highly secured PLC design using FPGA
5) To achieve optimized and High Speed PLC using FPGA
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PicoBlaze Microcontroller Features
1. Only 26 Slices plus program memory (BRAM)
2. Performance: 52 MIPS to 120 MIPS depending on device family and clock rate
3. Programs up to 4K instructions
4. 32 General Purpose Registers arranged in 2 banks of 16 Registers
5. 256 General Purpose Input Ports
6. 256 General Purpose Output Ports
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7. 64-bytes of scratch pad memory expandable to 128 and 256-bytes
8. Fully automatic CALL/RETURN stacks supporting nested subroutines to 30 levels
9. Power saving features including 'sleep' mode.
10. Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-II Pro FPGA
11. Assembler & instruction-set simulator support
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Why the PicoBlaze Microcontroller?
1. Specifically designed and optimized for the spartan-3 , spartan-6, and virtex-6 FPGA architectures
2. Resource efficient : consumes considerably less FPGA resources than comparable 8-bit microcontroller architectures within an FPGA
3. Provided as a free, source-level VHDL file with royalty-free re-use within Xilinx FPGAs
4. Can be retargeted to future generations of Xilinx FPGAs
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5. Fully embedded in the FPGA with flexible, extensive on-chip connectivity to other FPGA resources
6. Signals remain within the FPGA, improving overall performance
7. Reduces system cost because it is a single-chip solution, integrated within the FPGA
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Advantages of PLC designed using FPGA1. Short Product Development Cycle
Use of Standard HDLs
Engineers can try out various types of implementations within short time, so product
development time is reduced significantly
2. Flexibility Easy to upgrade the PLC designs
3. Very High Speed Performance FPGA performs all tasks in parallel
Conventional PLC performs all the tasks sequentially
4. Encryption Techniques FPGA ‘s provide design security by Bitstream encryption (256 bit AES key)
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Software Requirements
Xilinx ISE 14.2 Design Suite (Reconfigurable PLC Design)
KCPSM6 Assembler (PicoBlaze Assembly Code Development)
JTAG Loader Utility (Reconfiguration)
Visual Studio 2010 Software (Graphical User Interface)
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Hardware Requirements
ML605 Evaluation Board (Virtex 6)
UART cable
Personal Computer with following software's installed
Xilinx ISE 14.2 Design Suite Visual Studio 2010 Setup
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Proposed System Development Flowchart
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Design of PLC Top Module
Design of Input Module, Core Module and Output Module
Design of Communication Module
Design of Water Level Monitoring and Control System
Design of Graphical User Interface (GUI )
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Continued…Proposed System Development Flowchart
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Programming PLC Modules
Implementing Design on Virtex6 FPGA( ML 605 Evaluation Board)
Making Design Reconfigurable with JTAG Loader Utility
System Monitoring and Control with GUI
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Design of Graphical User Interface (GUI) for Water Level Monitoring and Control System.
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Generating Programming File
To Run the Generate Programming File Process1. In the View pane of the Design panel, select
Implementation. 2. In the Hierarchy pane, select the top module 3. In the Processes pane, double-click
Generate Programming File.
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Generate Programming FileProcess Properties
In the Processes pane, right-click the Generate Programming File process, and select Process Properties to set properties for the process in the following dialog boxes. Configuration Options Readback Options Encryption Options
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Managing Configuration Project (iMPACT) Process
1. Open the Boundary Scan Window Double-click on Boundary Scan in the iMPACT Flows panel.
2. Initialize the Boundary-Scan ChainRight-click in the Workspace and select Initialize Chain.
3. Programming a Device1. Click on a device to select it2. Select Operations > Program, or right-click on the device icon and select
Program.
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JTAG Loader for Reconfiuration
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1. Prepare the program memory in design for JTAG loader by enabling JTAG loader.2. Generate the configuration BIT file for design and configure the target device using
iMPACT and JTAG.3. Copy the ‘JTAG Loader’ executable to working directory
Working Directory: C:Xilinx\14.2\ISE_DS\ISE\bin\nt4. Open the ‘ISE Design Suite Command Prompt’ and navigate to working directory.5. Modifying ‘core_rom.psm’ as per the changes required in existing design.6. Generating the HEX file7. Copy the ‘core_rom.hex’ file to working directory8. Downloading New Program with JTAG loader utility
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Navigating to working directory
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Working Directory: C:Xilinx\14.2\ISE_DS\ISE\bin\nt
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Generating the HEX file
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1. Modify core_rom.psm as per the required changes in the existing program2. Run KCPSM6 assembler to generate core_rom.hex file3. Copy core_rom.hex file to working directory
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Downloading New Program
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Run JTAG Loader again but this time specifying the name of the HEX file to be loaded into the Core Module's program memory.
jtagloader -l core_rom.hex
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JTAG Loader Screen
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Simulation of PLC (Top Module)
Working of PLC is tested by implementing Water Level Monitoring and Control System
There are five cases for this system1. Overhead tank is empty2. Overhead tank is full3. Both tanks empty4. Sensor error5. Dry run error
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SimulationCase 1: Overhead Tank is Empty
(OH_HL=0, OH_LL=1, UG_LL=0)
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SimulationCase 2: Overhead Tank is Full
(OH_HL=1, OH_LL=0, UG_LL=0)
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Conclusion
1. This work represents FPGA based Reconfigurable PLC
2. This PLC has advantage of supporting high speed parallel execution and hardware configuration
3. Cyclic scan period is significantly reduced, therefore faster response to input changes
4. In traditional PLC, input scan, logic solve and output scan phases are executed in sequence, but in this reconfigurable PLC these phases are executed in parallel, by implementing separate hardware for each phase.
5. In this PLC, cyclic scan period depends only on core module, therefore again reducing cyclic scan period.
6. This PLC is Reconfigurable, easy to update PLC control programs
7. It takes just 10 seconds to reconfigure new PLC program
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8. On board programming
9. Easy to upgrade PLC design for future requirements.
10. Large I/O’s available
11. Complex control functions can be implemented
12. Provides design security by Bitstream encryption
13. Protects from design threats
14. Graphical user interface provides better visual control over PLC operations.
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Paper Publications
1. “A Review on Reconfigurable PLC Development, Synthesis & Implementation for Industrial Application”, Paramveer Teli, P.C. Bhaskar, IJSRD (International Journal for Scientific Research and Development), Volume 3, Issue 12, Feb 2016.
2. “Reconfigurable PLC Development, Synthesis & Implementation for Industrial Application”, Paramveer Teli, P.C. Bhaskar, IJSRD (International Journal for Scientific Research and Development)
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References
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[5] Daoshan Du, Yadong Liu, Xingui Guo, Kazuo Yamazaki and Makoto Fujishima. Study on LDVHDL conversion for FPGA-based PLC implementation. Int J Adv Manuf Technol, vol. 40, pp.1181~1190, 2009.
[6] Ichikawa Shuichi, Akinaka Masanori, Hata Hisashi, Ikeda Ryo, Yamamoto Hiroshi. An FPGA implementation of hard-wired sequence control system based on PLC software. IEEJ Transactions on Electrical and Electronic Engineering, vol. 6, pp. 367–375, 2011.
[7] Shanta S, Dipali S. A new generation of PLC - an FPGA based PLC. Proceedings of the SICE annual conference, Okayama, Japan, pp. 2367-2370, 2005
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[11] M. Wegrzyn, M.A. Adamski, and J.L. Monteiro, “The application of reconfigurable logic to controller design,” Control Engineering Practice, vol.6, pp.879–887, 1998.
[12] A. Wegrzyn and M. Wegrzyn, “Petri net-based specification, analysis and synthesis of logic controllers,” Proc. IEEE Int’l Symp. Industrial Electronics (ISIE 2000), pp.20–26, 2000
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[15] D. Du, Y. Liu, X. Guo, K. Yamazaki, and M. Fujishima, “Study on LDVHDL conversion for FPGA-based PLC implementation,” International Journal of Advanced Manufacturing Technology, vol.40, pp.1181–1190, 2009.
[16] C. Economakos and G. Economakos, “FPGA implementation of PLC programs using automated high-level synthesis tools,” Proc. IEEE Int’l Symp. Industrial Electronics (ISIE 2008), pp.1908–1913, 2008.
[17] C. Economakos and G. Economakos, “Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis,” Proc. IEEE Int’l Conf. Emerging Technologies and Factory Automation (ETFA 2008), pp.1002–1009, 2008
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[19] Mitsubishi Electric Corp., Programming Manual II: The FX series of programmable controller (FX1S/FX1N/FX2N/FX1NC/FX2NC), April 2003. JY992D88101 rev. D.
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